Datasheet X9250 Datasheet (intersil)

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X9250

Low Noise/Low Power/SPI Bus/256 Taps

Data Sheet FN8165.3August 29, 2006

Quad Digitally Controlled Potentiometers (XDCP™)

FEATURES

• Four potentiometers in one package

• 256 resistor taps/pot - 0.4% resolution

• SPI serial interface

• Wiper resistance, 40Ω typical @ V

• Four nonvolatile data registers for each pot

• Nonvolatile storage of wiper position

• Standby current < 5µA max (total package)

• Power supplies —V

= 2.7V to 5.5V

—V+ = 2.7V to 5.5V —V– = -2.7V to -5.5V

• 100kΩ, 50kΩ total pot resistance

• High reliability —Endurance – 100,000 data changes per bit per

—Register data retention - 100 years

• 24 Ld SOIC, 24 Ld TSSOP

• Dual supply version of X9251

• Pb-free plus anneal available (RoHS compliant)

= 5V

DESCRIPTION

The X9250 integrates 4 digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit.

The digitally controlled potentiometer is implemented using 255 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and 4 nonvolatile Data Registers (DR0:DR3) that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Power up recalls the contents of DR0 to the WCR.

The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.

BLOCK DIAGRAM

HOLD

SCK

A0 A1

V+

V-

Interface

and

Control

Circuitry

Data

Pot 0

R0R

Wiper

Counter Register

(WCR)

Wiper Counter Register

(WCR)

Resistor

Array

Pot1

R2R

R0R

R2R

VH0/R

VL0/R

VW0/R

VW1/R

H1/RH1

VL1/R

R0R

R2R

R0R

R2R

Wiper

Counter Register

(WCR)

Wiper

Counter

(WCR)

Resistor

Array Pot 2

Resistor

Array Pot 3

H2/RH2

VL2/R

VW2/R

VW3/R

H3/RH3

VL3/R

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

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Ordering Information

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X9250

PART

PART NUMBER

X9250TS24I X9250TS I 5 ±10% 100 -40 to +85 24 Ld SOIC (300 mil) M24.3 X9250TS24IZ (Note) X9250TS ZI -40 to +85 24 Ld SOIC (300 mil)

X9250TV24I X9250TV I -40 to +85 24 Ld TSSOP

X9250TV24IZ (Note) X9250TV ZI -40 to +85 24 Ld TSSOP

X9250US24 X9250US 50 0 to +70 24 Ld SOIC (300 mil) M24.3 X9250US24Z (Note) X9250US Z 0 to +70 24 Ld SOIC (300 mil)

X9250US24I X9250US I -40 to +85 24 Ld SOIC (300 mil) M24.3 X9250US24IZ (Note) X9250US ZI -40 to +85 24 Ld SOIC (300 mil)

X9250UV24I X9250UV I -40 to +85 24 Ld TSSOP

X9250UV24IZ (Note) X9250UV ZI -40 to +85 24 Ld TSSOP

X9250TS24-2.7 X9250TS F -2.7 to 5.5 100 0 to +70 24 Ld SOIC (300 mil) M24.3 X9250TS24Z-2.7 (Note) X9250TS ZF 0 to +70 24 Ld SOIC (300 mil)

X9250TS24I-2.7* X9250TS G -40 to +85 24 Ld SOIC (300 mil) M24.3 X9250TS24IZ-2.7*

(Note) X9250TV24I-2.7 X9250TV G -40 to +85 24 Ld TSSOP

X9250TV24IZ-2.7 (Note) X9250TV ZG -40 to +85 24 Ld TSSOP

X9250US24-2.7* X9250US F 50 0 to +70 24 Ld SOIC (300 mil) M24.3 X9250US24Z-2.7* (Note) X9250US ZF 0 to +70 24 Ld SOIC (300 mil)

X9250US24I-2.7 X9250US G -40 to +85 24 Ld SOIC (300 mil) M24.3 X9250US24IZ-2.7 (Note) X9250US ZG -40 to +85 24 Ld SOIC (300 mil)

X9250UV24-2.7 X9250UV F 0 to +70 24 Ld TSSOP

X9250UV24Z-2.7 (Note) X9250UV ZF 0 to +70 24 Ld TSSOP

X9250UV24I-2.7 X9250UV G -40 to +85 24 Ld TSSOP

X9250UV24IZ-2.7 (Note) X9250UV ZG -40 to +85 24 Ld TSSOP

*Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

MARKING VCC LIMITS (V)

X9250TS ZG -40 to +85 24 Ld SOIC (300 mil)

POTENTIOMETER

ORGANIZATION (kΩ)

TEMP. RANGE

(°C) PACKAGE PKG . DWG. #

M24.3

(Pb-free)

MDP0044

(4.4mm)

MDP0044

(4.4mm) (Pb-free)

M24.3

(Pb-free)

M24.3

(Pb-free)

MDP0044

(4.4mm)

MDP0044

(4.4mm) (Pb-free)

M24.3

(Pb-free)

M24.3

(Pb-free)

MDP0044

(4.4mm)

MDP0044

(4.4mm) (Pb-free)

M24.3

(Pb-free)

M24.3

(Pb-free)

MDP0044

(4.4mm)

MDP0044

(4.4mm) (Pb-free)

MDP0044

(4.4mm)

MDP0044

(4.4mm) (Pb-free)

FN8165.3

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X9250

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PIN DESCRIPTIONS

Serial Output (SO)

SO is a serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock.

Serial Input

SI is the serial data input pin. All opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. Data is latched by the rising edge of the serial clock.

Serial Clock (SCK)

The SCK input is used to clock data into and out of the X9250.

Chip Select (CS

When CS

is HIGH, the X9250 is deselected and the

)

SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS

LOW enables the X9250, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS

required prior to the start of any operation.

Hold (HOLD

HOLD

)

is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD

may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD

must be brought LOW while SCK is LOW. To resume communication, HOLD

is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times.

Device Address (A

- A1)

The address inputs are used to set the least significant 2 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9250. A maximum of 4 devices may occupy the SPI serial bus.

Potentiometer Pins

H/RH

L3/RL3

The R

(VH0/R

)

and RL pins are equivalent to the terminal

- VH3/RH3), VL/RL (VL0/R

connections on a mechanical potentiometer.

W/RW

(VW0/R

W0 - VW3/RW3

)

The wiper pins are equivalent to the wiper terminal of a mechanical potentiometer.

Hardware Write Protect Input (WP

The WP

pin when LOW prevents nonvolatile writes to

)

the Data Registers.

Analog Supplies (V+, V-)

The analog supplies V+, V- are the supply voltages for the XDCP analog section.

PIN CONFIGURATION

SOIC/TSSOP

W3/RW3

VH3/R

L3/RL3

VL0/R

VH0/R

VW0/R

V+

X9250

HOLD

SCK

L2/RL2

VH2/R

VW2/R

V–

VW1/R

VH1/R

VL1/R

PIN NAMES

Symbol Description

SCK Serial Clock

SI, SO Serial Data

0-A1

H0/RH0–VH3/RH3

L0/RL0–VL3/RL3

W0/RW0–VW3/RW3

Device Address

Potentiometer Pins (terminal equivalent)

Potentiometer Pins (wiper equivalent)

Hardware Write Protection

V+,V- Analog Supplies

System Supply Voltage

System Ground

NC No Connection

FN8165.3

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X9250

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DEVICE DESCRIPTION

Serial Interface

The X9250 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked in on the rising SCK. CS LOW and the HOLD during the entire operation.

The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count.

Array Description

The X9250 is comprised of four resistor arrays. Each array contains 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (V

At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (V switch may be turned on at a time.

These switches are controlled by a Wiper Counter Register (WCR). The 8 bits of the WCR are decoded to select, and enable, one of 256 switches.

) output. Within each individual array only one

W/RW

and WP pins must be HIGH

and VL/RL inputs).

H/RH

must be

Wiper Counter Register (WCR)

The X9250 contains four Wiper Counter Registers, one for each XDCP potentiometer. The WCR is equivalent to a serial-in, parallel-out register/counter with its outputs decoded to select one of 256 switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated Data Registers via the XFR Data Register or Global XFR Data Register instructions (parallel load); it can be modified one step at a time by the increment/decrement instruction. Finally, it is loaded with the contents of its Data Register zero (DR0) upon power-up.

The Wiper Counter Register is a volatile register; that is, its contents are lost when the X9250 is powereddown. Although the register is automatically loaded with the value in R0 upon power-up, this may be different from the value present at power-down.

Data Registers

Each potentiometer has four 8-bit nonvolatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the associated Wiper Counter Register. All operations changing data in one of the Data Registers is a nonvolatile operation and will take a maximum of 10ms.

If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data.

Data Register Detail

(MSB) (LSB)

D7 D6 D5 D4 D3 D2 D1 D0

NV NV NV NV NV NV NV NV

FN8165.3

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Figure 1. Detailed Potentiometer Block Diagram

www.BDTIC.com/Intersil

(One of Four Arrays)

X9250

Serial Data Path

From Interface

Circuitry

If WCR = 00[H] then VW/RW = VL/R

If WCR = FF[H] then V

W/RW

= VH/R

Modified SCK

Write in Process

The contents of the Data Registers are saved to nonvolatile memory when the CS

pin goes from LOW to HIGH after a complete write sequence is received by the device. The progress of this internal write operation can be monitored by a write in process bit (WIP). The WIP bit is read with a read status command.

Serial Bus

UP/DN

Input

Parallel Bus Input

Wiper

Counter

(WCR)

Inc/Dec

Logic

UP/DN

CLK

C o u n

D e c o d e

Figure 2. Identification Byte Format

Device Type

Identifier

100

VH/R

VL/R

VW/R

0 0 A1 A0

Device Address

INSTRUCTIONS

Identification (ID) Byte

The first byte sent to the X9250 from the host, following a CS

going HIGH to LOW, is called the Identification byte. The most significant four bits of the slave address are a device type identifier, for the X9250 this is fixed as 0101[B] (refer to Figure 2).

The two least significant bits in the ID byte select one of four devices on the bus. The physical device address is defined by the state of the A

- A1 input

pins. The X9250 compares the serial data stream with the address input state; a successful compare of both address bits is required for the X9250 to successfully continue the command sequence. The A

- A1 inputs

can be actively driven by CMOS input signals or tied to

or VSS.

The remaining two bits in the slave byte must be set to 0.

Instruction Byte

The next byte sent to the X9250 contains the instruction and register pointer information. The four most significant bits are the instruction. The next four bits point to one of the four pots and, when applicable, they point to one of four associated registers. The format is shown below in Figure 3.

Figure 3. Instruction Byte Format

Select

I1I2I3 I0 R1 R0 P1 P0

Instructions

Pot Select

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FN8165.3

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X9250

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The four high order bits of the instruction byte specify the operation. The next two bits (R one of the four registers that is to be acted upon when a register oriented instruction is issued. The last two bits (P1 and P potentiometers is to be affected by the instruction.

Four of the ten instructions are two bytes in length and end with the transmission of the instruction byte. These instructions are:

– XFR Data Register to Wiper Counter Register

transfers the contents of one specified Data Register to the associated Wiper Counter Register.

– XFR Wiper Counter Register to Data Register

transfers the contents of the specified Wiper Counter Register to the specified associated Data Register.

– Global XFR Data Register to Wiper Counter Regiter

This transfers the contents of all specified Data Registers to the associated Wiper Counter Registers.

– Global XFR Wiper Counter Register to Data Regiter

This transfers the contents of all Wiper Counter Registers to the specified associated Data Registers.

The basic sequence of the two byte instructions is illustrated in Figure 4. These two-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by t from the WCR (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of t between one of the four potentiometers and one of its associated registers; or it may occur globally, where the transfer occurs between all potentiometers and one associated register.

) selects which one of the four

to complete. The transfer can occur

and R0) select

—This

. A transfer

WRL

—

Five instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9250; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are:

– Read Wiper Counter Register

wiper position of the selected pot,

– Write Wiper Counter Register

wiper position of the selected pot,

– Read Data Register

selected data register;

– Write Data Register

selected data register.

– Read Status

of the WIP bit which indicates if the internal write cycle is in progress.

The sequence of these operations is shown in Figure 5 and Figure 6.

The final command is Increment/Decrement. It is different from the other commands, because it’s length is indeterminate. Once the command is issued, the master can clock the selected wiper up and/or down in one resistor segment steps; thereby, providing a fine tuning capability to the host. For each SCK clock pulse

) while SI is HIGH, the selected wiper will move

HIGH

one resistor segment towards the V Similarly, for each SCK clock pulse while SI is LOW, the selected wiper will move one resistor segment towards the V sequence and timing for this operation are shown in Figure 7 and Figure 8.

—This command returns the contents

L/RL

—read the contents of the

—write a new value to the

terminal. A detailed illustration of the

—read the current

—change current

terminal.

H/RH

FN8165.3

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Figure 4. Two-Byte Instruction Sequence

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SCK

010100A1A0 I3 I2 I1 I0 R1 R0 P1 P0

Figure 5. Three-Byte Instruction Sequence (Write)

SCL

X9250

0 1 0 1 A1 A0 I3 I2 I1 I0 R1 R0 P1 P0

Figure 6. Three-Byte Instruction Sequence (Read)

SCL

0 1 0 1 A1 A0 I3 I2 I1 I0 R1 R0 P1 P0

Figure 7. Increment/Decrement Instruction Sequence

SCK

D7 D6 D5 D4 D3 D2 D1 D0

Don’t Care

D7 D6 D5 D4 D3 D2 D1 D0

010100A1A0 I3 I2 I1 I0 0

D E C n

FN8165.3

August 29, 2006

Page 8

Figure 8. Increment/Decrement Timing Limits

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SCK

X9250

WRID

VW/R

INC/DEC CMD Issued

Voltage Out

Table 1. Instruction Set

Instruction Set

Instruction

Read Wiper Counter Register

Write Wiper Counter Register

3I2I1I0R1R0

10010 0P1P0Read the contents of the Wiper Counter

10100 0P1P0Write new value to the Wiper Counter Register

P1P

pointed to by P

- P

OperationI

- P

Read Data Register 1 0 1 1 R1R0P1P0Read the contents of the Data Register

pointed to by P

- P0 and R1- R

Write Data Register 1 1 0 0 R1R0P1P0Write new value to the Data Register pointed to

- P0 and R1- R

by P

XFR Data Register to Wiper Counter Register

XFR Wiper Counter Register to Data Register

Global XFR Data Register to Wiper Counter Register

1101R1R0P1P0Transfer the contents of the Data Register

pointed to by R Register pointed to by P

1110R1R0P1P0Transfer the contents of the Wiper Counter

0001R1R

0 0 Transfer the contents of the Data Registers

pointed to by R

- R0 to the Wiper Counter

- R

- R0 of all four pots to their

- P

- P0 to the Register

respective Wiper Counter Register

Global XFR Wiper Counter Register to Data Register

Increment/Decrement Wiper Counter Register

1000R

1R0

00100 0P

0 0 Transfer the contents of all Wiper Counter

Registers to their respective data Registers pointed to by R

P0Enable Increment/decrement of the Wiper

Counter Register pointed to by P

- R0 of all four pots

- P

Read Status (WIP bit) 0 1010 0 0 1Read the status of the internal write cycle, by

checking the WIP bit.

FN8165.3

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X9250

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Instruction Format

Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.

(2) WPx refers to wiper position data in the Counter Register (2) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high). (3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).

Read Wiper Counter Register(WCR)

Falling

Edge

device type

identifier

010100

device

addresses

A1A

instruction

opcode

100100

Write Wiper Counter Register (WCR)

Falling

Edge

device type

identifier

010100

device

addresses

A1A

instruction

opcode

101000

Read Data Register (DR)

Falling

Edge

device type

identifier

010100

device

addresses

A1A

instruction

opcode

1011

Write Data Register (DR)

WCR

addresses

P1P

WCR

addresses

P1P

DR and WCR

addresses

R1R0P1P

wiper position

(sent by X9250 on SO)

Data Byte

(sent by Host on SI)

Data Byte

(sent by X9250 on SO)

P 2

Rising

W P 1

P 2

Edge

P 0

Rising

Edge

Rising

W P 1

Edge

P 1

Falling

Edge

device type

identifier

010100

device

addresses

A1A

instruction

opcode

1100

DR and WCR

addresses

R1R0P1P

W P

Transfer Data Register (DR) to Wiper Counter Register (WCR)

Falling

Edge

device type

identifier

010100

device

addresses

A1A

instruction

opcode

1101R1R0P1P0

DR and WCR

addresses

Data Byte

(sent by host on SI)

Rising

Edge

W P

Rising

Edge

HIGH-VOLTAGE

WRITE CYCLE

FN8165.3

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X9250

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Transfer Wiper Counter Register (WCR) to Data Register (DR)

Falling

Edge

device type

identifier

010100

device

addresses

A1A

instruction

opcode

1110

DR and WCR

addresses

R1R0P1P

Rising

Edge

Increment/Decrement Wiper Counter Register (WCR)

Falling

Edge

device type

identifier

010100

device

addresses

A1A

instruction

opcode

0010XX

WCR

addresses

P1P

increment/decrement

(sent by master on SI)

I/D I/D . . . . I/D I/D

Global Transfer Data Register (DR) to Wiper Counter Register (WCR)

Falling

Edge

device type

identifier

010100

device

addresses

A1A

instruction

opcode

0001

addresses

R1R

Rising

Edge

Global Transfer Wiper Counter Register (WCR) to Data Register (DR)

Falling

Edge

device type

identifier

010100

device

addresses

A1A

instruction

opcodeDRaddresses

1000

R1R

Rising

Edge

HIGH-VOLTAGE

WRITE CYCLE

HIGH-VOLTAGE

WRITE CYCLE

Rising

Edge

Read Status

device type

Falling

Edge

identifier

010100

device

addresses

A1A

instruction

opcode

010100010000000WI

Data Byte

(sent by X9250 on SO)

Rising

Edge

FN8165.3

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Page 11

X9250

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ABSOLUTE MAXIMUM RATINGS

Temperature under bias ........................ -65 to +135°C

Storage temperature ............................. -65 to +150°C

Voltage on SCK, SCL or any address input

with respect to V Voltage on V+ (referenced to V Voltage on V- (referenced to V

................................. -1V to +7V

)........................ 10V

)........................-10V

(V+) - (V-) .............................................................. 12V

Any V Any V

..............................................................V+

H/RH

.................................................................V-

L/RL

COMMENT

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Lead temperature (soldering, 10s) .................. +300°C

(10s) ............................................................±15mA

RECOMMENDED OPERATING CONDITIONS

Temp Min. Max.

Commercial 0°C+70°C

Industrial -40°C+85°C

POTENTIOMETER CHARACTERISTICS

Device Supply Voltage (VCC) Limits

X9250 5V ±10%

X9250-2.7 2.7V to 5.5V

(Over recommended operating conditions unless otherwise stated.)

(4)

Limits

Symbol Parameter

End to end resistance tolerance ±20 %

Power rating 50 mW +25°C, each pot

Vv+ Voltage on V+ pin X9250 +4.5 +5.5 V

Vv- Voltage on V- pin X9250 -5.5 -4.5 V

TERM

H/CL/CW

Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a

Wiper current ±7.5 mA

Wiper resistance 150 250 Ω Wiper current = ± 1mA

X9250-2.7 +2.7 +5.5

X9250-2.7 -5.5 -2.7

Voltage on any VH/RH or VL/RL pin V- V+ V

Noise -120 dBV Ref: 1kHz

Resolution

Absolute linearity

Relative linearity

Temperature coefficient of R

Ratiometric Temperature Coefficient

Potentiometer Capacitances 10/10/25 pF See Circuit #3

potentiometer.

(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiom-

eter. It is a measure of the error in step size. (3) MI = RTOT/255 or (V (4) Individual array resolutions.

(4)

(1)

(2)

- VL/RL)/255, single pot

H/RH

TOTAL

0.6 %

±1 MI

±0.6 MI

±300 ppm/°C

±20 ppm/°C

(3)

Test ConditionsMin. Typ. Max. Unit

w(n)(actual)

w(n + 1 - [Vw(n) + MI

- V

w(n)(expected)

]

FN8165.3

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X9250

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D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Limits

Symbol Parameter

CC1

VCC supply current (active)

CC2

VCC supply current (nonvolatile write)

VCC current (standby) 5 µA SCK = SI = VSS, Addr. = V

Input leakage current 10 µA VIN = VSS to V

Output leakage current 10 µA V

Input HIGH voltage VCC x 0.7 VCC + 0.1 V

Input LOW voltage -0.5 VCC x 0.3 V

Output LOW voltage 0.4 V IOL = 3mA

ENDURANCE AND DATA RETENTION

Parameter Min. Unit

Minimum endurance 100,000 Data changes per bit per register

Data retention 100 Years

400 µA f

SCK

Other Inputs = V

1mAf

SCK

Other Inputs = V

OUT

Test ConditionsMin. Typ. Max. Unit

= 2MHz, SO = Open,

= VSS to V

CAPACITANCE

Symbol Test Max. Unit Test Conditions

(5)

OUT

(5)

Output capacitance (SO) 8 pF V

OUT

= 0V

Input capacitance (A0, A1, SI, and SCK, CS) 6 pF VIN = 0V

POWER-UP TIMING

Symbol Parameter Min. Max. Unit

(6)

PUR

PUW

R VCC

(6)

(7)

Power-up to initiation of read operation 1 ms

Power-up to initiation of write operation 5 ms

VCC power up ramp rate 0.2 50 V/msec

POWER UP AND DOWN REQUIREMENT

The are no restrictions on the sequencing of the bias supplies V

, V+, and V- provided that all three supplies reach

their final values within 1msec of each other. At all times, the voltages on the potentiometer pins must be less than V+ and more than V-. The recall of the wiper position from nonvolatile memory is not in effect until all supplies reach their final value. The V

Notes: (5) This parameter is periodically sampled and not 100% tested

(6) t

PUR

issued. These parameters are periodically sampled and not 100% tested. (7) Sample tested only.

ramp rate spec is always in effect.

and t

are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific instruction can be

PUW

A.C. TEST CONDITIONS

Input pulse levels V

x 0.1 to VCC x 0.9

Input rise and fall times 10ns

Input and output timing level V

x 0.5

FN8165.3

August 29, 2006

Page 13

X9250

www.BDTIC.com/Intersil

Circuit #3 SPICE Macro Model EQUIVALENT A.C. LOAD CIRCUIT

10pF

TOTAL

25pF

10pF

SDA Output

1533Ω

100pF

2.7V

AC TIMING

Symbol Parameter Min. Max. Unit

SCK

CYC

LEAD

LAG

DIS

HOLD

HSU

WPASU

WPAH

SSI/SPI clock frequency 2.0 MHz

SSI/SPI clock cycle time 500 ns

SSI/SPI clock high time 200 ns

SSI/SPI clock low time 200 ns

Lead time 250 ns

Lag time 250 ns

SI, SCK, HOLD and CS input setup time 50 ns

SI, SCK, HOLD and CS input hold time 75 ns

SI, SCK, HOLD and CS input rise time 2 µs

SI, SCK, HOLD and CS input fall time 2 µs

SO output disable Time 0 500 ns

SO output valid time 100 ns

SO output hold time 0 ns

SO output rise time 50 ns

SO output fall time 50 ns

HOLD time 400 ns

HOLD setup time 100 ns

HOLD hold time 100 ns

HOLD low to output in high Z 100 ns

HOLD high to output in low Z 100 ns

Noise suppression time constant at SI, SCK, HOLD and CS inputs TBD ns

CS deselect time 2 µs

WP, A0 and A1 setup time 0 ns

WP, A0 and A1 hold time 0 ns

100pF

FN8165.3

August 29, 2006

Page 14

X9250

www.BDTIC.com/Intersil

HIGH-VOLTAGE WRITE CYCLE TIMING

Symbol Parameter Typ. Max. Unit

XDCP TIMING

Symbol Parameter Min. Max. Unit

WRPO

WRL

WRID

SYMBOL TABLE

WAVEFORM INPUTS OUTPUTS

High-voltage write cycle time (store instructions) 5 10 ms

Wiper response time after the third (last) power supply is stable 10 µs

Wiper response time after instruction issued (all load instructions) 10 µs

Wiper response time from an active SCL/SCK edge (increment/decrement instruc-

40 µs

tion)

Must be steady

May change from Low to High

May change from High to Low

Don’t Care: Changes Allowed

N/A Center Line

TIMING DIAGRAMS

Input Timing

SCK

Will be steady

Will change from Low to High

Will change from High to Low

Changing: State Not Known

is High Impedance

LEAD

MSB LSB

CYC

...

LAG

High Impedance

FN8165.3

August 29, 2006

Page 15

Output Timing

www.BDTIC.com/Intersil

X9250

SCK

Hold Timing

SCK

HOLD

MSB LSB

ADDR

HSU

...

DIS

...

HOLD

XDCP Timing (for all Load Instructions)

SCK

MSB LSB

VWx

High Impedance

...

WRL

FN8165.3

August 29, 2006

Page 16

XDCP Timing (for Increment/Decrement Instruction)

www.BDTIC.com/Intersil

X9250

SCK

VWx

ADDR

High Impedance

Inc/Dec

Write Protect and Device Address Pins Timing

WPASU

...

WRID

Inc/Dec

(Any Instruction)

...

WPAH

FN8165.3

August 29, 2006

Page 17

APPLICATIONS INFORMATION

www.BDTIC.com/Intersil

Basic Configurations of Electronic Potentiometers

VW/R

Three terminal Potentiometer; Variable voltage divider

Application Circuits

Noninverting Amplifier Voltage Regulator

X9250

Two terminal Variable Resistor; Variable current

VO = (1+R2/R1)V

Offset Voltage Adjustment Comparator with Hysterisis

10kΩ

100kΩ

-12V+12V

–

TL072

10kΩ10kΩ

VO (REG) = 1.25V (1+R2/R1)+I

VUL = {R1/(R1+R2) VO(max) V

= {R1/(R1+R2) VO(min)

317

adj

–

}

adj R2

VO (REG)V

FN8165.3

August 29, 2006

Page 18

Application Circuits (continued)

www.BDTIC.com/Intersil

Attenuator Filter

VO = G V

-1/2 ≤ G ≤ +1/2

Inverting Amplifier Equivalent L-R Circuit

}

VO = G V G = - R2/R

–

R1 = R2 = R3 = R4 = 10kΩ

}

–

X9250

fc = 1/(2πRC)

= 1 + R2/R

–

frequency ∝ R1, R2, C amplitude ∝ R

, R

ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R

}

+ R3) >> R

–

FN8165.3

August 29, 2006

Page 19

X9250

www.BDTIC.com/Intersil

Thin Shrink Small Outline Package Family (TSSOP)

SEATING PLANE

N LEADS

0.25 CAB

0.10 C

TOP VIEW

SIDE VIEW

SEE DETAIL “X”

(N/2)+1

(N/2)

0.10 CABM

PIN #1 I.D.

0.20 C2XB A

N/2 LEAD TIPS

0.05

MDP0044

THIN SHRINK SMALL OUTLINE PACKAGE FAMILY

SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE

A 1.20 1.20 1.20 1.20 1.20 Max

A1 0.10 0.10 0.10 0.10 0.10 ±0.05

A2 0.90 0.90 0.90 0.90 0.90 ±0.05

b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06

c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06

D 5.00 5.00 6.50 7.80 9.70 ±0.10

E 6.40 6.40 6.40 6.40 6.40 Basic

E1 4.40 4.40 4.40 4.40 4.40 ±0.10

e 0.65 0.65 0.65 0.65 0.65 Basic

L 0.60 0.60 0.60 0.60 0.60 ±0.15

L1 1.00 1.00 1.00 1.00 1.00 Reference

Rev. E 12/02

NOTES:

1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed

0.15mm per side.

2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side.

3. Dimensions “D” and “E1” are measured at dAtum Plane H.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

END VIEW

DETAIL X

GAUGE PLANE

0.25

0° - 8°

FN8165.3

August 29, 2006

Page 20

Small Outline Plastic Packages (SOIC)

www.BDTIC.com/Intersil

X9250

INDEX AREA

123

-A-

-B-

SEATING PLANE

-C-

0.25(0.010) BM M

h x 45°

0.25(0.010) C AM BS

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.

0.10(0.004)

M24.3 (JEDEC MS-013-AD ISSUE C)

24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0926 0.1043 2.35 2.65 -

A1 0.0040 0.0118 0.10 0.30 -

B 0.013 0.020 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 D 0.5985 0.6141 15.20 15.60 3 E 0.2914 0.2992 7.40 7.60 4 e 0.05 BSC 1.27 BSC H 0.394 0.419 10.00 10.65 h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N24 247

0° 8° 0° 8° -

NOTESMIN MAX MIN MAX

Rev. 1 4/06

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8165.3

August 29, 2006