Page 1
X88257
8051 Microcontroller Family Compatible
256K X88257 32,768 x 8 Bit
E2 Micro-Peripheral
FEATURES
• Multiplexed Address/Data Bus
—Direct Interface to Popular 8051 Family
• High Performance CMOS
—Fast Access Time, 120ns
—Low Power
—60mA Active Maximum
—500µA Standby Maximum
• Software Data Protection
• Toggle Bit Polling
—Early End of Write Detection
• Page Mode Write
—Allows up to 128 Bytes to be Written in
One Write Cycle
• High Reliability
—Endurance: 10,000 Write Cycle
—Data Retention: 100 Years
• 28-Lead PDIP Package
• 28-Lead SOIC Package
• 32-Lead PLCC Package
FUNCTIONAL DIAGRAM
DESCRIPTION
The X88257 is an 32K x 8 E2PROM fabricated with
advanced CMOS Textured Poly Floating Gate Technology. The X88257 features a multiplexed address and
data bus allowing direct interface to a variety of popular
single-chip microcontrollers operating in expanded multiplexed mode without the need for additional interface
circuitry.
CE, CE
WR
RD
PSEN
A8–A
ALE
© Xicor, Inc. 1994-1997 Patents Pending Characteristics subject to change without notice
6509-1.9 4/9/96 T2/C5/D8 NS
14
CONTROL
LOGIC
L
A
T
C
H
E
S
Y DECODE
SOFTWARE
DATA
PROTECT
X
D
E
C
O
D
E
I/O & ADDRESS LATCHES AND BUFFERS
1
32K x 8
E2PROM
A/D0–A/D
7
6509 ILL F02.1
Page 2
X88257
PIN DESCRIPTIONS
Address/Data (A/D0–A/D7)
Multiplexed low-order addresses and data. The addresses flow into the device while ALE is HIGH. After
ALE transitions from a HIGH to LOW the addresses are
latched. Once the addresses are latched these pins
input data or output data depending on RD, WR, PSEN,
and CE.
Addresses (A8–A14)
High order addresses flow into the device when ALE =
VIH and are latched when ALE goes LOW.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, ALE is LOW, and
CE is LOW, the X88257 is placed in the low power
standby mode. If CE is used to select the device, the CE
must be tied LOW.
Chip Enable (CE)
Chip enable is active HIGH. When CE is used to select
the device, the CE must be tied HIGH.
Program Store Enable (PSEN)
When the X88257 is to be used in a 8051-based system,
PSEN is tied directly to the microcontroller’s PSEN
output.
Read (RD)
When the X88257 is to be used in a 8051-based system,
RD is tied directly to the microcontroller’s RD output.
Write (WR)
When the X88257 is to be used in a 8051-based system,
WR is tied directly to the microcontroller’s WR output.
PIN CONFIGURATION
A
1
14
A
2
12
PSEN
CE
NC
NC
NC
NC
NC
NC
A/D
ALE
PSEN
A/D
A/D
A/D
V
0
3
4
CE
5
NC
6
NC
7
NC
8
NC
9
NC
10
11
0
12
1
13
2
14
SS
ALE
A
3213231
4
5
6
7
8
9
10
11
12
13
15 16 17 18 19
14
A/D1A/D
X88257
PLCC
12
A
X88257
2
V
PDIP
SOIC
14
SS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CC
NC
V
NC
A/D3A/D4A/D
WR
30
20
29
28
27
26
25
24
23
22
21
V
WR
A
A
A
A
RD
A
CE
A/D
A/D
A/D
A/D
A/D
13
A
5
CC
13
8
9
11
10
7
6
5
4
3
6509 FHD F01.3
A
8
A
9
A
11
NC
RD
A
10
CE
A/D
A/D
6509 FHD F01A.5
7
6
Address Latch Enable (ALE)
Addresses flow through the latches to address decoders
when ALE is HIGH and are latched when ALE transitions
from a HIGH to LOW.
PIN NAMES
Symbol Description
ALE Address Latch Enable
A/D0–A/D
A8–A
14
7
Address Inputs/Data I/O
Address Inputs
RD Read Input
WR Write Input
PSEN Program Store Enable Input
CE, CE Chip Enable
V
SS
V
CC
Ground
Supply Voltage
NC No Connect
2
6509 PGM T01.1
Page 3
X88257
TYPICAL APPLICATION
31
19
18
9
U?
EA/VP
X1
X2
RESET
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
39
38
37
36
35
34
33
32
11
12
12
15
16
17
18
19
A/D0
A/D1
A/D2
A/D3
A/D4
A/D5
A/D6
A/D7
12
INT0
13
INT1
14
T0
15
T1
1
P1.0
2
P1.1
3
P1.2
4
P1.3
5
P1.4
6
P1.5
7
P1.6
8
P1.7
8051
PRINCIPLES OF OPERATION
The X88257 is a highly integrated peripheral device for
a wide variety of single-chip microcontrollers. The X88257
provides 32K-bytes of 5V E2PROM which can be used
either for program storage, data storage or a combination of both, in systems based upon Harvard (80XX)
architectures. The X88257 incorporates the interface
circuitry normally needed to decode the control signals
and demultiplex the address/data bus to provide a
“seamless” interface.
The interface inputs on the X88257 are configured such
that it is possible to directly connect them to the proper
interface signals of the appropriate single-chip microcontroller. In the Harvard type system, the reading of
data from the chip is controlled either by the PSEN or the
RD signal, which essentially maps the X88257 into both
the Program and the Data Memory address map.
The X88257 also features the industry standard 5V
E2PROM characteristics such as byte or page mode
write and Toggle Bit Polling.
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
RD
WR
PSEN
ALE/P
TXD
RXD
21
22
23
24
25
26
27
28
17
16
29
30
11
10
25
24
21
23
2
26
1
20
22
27
4
3
A8
A9
A10
A11
A12
A13
A14
CE
RD
WR
PSEN
ALE
X88257
CE
6509 ILL F03.3
5
DEVICE OPERATION
Modes—Mixed Program/Data Memory
By properly assigning the address spaces, a single
X88257 can be used as both the program and data
memory. This would be accomplished by connecting all
the 8051 control outputs to the corresponding inputs of
the X88257.
Program Memory Mode
This mode of operation is read-only. The PSEN and ALE
inputs of the X88257 are tied directly to the PSEN and
ALE outputs of the microcontroller. The RD and WR
inputs are tied HIGH.
When ALE is HIGH, the A/D0–A/D7 and A8–A14 addresses flow into the device. The addresses, both lowand high-order, are latched when ALE transitions LOW
(VIL). PSEN will then go LOW and after t
PLDV
; Valid data
is presented on the A/D0–A/D7 pins. CE must be LOW
during the entire operation.
3
Page 4
X88257
DATA MEMORY MODE
This mode of operation allows both read and write
functions. The PSEN input is tied to VIH or to V
CC
through a pull-up resistor. The ALE, RD, and WR inputs
are tied directly to the microcontroller ALE, RD, and WR
outputs.
Read
This operation is quite similar to the program memory
read. A HIGH to LOW transition on ALE latches the
addresses and the data will be output on the AD pins
after RD goes LOW (t
RLDV
).
Write
A write is performed by latching the addresses on the
falling edge of ALE. Then WR is strobed LOW followed
by valid data being presented at the A/D0–A/D7 pins.
The data will be latched into the X88257 on the rising
edge of WR. To write to the X88257, a three-byte
command sequence must precede the byte(s) being
written. (See Software Data Protection.)
MODE SELECTION
CE PSEN RD WR Mode I/O Power
V
CC
X X X Standby High Z Standby (CMOS)
HIGH X X X Standby High Z Standby (TTL)
LOW LOW HIGH HIGH Read D
LOW HIGH LOW HIGH Read D
LOW HIGH HIGH Write D
PAGE WRITE OPERATION
Regardless of the microcontroller employed, the X88257
supports page mode write operations. This allows the
microcontroller to write from 1 to 128 bytes of data to the
X88257. Each individual write within a page write opera-
The falling edge of WR starts a timer delaying the
internal programming cycle 100µs. Therefore, each
successive write operation must begin within 100µs of
the last byte written. The following waveforms illustrate
the sequence and timing requirements.
OUT
OUT
IN
Active
Active
Active
tion must conform to the byte write timing requirements.
6509 PGM T02
Page Write Timing Sequence for WR Controlled Operation
OPERATION
CE
ALE
A/D0–A/D
7
A8–A
14
WR
PSEN(RD)
Notes: (1) For each successive write within a page write cycle A7–A14 must be the same.
BYTE 0
A
IN
D
IN
An
BYTE 1
A
IN
BYTE 2 LAST BYTE READ (1)(2) AFTER tWC READY FOR
t
BLC
A
D
IN
IN
An
D
IN
An
A
D
IN
IN
An
4
NEXT WRITE OPERATION
A
D
IN
OUT
An
t
WC
A
IN
ADDR
A
IN
Next Address
6509 ILL F08.1
Page 5
X88257
TOGGLE BIT POLLING
Because the typical write timing is less than the specified
5ms, Toggle Bit Polling has been provided to determine
the early end of write. During the internal programming
cycle I/O6 will toggle from “1” to “0” and “0” to “1” on
Toggle Bit Polling RD/WR Control
OPERATION
CE
ALE
A/D0–A/D
A8–A
7
14
WR
LAST BYTE
WRITTEN
A
D
IN
An
I/O6=X
A
D
IN
IN
OUT
An
I/O6=X I/O6=X I/O6=X
A
IN
subsequent attempts to read the device. When the
internal cycle is complete the toggling will cease and the
device will be accessible for additional read or write
operations.
X88C64 READY FOR
NEXT OPERATION
An
D
OUT
A
D
IN
OUT
An
A
D
IN
OUT
An
A
IN
ADDR
RD
SOFTWARE DATA PROTECTION
Software Data Protection (SDP) is employed to protect
the entire array against inadvertent writes. To write to the
X88257, a three-byte command sequence must precede
the byte(s) being written. All write operations, both the
command sequence and any data write operations must
conform to the page write timing requirements.
Writing with SDP
WRITE AA
TO 5555
WRITE 55
TO 2AAA
WRITE A0
TO 5555
PERFORM BYTE
OR PAGE WRITE
OPERATIONS
WAIT t
WC
6509 ILL F09.1
EXIT ROUTINE
6509 ILL F10.1
5
Page 6
X88257
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias .................. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to VSS.................................. –1V to +7V
D.C. Output Current .............................................5mA
Lead Temperature
(Soldering, 10 seconds).............................. 300°C
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature Min. Max.
Commercial 0°C +70°C
Industrial –40°C +85°C
Supply Voltage Limits
X88257 5V ±10%
6509 PGM T04.1
Military –55°C +125°C
6509 PGM T03.1
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Limits
Symbol Parameter Min. Max. Units Test Conditions
I
CC
I
SB1(CMOS)VCC
I
SB2(TTL)
I
LI
I
LO
VCC Current (Active) 60 mA CE = RD = VIL, All I/O’s =
Open,Other Inputs = V
Current (Standby) 500 µA CE = V
Open,Other Inputs = V
0.3V, ALE = V
– 0.3V, All I/O’s =
CC
IL
CC
CC
–
VCC Current (Standby) 6 mA CE = VIH, All I/O’s = Open, Other
Inputs = VIH, ALE = V
Input Leakage Current 10 µAV
Output Leakage Current 10 µAV
= VSS to V
IN
= V
OUT
SS
CC
to VCC,
IL
RD = VIH = PSEN
(3)
V
lL
(3)
V
IH
V
OL
V
OH
Input LOW Voltage –1 0.8 V
Input HIGH Voltage 2 VCC + 0.5 V
Output LOW Voltage 0.4 V IOL = 2.1mA
Output HIGH Voltage 2.4 V IOH = –400µA
6509 PGM T05.1
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
Symbol Test Max. Units Conditions
(4)
C
I/O
(4)
C
IN
Input/Output Capacitance 10 pF V
Input Capacitance 6 pF V
POWER-UP TIMING
Symbol Parameter Max. Units
(4)
t
PUR
(4)
t
PUW
Notes: (3) VIL min. and VIH max. are for reference only and are not tested.
(4) This parameter is periodically sampled and not 100% tested.
Power-Up to Read 1 ms
Power-Up to Write 5 ms
6
I/O
IN
= 0V
= 0V
6509 PGM T06
6509 PGM T07
Page 7
X88257
6509 ILL F04.3
5V
1.92KΩ
100pF
OUTPUT
1.37KΩ
A.C. CONDITIONS OF TEST
EQUIVALENT A.C. TEST CIRCUIT
Input Pulse Levels 0V to 3V
Input Rise and
Fall Times 10ns
Input and Output
Timing Levels 1.5V
6509 PGM T08.1
A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
PSEN Controlled Read Cycle
Symbol Parameter Min. Max. Units
t
LHLL
t
AVLL
t
LLAX
t
PLDV
t
PHDX
t
ELLL
PW
t
PS
t
PH
t
PHDZ
t
PLDX
PL
(5)
(5)
ALE Pulse Width 80 ns
Address Setup Time 20 ns
Address Hold Time 30 ns
PSEN Read Access Time 120 ns
Data Hold Time 0 ns
Chip Enable Setup Time 7 ns
PSEN Pulse Width 150 ns
PSEN Setup Time 30 ns
PSEN Hold Time 20 ns
PSEN Disable to Output in High Z 50 ns
PSEN to Output in Low Z 10 ns
PSEN Controlled Read Timing Diagram
6509 PGM T09
CE
t
t
LHLL
ALE
t
AVLL
A/D0–A/D
Note: (5) This parameter is periodically sampled and not 100% tested.
A8–A
PSEN
7
14
A
ELLL
t
LLAX
IN
t
PLDX
t
PLDV
t
PS
PW
PL
7
D
OUT
t
PHDX
ADDRESS
t
PH
t
PH
t
PHDZ
6509 ILL F05.1
Page 8
X88257
RD Controlled Read Cycle
Symbol Parameter Min. Max. Units
t
LHLL
t
AVLL
t
LLAX
t
RLDV
t
RHDX
t
ELLL
PW
t
RDS
t
RDH
t
RHDZ
t
RLDX
RL
(6)
(6)
ALE Pulse Width 80 ns
Address Setup Time 20 ns
Address Hold Time 30 ns
RD Read Access Time 120 ns
Data Hold Time 0 ns
Chip Enable Setup Time 7 ns
RD Pulse Width 150 ns
RD Setup Time 30 ns
RD Hold Time 20 ns
RD Disable to Output in High Z 50 ns
RD to Output in Low Z 0 ns
RD Controlled Read Timing Diagram
CE
t
ELLL
t
LLAX
IN
t
RDS
ALE
A/D0–A/D
A8–A
RD
14
t
LHLL
t
AVLL
7
A
t
RLDX
t
RLDV
PW
RL
D
OUT
t
RDH
t
RHDX
ADDRESS
t
RDH
t
RHDZ
6509 PGM T10
6509 ILL F06.1
Note: (6) This parameter is periodically sampled and not 100% tested.
8
SYMBOL TABLE
WAVEFORM
INPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
OUTPUTS
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
Page 9
X88257
WR Controlled Write Cycle
Symbol Parameter Min. Max. Units
t
LHLL
t
AVLL
t
LLAX
t
DVWH
t
WHDX
t
ELLL
t
WLWH
t
WRS
t
WRH
t
BLC
t
WC
(7)
ALE Pulse Width 80 ns
Address Setup Time 20 ns
Address Hold Time 30 ns
Data Setup Time 50 ns
Data Hold Time 30 ns
Chip Enable Setup Time 7 ns
WR Pulse Width 120 ns
WR Setup Time 30 ns
WR Hold Time 20 ns
Byte Load Time (Page Write) 0.5 100 µs
Write Cycle Time 5 ms
WR Controlled Write Timing Diagram
CE
t
ELLL
t
LLAX
IN
ALE
A/D0–A/D
t
LHLL
t
AVLL
7
A
D
t
DVWH
6509 PGM T11
t
WRH
t
WRH
IN
t
WHDX
A8–A
14
t
WRS
WR
Note: (7) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation.
t
WLWH
9
ADDRESS
6509 ILL F07.1
Page 10
X88257
NOTES
10
Page 11
X88257
NOTES
11
Page 12
X88257
PACKAGING INFORMATION
28-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
PIN 1 INDEX
PIN 1
1.470 (37.34)
1.400 (35.56)
1.300 (33.02)
REF.
0.557 (14.15)
0.510 (12.95)
0.085 (2.16)
0.040 (1.02)
SEATING
PLANE
0.160 (4.06)
0.120 (3.05)
0.110 (2.79)
0.090 (2.29)
0.065 (1.65)
0.040 (1.02)
0.625 (15.88)
0.590 (14.99)
TYP. 0.010 (0.25)
0°
15°
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
0.160 (4.06)
0.125 (3.17)
0.030 (0.76)
0.015 (0.38)
0.022 (0.56)
0.014 (0.36)
12
3926 FHD F04
Page 13
X88257
PACKAGING INFORMATION
28-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0° – 8°
0.105 (2.67)
0.092 (2.34)
0.0200 (0.5080)
0.0100 (0.2540)
0.020 (0.508)
0.014 (0.356)
0.050 (1.270)
X 45°
0.713 (18.11)
0.697 (17.70)
BSC
0.013 (0.32)
0.008 (0.20)
0.42" MAX
0.299 (7.59)
0.290 (7.37)
0.012 (0.30)
0.003 (0.08)
0.050" TYPICAL
0.419 (10.64)
0.394 (10.01)
BASE PLANE
SEATING PLANE
0.050"
TYPICAL
0.0350 (0.8890)
0.0160 (0.4064)
FOOTPRINT
0.030" TYPICAL
28 PLACES
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES
3926 FHD F17
13
Page 14
X88257
PACKAGING INFORMATION
32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J
0.420 (10.67)
0.495 (12.57)
0.485 (12.32)
TYP. 0.490 (12.45)
0.453 (11.51)
0.447 (11.35)
TYP. 0.450 (11.43)
0.300 (7.62)
REF.
0.050 (1.27) TYP.
0.021 (0.53)
0.013 (0.33)
TYP. 0.017 (0.43)0.045 (1.14) x 45°
0.050"
TYPICAL
0.510"
TYPICAL
0.400"
FOOTPRINT
SEATING PLANE
±0.004 LEAD
CO – PLANARITY
0.015 (0.38)
0.095 (2.41)
0.060 (1.52)
0.140 (3.56)
0.100 (2.45)
TYP. 0.136 (3.45)
0.048 (1.22)
0.042 (1.07)
0.030" TYPICAL
32 PLACES
0.050"
TYPICAL
0.300"
REF
0.410"
—
PIN 1
0.595 (15.11)
0.585 (14.86)
TYP. 0.590 (14.99)
0.553 (14.05)
0.547 (13.89)
TYP. 0.550 (13.97)
0.400
REF.
(10.16)
3° TYP.
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
3926 FHD F13
14
Page 15
X88257
ORDERING INFORMATION
X88257 X X
Device
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
Package
P = 28-Lead Plastic DIP
S = 28-Lead SOIC
J = 32-Lead PLCC
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes
no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to
discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
US. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976;
4,980,859; 5,012,132; 5,003,197; 5,023,694. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use as critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure
of the life support device or system, or to affect its satety or effectiveness.
15
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