Page 1
APPLICATION NOTE
A V A I L A B L E
Application Brief
iAPX88/188, MCS
196, MCS51 Compatible*
64K
2
E
• Block Lock Write Control
—Eight 1K Byte Blocks
- Lockable Independently or in Combination
• Multiplexed Address/Data Bus
—Direct Interface to Popular Microcontrollers
• High Performance CMOS
—Fast Access Times, 60ns and 80 ns
—Low Power
- 30mA Active Maximum
- 150 µ A Standby Maximum
• Software Data Protection
• Toggle Bit Polling
—Early End of Write Detection
• Page Mode Write
—Allows up to 32 Bytes to be Written in
One Write Cycle
Microcontroller Peripheral
X88064
DESCRIPTION
The X88064 is a high speed byte wide microperipheral
device with eight 1K byte blocks of E
directly connected to industry standard high performance
microprocessors. This peripheral provides two levels of
memory write control, the standard Software Data Program (SDP) control and Block Lock.
Block Lock provides a higher level of memory write control above SDP. This allows the software developer to
partition any or all of the eight 1K byte blocks as In-Circuit
Programmable ROM (ICPROM). Once locked, a block of
memory must first be unlocked before being written. Not
even a write operation using the SDP sequence will
change the contents of a locked block. Since a distinct, 6
byte, software command sequence locks and unlocks
the memory, the software developer has complete control of the memory contents.
8192 x 8 Bit
2
PROM and can be
ALE
A/D
WR
RD
PSEN
CE
WC
BLOCK LOCK
CONTROL
LOGIC
INDIVIDUALLY LOCKABLE
–A/D
0
7
L
A
12
T
C
H
INTERFACE
CONTROL
A
–A
8
D
E
C
O
D
E
R
SOFTWARE DATA PROTECT
POWER-ON RESET
AND V
(SDP)
CC
SENSE
WE
OE
1Kx8 BLOCKS
BUS TRANSCEIVER
A/D
–A/D
0
7
2
E
PROM
ARRAY
Xicor, Inc. 1994, 1995, 1996 Patents Pending
* All other brand and product names may be trademarks or
registered trademarks of their respective companies.
7023-2.3 1/29/97 T0/C2/D0 SH
1
Characteristics subject to change without notice
Page 2
X88064
Software Data Program Control provides a lower level of
memory write management. SDP controls write operations to the entire memory . When enabled, the host microprocessor must send a special 3 byte command sequence
before any byte or page writes to unloc ked locations in the
memory .
Pin configuration
NC
A
NC
NC
WC
PSEN
A/D
A/D
A/D
A/D
A/D
V
SS
1
2
12
3
4
5
6
7
0
8
1
9
2
10
3
11
4
12
DIP/SOIC
X88064
24
23
22
21
20
19
18
17
16
15
14
13
7023 FRM F02
V
CC
WR
ALE
A
8
A
9
A
11
RD
A
10
CE
A/D
A/D
A/D
7
6
5
PIN NAMES
PIN NAME I/O DESCRIPTION
PSEN
I
Content of E
HIGH. The device then places on the data bus (AD
2
memory can be read by lowering the PSEN
–AD
0
and holding both RD and WR
) the contents of E
7
2
memory at the
latched address.
A
AD
8
–A
0
12
–AD
7
I Non-multiplexed high-order Address Bus inputs for the upper byte of the address.
I/O Multiplexed low-order Address and Data Bus. The addresses are latched when ALE makes a
HIGH to LOW transition.
WR
RD
I During a byte/page write cycle WR
placed on the bus. The rising edge of
I
The RD
address. Both PSEN
input is active LOW and is used to read content of the E
an WR signals must be held HIGH during RD controlled read operation.
is brought LOW while RD is held HIGH and the data is
WR
latches data into the device.
2
memory at the latched
WC I WC input has to be held LOW during a write cycle. It can be permanently tied HIGH in order
to disable write to the E
memory. Taking WC
HIGH prior to t
(100ns, the time delay from
BLC
2
the last write cycle to the start of internal programming cycle) will inhibit the write operation.
CE
I The device select (CE
) is an active LOW input. This signal has to be asserted prior to ALE
HIGH to LOW transition in order to generate a valid internal device select signal. Holding this
pin HIGH and ALE LOW will place the device in standby mode.
ALE I Address Latch Enable input is used to latch the addresses present on the address lines
A
–A
and AD
8
12
–AD
into the device. The addresses are latched when ALE transitions from
0
7
HIGH to LOW.
2
Page 3
X88064
).
PRINCIPLES OF OPERATION
The X88064 is a highly integrated peripheral device for a
wide variety of single-chip microcontrollers. The X88064
provides 8K bytes of E
2
PROM which can be used either
for Program Storage, Data Storage, or a combination of
both, in systems based upon Harvard (80XX) architectures. The X88064 incorporates the interface circuitry
normally needed to decode the control signals and
demultiplex the Address/Data bus to provide a “Seamless” interf ace.
The interface inputs on the X88064 are configured such
that it is possible to directly connect them to the proper
interface signals of the appropriate single-chip microcontroller. In the Harvard type system, the reading of data
from the chip is controlled either by the PSEN
or the RD
signal, which essentially maps the X88064 into both the
Program and the Data Memory address map.
The X88064 also features an advanced implementation
of the Software Data Protection scheme, called Block
Lock, which allows the device to be broken into 8 independent sections of 1K bytes. Each of these sections can
be independently enabled for write operations; thereby
allowing certain sections of the device to be secured so
that updates can only occur in a controlled environment
(e.g. in an automotive application, only at an authorized
service center). The desired set-up configuration is
stored in a nonvolatile register , ensuring the configuration
data will be maintained after the device is powered do wn.
The X88064 also features a Write Control input (WC),
which serves as an external control over the completion
of a previously initiated page load cycle.
The X88064 also features the industry standard
2
E
PROM characteristics such as byte or page mode
write and Toggle Bit Polling.
Program Memory Mode
This mode of operation is read-only. The PSEN
inputs of the X88064 are tied directly to the PSEN and
ALE outputs of the microcontroller. The RD and WR
inputs are tied HIGH.
When ALE is HIGH, the A/D
–A/D
0
and A
7
addresses flow into the device. The addresses, both low
and high order, are latched when ALE transitions LOW
(V
). PSEN
IL
is presented on the A/D
will then go LOW and after t
–A/D
0
pins. CE
7
PLDV
must be LOW
during the entire operation.
Data Memory Mode
This mode of operation allows both read and write functions. The PSEN
pull-up resistor. The ALE, RD
input is tied to V
, and WR inputs are tied
or to V
IH
directly to the microcontroller’s ALE, RD, and WR outputs.
Read
This operation is quite similar to the Program Memory
read. A HIGH to LOW transition on ALE latches the
addresses and the data will be output on the A/D pins
after RD goes LOW (t
RLDV
Write
A write is performed by latching the addresses on the falling edge of ALE. Then WR
valid data being presented at the A/D
is strobed LOW followed by
–A/D
0
data will be latched into the X88064 on the rising edge of
. To write to the X88064, with the SDP feature
WR
enabled, a three-byte command sequence must precede
the byte(s) being written. (See Software Data Protection.)
and ALE
, valid data
through a
CC
pins. The
7
–A
8
12
DEVICE OPERATION MODES
Mixed Program/Data Memory
By properly assigning the address space, a single
X88064 can be used as both the Program and Data
Memory. This would be accomplished by connecting all
of the Microcontroller control outputs to the corresponding inputs of the X88064.
The Data Storage can be fully protected by enabling
Block Lock Control.
3
Page 4
X88064
MODE SELECTION
CE
V
CC
PSEN RD WR Mode I/O Power
X X X Standby High Z Standby (CMOS)
HIGH X X X Standby High Z Standby (TTL)
LOW LOW HIGH HIGH Program Fetch
LOW HIGH LOW HIGH Data Read
LOW HIGH HIGH Write
D
D
OUT
OUT
D
IN
TYPICAL APPLICATIONS
U4
U3
U2
X1
X2
80188
LCS
–A/D
A/D
0
A/D
–A/D
8
ALE/QS0
WR
RD/QSMD
UCS
/QS1
7
15
LATCH
188 Interface
U1
A/D
0
A
8–A12
CE
ALE
WR
RD
X88064
–A/D
PSEN
RAM
7
WC
EA/VP
X1
X2
VCC
80C51 µC Family
A/D
0
A
–A/D
8–A12
PSEN
ALE
WR
P2.7
RD
7
A/D
A
8–A12
WC
PSEN
ALE
RD
WR
CE
0
Active
Active
Active
V
–A/D
7
X88064
7023 FRM T02
CC
U2
A/D
A/D
0
–A/D
8
–A/D
X1
X2
EA
BUSWIDTH
8X196 KC/KD
ALE
WR
RD
7
15
196 Interface
4
U1
A/D
A
8–A12
CE
ALE
WR
RD
X88064
–A/D
0
7
WC
PSEN
VCC
7023 FRM F03
Page 5
X88064
PAGE WRITE OPERATION
Regardless of the microcontroller employed, the X88064
supports page mode write operations. This allows the
microcontroller to write from one to thirty-two bytes of
data to the X88064. Each individual write within a page
write operation must conform to the byte write timing
requirements. The falling edge of WR
delaying the internal programming cycle 100µs. Therefore, each successive write operation must begin within
100µs of the last byte written. The following waveforms
illustrate the sequence and timing requirements.
Page Write Timing Sequence for WR Controller Operation
OPERATION BYTE 0 BYTE 1 BYTE 2 LAST BYTE READ (1)
CE
ALE
A/D
–A/D
0
A8–A
WR
A
D
IN
7
12
IN
A12=n
A
IN
A12=n
D
IN
A
IN
A12=n
D
IN
A
IN
A12=n
D
IN
A
IN
A12=x
starts a timer
AFTER t
NEXT WRITE OPERATION
D
OUT
ADDR
A
IN
READY FOR
WC
A
IN
Next Address
PSEN(RD)
t
BLC
Notes: (1) For each successiv e write within a page write cycle A
–A
must be the same.
5
12
t
WC
7023 FRM F04
5
Page 6
X88064
TOGGLE BIT POLLING
Because the X88064 typical nonvolatile write cycle time
is less than the specified 5ms, Toggle Bit Polling has
been provided to determine the early completion of write.
During the internal programming cycle I/O6 will toggle
from HIGH to LOW and LOW to HIGH on subsequent
Toggle Bit Polling RD/WR Control
OPERATION
CE
ALE
A/D
–A/D
0
7
A8–A
12
LAST BYTE•
WRITTEN
AIN
DIN
A12=n A12=n A12=n A12=n A12=n
I/O6=X
AIN
DOUT
I/O6=X I/O6=X I/O6=X
AIN
attempts to read the device. When the internal cycle is
complete, the toggling will cease and the device will be
accessible for additional read or write operations.
X88064 READY FOR
NEXT OPERATION
DOUT
AIN
DOUT
AIN
DOUT
AIN
ADDR
WR
RD
Symbol Table
WAVEFORM INPUTS OUTPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A Center Line
7023 FRM F05
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
is High
Impedance
6
Page 7
X88064
WRITE AA to 555
EXIT ROUTINE
WRITE 55 to AAA
WRITE A0 to 555
WRITE AA to 555
WRITE 80 to AAA
WAIT OF t
wc
DATA PROTECTION
The X88064 provides two levels of data protection
through software control. There is a global software data
protection feature similar to the industry standard for
E2PROMs and a new Block Lock Control providing a
secondary level of data security .
SOFTWARE DATA PROTECTION
The X88064 offers a software controlled data protection
feature. The X88064 is shipped from Xicor with the software data protection NOT ENABLED; that is, the device
will be in the standard operating mode. In this mode data
should be protected during power-up/down operations
through the use of external circuits. The host then has
open read and write access of the device once VCC is
stable.
The X88064 can be automatically protected during
power-up/down without the need for external circuits by
employing the software data protection f eature. The internal software data protection circuit is enabled after the
first write operation utilizing the software algorithm. This
circuit is nonvolatile and will remain set for the life of the
device unless the SDP deactivation command is issued.
Once the software protection is enabled, the X88064 is
also protected from inadvertent and accidental writes in
the powered-up state. That is, the SDP software algorithm must be issued prior to writing additional data to the
device.
Writing with SDP Enabled
WRITE AA
TO X555
WRITE 55
TO XAAA
WRITE A0
TO X555
PERFORM BYTE
OR PAGE WRITE
OPERATIONS
X = Address bit (A12) of
the byte being updated.
WAIT t
WC
EXIT ROUTINE
7023 FRM F06
SEQUENCE TO DEACTIVATE SOFTWARE DATA
PROTECTION
7
Page 8
X88064
6 5
4 3
2 1 07
0000–03FF
0400–07FF
0800–0BFF
0C00–0FFF
1000–13FF
1400–17FF
1800–1BFF
1C00–1FFF
BLOCK
ADDRESS
1 = Locked, 0 = Unlocked
MSB LSB
7023 FRM F07
Block Lock Write Control
The X88064 provides a secondary level of data security
referred to as Block Lock Control. This is accessed
through an extension of the SDP command sequence.
Block Lock allows the user to inhibit writes to any 1K x 8
blocks of memory. Unlike SDP which prevents inadvertent writes, but still allows easy system access to writing
the memory , Block Loc k will inhibit all attempts unless it is
specifically disabled by the host. This could be used to
set a higher level of protection in a system where a portion of the memory is used for Program Storage and
another portion is used as Data Storage.
Setting write lockout is accomplished by writing a fivebyte command sequence, opening access to the Block
Lock Register (BLR). After the fifth byte is written, the
user writes to the BLR, selecting which blocks to protect
or unprotect. All write operations, both the command
sequence and writing the data to the BLR, must conform
to the page write timing requirements.
Block Lock Register Format
Setting Block Lock Register Sequence
WRITE AA
TO 555
WRITE 55
TO AAA
WRITE A0
TO 555
WRITE AA
TO 555
WRITE C0
TO AAA
XXXX
WAIT t
WC
(BLR SET)
7023 FRM F08
8
WRITE BLR
MASK VALUE TO
EXIT ROUTINE
Page 9
X88064
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias.......................–65°C to +135°C
Storage Temperature ...........................–65°C to +150°C
V oltage on any Pin with
Respect to VSS .......................................... –1V to +7V
D .C. Output Current.................................................5 mA
Lead Temperature
(Soldering, 10 seconds)300°C
*COMMENT
Stresses above those listed under “Absolute Maximum Ratings” ma y cause permanent damage to the device. This is a
stress rating only and the functional operation of the device
at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for e xtended
periods may affect de vice reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature Min. Max.
Commercial 0°C +70°C
Industrial –40°C +85°C
7023 FRM T03 7023 FRM T04
Supply Voltage Limits
X88064 5V ±10%
X88064-60 5V ±10%
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Limits
Symbol Parameter Min. Max. Units Test Conditions
= RD = VIL, All I/O’s = Open,
I
CC
I
SB1(CMOS)
I
SB2(TTL)
I
LI
I
LO
(3)
V
lL
(3)
V
IH
V
OL
V
OH
VCC Current (Active)
VCC Current (Standby)
VCC Current (Standby)
Input Leakage Current
Output Leakage Current
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
30 mA
150 µA
2.5 mA
10 µA
10 µA
–1 0.8 V
+ 0.5
2
V
CC
0.4 V
2.4 V
CE
Other Inputs = V
CE
Other Inputs = V
CE
Other Inputs = V
V
IN
V
OUT
V
I
OL
I
OH
CC
= V
– 0.3V, All I/O’s = Open,
CC
– 0.3V, ALE = V
CC
= VIH, All I/O’s = Open,
, ALE = V
= VSS to V
IH
CC
IL
= VSS to VCC, RD = VIH = PSEN
= 2.1 mA
= –400 µA
7023 FRM T05
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
IL
Symbol Test Max. Units Conditions
(4)
C
I/O
(4)
C
IN
Input/Output Capacitance
Input Capacitance
10 pF
6 pF
V
I/O
V
POWER-UP TIMING
Symbol Parameter Max. Units
(4)
t
PUR
(4)
t
PUW
Notes: (3) VIL min. and VIH max. are f or reference only and are not tested.
(4) This parameter is periodically sampled and not 100% tested.
Power-Up to Read 1 ms
Power-Up to Write 5 ms
9
IN
= 0V
= 0V
7023 FRM T06
7032 FRM T07
Page 10
X88064
A.C. CONDITIONS OF TEST
Input Pulse Levels
0V to 3V
EQUIVALENT A.C. TEST CIRCUIT
5V
Input Rise and Fall Times 10ns
Input and Output Timing Levels 1.5V
7023 FRM T08
OUTPUT
1.37KΩ
1.92KΩ
100pF
7023 FRM F09
PSEN Controlled Read Cycle
X88064 – 60 X88064
Symbol Parameter Min. Max. Min. Max. Units
t
LHLL
t
AVLL
t
LLAX
t
PLDV
t
PHDX
t
ELLL
PW
t
PS
t
PH
t
PHDZ
t
PLDX
PL
ALE Pulse Width
Address Setup Time
Address Hold Time
PSEN Read Access Time
Data Hold Time
Chip Enable Setup Time
PSEN Pulse Width
PSEN Setup Time
PSEN Hold Time
(5)
(5)
PSEN Disable to Output in High Z
PSEN to Output in Low Z
60 80 ns
10 10 ns
20 20 ns
45 80 ns
0 0 ns
7 7 ns
100 140 ns
20 30 ns
20 20 ns
20 30 ns
10 10 ns
PSEN Controlled Read Timing Diagram
t
PH
7023 FRM T09
ALE
A/D0–A/D
A8–A
PSEN
CE
t
t
LHLL
t
AVLL
A
7
12
IN
ELLL
t
LLAX
D
OUT
t
PLDX
t
PLDV
t
PS
P
WPL
10
t
t
PHDX
ADDRESS
PH
t
PHDZ
7023 FRM F10
Page 11
X88064
RD Controlled Read Cycle
X88064 – 60 X88064
Symbol Parameter Min. Max. Min. Max. Units
t
LHLL
t
AVLL
t
LLAX
t
RLDV
t
RHDX
t
ELLL
PW
t
RDS
t
RDH
t
RHDZ
t
RLDX
RL
(6)
(6)
ALE Pulse Width
Address Setup Time
Address Hold Time
RD Read Access Time
Data Hold Time
Chip Enable Setup Time
RD Pulse Width
RD Setup Time
RD Hold Time
RD Disable to Output in High Z
RD to Output in Low Z
RD Controlled Read Timing Diagram
60 80 ns
10 10 ns
20 20 ns
60 80 ns
0 0 ns
7 7 ns
120 150 ns
20 30 ns
20 20 ns
20 30 ns
0 0 ns
7023 FRM T10
CE
t
t
LHLL
ALE
t
AVLL
A/D0–A/D
Notes: (6) This parameter is periodically sampled and not 100% tested.
A8–A
7
12
RD
A
IN
ELLL
t
LLAX
t
RDS
t
RLDX
t
RLDV
PW
RL
t
RDH
t
RDH
D
OUT
t
RHDX
t
RHDZ
ADDRESS
7023 FRM F11
11
Page 12
X88064
WR Controlled Write Cycle
X88064 – 60 X88064
Symbol Parameter Min. Max. Min. Max. Units
t
LHLL
t
AVLL
t
LLAX
t
DVWH
t
WHDX
t
ELLL
t
WLWH
t
WRS
t
WRH
t
BLC
t
WC
(7)
ALE Pulse Width
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Chip Enable Setup Time
WR Pulse Width
WR Setup Time
WR Hold Time
Byte Load Time (Page Write)
Write Cycle Time
WR Controlled Write Timing Diagram
CE
t
t
LHLL
ELLL
60 80 ns
10 10 ns
20 20 ns
50 50 ns
30 30 ns
7 7 ns
100 120 ns
20 30 ns
20 20 ns
0.5 100 0.5 100 µs
5 5 ms
WRH
t
t
WRH
7023 FRM T11
ALE
t
AVLL
A/D0–A/D
Notes: (7) TWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time
7
A8–A
12
WR
the device requires to automatically complete the internal write operation.
A
IN
t
LLAX
t
WRS
t
WLWH
D
t
DVWH
IN
t
WHDX
ADDRESS
7023 FRM T12
12
Page 13
X88064
PACKAGING INFORMATION
PIN 1 INDEX
SEATING
PLANE
0.150 (3.81)
0.125 (3.18)
24-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
1.265 (32.13)
1.230 (31.24)
PIN 1
1.100 (27.94)
REF.
0.557 (14.15)
0.530 (13.46)
0.080 (2.03)
0.065 (1.65)
0.162 (4.11)
0.140 (3.56)
0.030 (0.76)
0.015 (0.38)
0.110 (2.79)
0.090 (2.29)
TYP. 0.010 (0.25)
0.065 (1.65)
0.040 (1.02)
0.625 (15.87)
0.600 (15.24)
0.022 (0.56)
0.014 (0.36)
0°
15°
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
13
7023 FRM F13
Page 14
X88064
PACKAGING INFORMATION
24-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
PIN 1 INDEX
(4X) 7°
0.050 (1.27)
0.010 (0.25)
0.020 (0.50)
PIN 1
X 45°
0.014 (0.35)
0.020 (0.50)
0.598 (15.20)
0.610 (15.49)
0.290 (7.37)
0.299 (7.60)
0.003 (0.10)
0.012 (0.30)
0.050" TYPICAL
0.393 (10.00)
0.420 (10.65)
0.092 (2.35)
0.105 (2.65)
0° – 8°
0.009 (0.22)
0.013 (0.33)
0.015 (0.40)
0.050 (1.27)
0.420"
FOOTPRINT
0.030" TYPICAL
24 PLACES
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
14
0.050"
TYPICAL
7023 FRM F14
Page 15
X88064
ORDERING INFORMATION
Device
X88064 X X
XX
Access Time
Blank = 80 ns
-60 = 60 ns
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Packages:
P = 24-Lead Plastic DIP
S = 24-Lead SOIC
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc.
makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the
described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the
right to discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967;
4,883, 976. Foreign patents and additional patents pending.
LIFE RELA TED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prev ent such an occurence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain
life, and whose failure to perform, when properly used in accordance with instr uctions for use provided in the labeling, can be reasonably
expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its saf ety or effectiveness.
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