Datasheet X76F128 Datasheet (Xicor)

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Page 1

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查询X76F128供应商

128K

X76F128

Secure SerialFlash

FEATURES

• 64-bit Password Security —Five 64-bit Passwords for Read, Program

and Reset

• 16384 Byte+64 Byte Password Protected Arrays —Seperate Read Passwords —Seperate Write Passw ords —Reset Password

• Programmable Passwords

• Retry Counter Register —Allows 8 tries before clearing of both arrays —Password Protected Reset

• 32-bit Response to Reset (RST Input)

• 64 byte Sector Program

• 400kHz Clock Rate

• 2 wire Serial Interface

• Low Power CMOS —2.7 to 5.5V operation —Standby current Less than 1 µ A —Active current less than 3 mA

• High Reliability Endurance: —100,000 Write Cycles

• Data Retention: 100 years

• Available in: —SmartCard Module —TQFP Package

16Kx8+64x8

DESCRIPTION

The X76F128 is a Pass word Access Security Supervisor, containing one 131072-bit Secure SerialFlash array and one 512-bit Secure SerialFlash array. Access to each memory array is controlled by two 64-bit passwords. These passwords protect read and write operations of the memory array. A separate RESET password is used to reset the passwords and clear the memory arrays in the event the read and write pass words are lost.

The X76F128 features a serial interface and software protocol allowing operation on a popular two wire bus. The bus signals are a clock Input (SCL) and a bidirectional data input and output (SDA). Access to the device is controlled through a chip select (CS any number of devices to share the same b us.

The X76F128 also features a synchronous response to reset providing an automatic output of a hard-wired 32-bit data stream conforming to the industry standard for memory cards.

The X76F128 utilizes Xicor’s proprietary Direct Write cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years.

) input, allowing

Functional Diagram

SCL

SDA

RST

Xicor, Inc. 1994, 1995, 1996 Patents Pending

7052 10/7/97 T0/C0/D0 SH

INTERFACE

LOGIC

CHIP ENABLE DATA T RANSF ER

ARRAY ACCESS

ENABLE

PASSWORD ARRAY

AND PASSWORD

VERIFICATION LOGIC

RESET

RESPONSE REGISTER

(PASSWORD PROTECTED)

Characteristics subject to change without notice

16K BYTE

SerialFlash ARRAY

ARRAY 0

64 BYTE

SerialFlash ARRAY

ARRAY 1

RETRY COUNTER

7052 FM 01

Page 2

X76F128

PIN DESCRIPTIONS Serial Clock (SCL)

The SCL input is used to clock all data into and out of the device.

Serial Data (SDA)

SDA is a true three state serial data input/output pin. During a read cycle, data is shifted out on this pin. During a write cycle, data is shifted in on this pin. In all other cases, this pin is in a high impedance state.

Chip Enable (CS

)

When CS is high, the X76F128 is deselected and the SDA pin is at high impedance and unless an internal write operation is underway, the X76F128 will be in standby mode. CS lo w enab les the X76F128, placing it in the active mode.

Reset (RST)

RST is a device reset pin. When RST is pulsed high while CS is low the X76F128 will output 32 bits of ﬁxed data which conforms to the standard for “synchronous response to reset”. CS must remain LOW and the part must not be in a write cycle for the response to reset to occur. See Figure 11. If at any time during the response to reset CS goes HIGH, the response to reset will be aborted and the par t will return to the standby state. The response to reset is "mask programmable" only!

If the X76F128 is in a nonvolatile write cycle a “no ACK” (SDA=High) response will be issued in response to loading of the command byte. If a stop is issued prior to the nonvolatile write cycle the write operation will be terminated and the part will reset and enter into a standby mode.

The basic sequence is illustrated in Figure 1.

PIN NAMES

Symbol Description

CS Chip Select Input SDA Serial Data Input/Output SCL Serial Clock Input RST Reset Input Vcc Supply Voltage Vss Ground NC No Connect

7052 FM T01

PIN CONFIGURATION

Smart Card

RST

SCL

GND

SDA

DEVICE OPERATION

There are two primary modes of operation for the X76F128; Protected READ and protected WRITE. Protected operations must be performed with one of four 8-byte passwords .

The basic method of communication for the device is established by ﬁrst enabling the device (CS LOW), generating a start condition, then transmitting a command, followed by the correct password. All parts will be shipped from the factory with all passwords equal to ‘0’. The user must perform ACK Polling to determine the validity of the password, before starting a data transfer (see Acknowledge Polling.) Only after the correct password is accepted and a ACK polling has been perf ormed, can the data transfer occur .

To ensure the correct communication, RST must remain LOW under all conditions except when running a “Response to Reset sequence”.

Data is transferred in 8-bit segments, with each transfer being followed by an ACK, generated by the receiving device.

VSS

NC NC NC NC NC NC NC NC NC CS

SDA

NCNCNCNCNCNCNCNCNCNCNC

4847464544434241403938

1 2 3 4 5 6 7 8 9 10 11 12

1314151617181920212223

NCNCNCNCNCNCNCNCNCNCNC

36 35 34 33 32 31 30 29 28 27 26 25

7052 FM 02

VCC NC NC NC NC NC NC NC NC NC RST SCL

After each transaction is completed, the X76F128 will reset and enter into a standby mode. This will also be the response if an unsuccessful attempt is made to access a protected array.

Page 3

X76F128

Figure 1. X76F128 Device Operation

LOAD COMMAND BYTE

LOAD 8-BYTE

PASSWORD

VERIFY PASSWORD

ACCEPTANCE BY

USE OF PASSWORD ACK POLLING

LOAD 2 BYTE ADDRESS

READ/WRITE

DATA BYTES

Twc OR DATA ACK POLLING

7052 FM 03

Retry Counter

The X76F128 contains a retry counter. The retry counter allows 8 accesses with an invalid password before any action is taken. The counter will increment with any combination of incorrect passwords. If the retry counter overﬂows, all memory areas are cleared and the device is locked by preventing any read or write array password matches. The passwords are unaffected. If a correct password is received prior to retry counter overﬂow, the retry counter is reset and access is granted. In order to reset the operation of a locked up device, a special reset command must be used with a RESET PASSWORD.

Device Protocol

The X76F128 supports a bidirectional bus oriented protocol. The protocol deﬁnes any device that sends data onto the bus as a transmitter and the receiving device as a receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transf ers and pro vide the clock f or both transmit and receive operations. Therefore, the X76F128 will be considered a slave in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during SCL LOW. SDA changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figure 2 and Figure 3.

Start Condition

All commands are preceeded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X76F128 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met.

A start may be issued to terminate the input of a control byte or the input data to be written. This will reset the device and leave it ready to begin a new read or write command. Because of the push/pull output, a start cannot be generated while the part is outputting data. Starts are inhibited while a write is in progress.

Stop Condition

All communications must be terminated by a stop condition. The stop condition is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to reset the device during a command or data input sequence and will leave the device in the standby power mode. As with starts, stops are inhibited when outputting data and while a write is in progress.

Acknowledge

Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data.

The X76F128 will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write condition have been selected, the X76F128 will respond with an acknowledge after the receipt of each subsequent eight-bit word.

RESET DEVICE Command

The RESET DEVICE command is used to clear the retry counter and reactivate the device. When the RESET DEVICE command is used prior to the retry counter overﬂow, the retry counter is reset and no arrays or passwords are affected. If the retry counter has ov erﬂowed, all memory areas are cleared and all commands are blocked and the retry counter is disabled. Issuing a valid RESET DEVICE command (with reset password) to the device resets and re-enables the retry counter and reenables the other commands. Again, the passwords are not affected.

RESET PASSWORD Command

A RESET PASSWORD command will clear both arrays and set all passwords to all zero .

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X76F128

Figure 2. Data Validity

SCL

SDA

Data Stable

Data

Change

Figure 3. Definition of Start and Stop Conditions

SCL

SDA

Start Condition Stop Condition

Table 1. X76F128 Instruction Set

1st Byte

after Start

1st Byte

after

Password

2nd Byte

after

Password Command Description

Password

used

1000 0000 High Address Low address Read (Array 0) Read 0 1000 1000 High Address Low address Read (Array 1) Read 1 1001 0000 High Address Low address Sector Write (Array 0) Write 0 1001 1000 High Address Low address Sector Write (Array 1) Write 1 1010 0000 0000 0000 0000 0000 Change Read 0 Password Read 0 1010 1000 0000 0000 0000 0000 Change Read 1 Password Read 1 1011 0000 0000 0000 0000 0000 Change Write 0 Password Write 0 1011 1000 0000 0000 0000 0000 Change Write 1 Password Write 1 1100 0000 0000 0000 0000 0000 Change Reset Password Reset 1110 0000 not used not used RESET PASSWORD Command Reset 1110 1000 not used not used RESET DEVICE Command Reset 1111 0000 not used not used ACK Polling command (Ends Password operation) None

All the rest Reserved

7052 FM 04

7052 FM 05

7052 FM T04

Notes: Illegal command codes will be disregarded. The part will respond with a “no-A CK” to the illegal b yte and then return to the standby mode.

All write/read operations require a password.

Page 5

X76F128

PROGRAM OPERATIONS Sector Programming

The sector program mode requires issuing the 8-bit write command followed b y the pass word, pass w ord Ack command, the address and then the data bytes transferred as illustrated in ﬁgure 4. Up to 64 bytes may be transferred. After the last byte to be transferred is acknowledged a stop condition is issued which starts the nonvolatile write cycle.

Figure 4. Sector Programming

COMMAND

START

SDA

ACK POLLING

START

COMMAND

NACK

Password

ACK

If ACK, Then

Password Matches

Write

ACK

A15

A14

A13

A12

ACK

A11

A10A9A8

Write

Password

ACK

A7A6A5A4A3A2A1

ACK

Data 63

ACK

Wait t Repeated

ACK Polling

Command

ACK

STOP

Data ACK Polling

ACK

Data 0

Wait t

. . .

ACK

7052 FM 07

Page 6

X76F128

Password ACK Polling Sequence

ACK

RETURNED?

ISSUE

PASSWORD

ACK COMMAND

PASSWORD LOAD

COMPLETED

ENTER ACK POLLING

ISSUE START

YES

PROCEED

7052 FM 09

ACK Polling

Once a stop condition is issued to indicate the end of the host’s write sequence, the X76F128 initiates the internal nonvolatile write cycle. In order to take advantage of the typical 5ms write cycle, ACK polling can begin immediately. This involves issuing the start condition followed by the new command code of 8 bits (1st byte of the protocol.) If the X76F128 is still busy with the nonvolatile write operation, it will issue a “no-ACK” in response. If the nonvolatile write operation has completed, an “ACK” will be returned and the host can then proceed with the rest of the protocol.

Data ACK Polling Sequence

WRITE SEQUENCE

COMPLETED

ENTER ACK POLLING

ISSUE START

ISSUE NEW

COMMAND

CODE

requires the master to perform an ACK polling with the speciﬁc code of F0h. As with regular Acknowledge polling the user can either time out for 10ms, and then issue the ACK polling once, or continuously loop as described in the ﬂow .

ACK

RETURNED?

YES

PROCEED

After the password sequence, there is always a nonvolatile write cycle. This is done to discourage random guesses of the password if the device is being tampered with. In order to continue the transaction, the X76F128

Figure 5. Acknowledge Polling

SCL

SDA

8th clk.

of 8th

pwd. byte

‘ACK’

clk

‘ACK’

7052 FM 08

If the password that was inserted was correct, then an “ACK” will be returned once the nonvolatile cycle is over, in response to the ACK polling cycle immediately follo wing it.

If the password that was inserted was incorrect, then a “no ACK” will be returned even if the nonvolatile cycle is over. Therefore, the user cannot be certain that the password is incorrect until the 10ms write cycle time has elapsed.

‘ACK’

clk

ACK or

no ACK

START

condition

8th clk

8th bit

7052 FM 10

Page 7

X76F128

READ OPERATIONS

Read operations are initiated in the same manner as write operations but with a different command code .

Random Read

The master issues the start condition and a Read instruction and password, perf orms a Password Ack Polling, then issues the word address. Once the password has been acknowledged and ﬁrst byte has been read, another start can be issued followed by a new 8-bit address. Random reads are allowed, but only the low order 8 bits can change. This limits random reads to a 512 byte block. Therefore, with a single password cycle only a 512 byte block of array 0 may be accessed randomly. To randomly access another block of arra y 0, a stop m ust be issued f ollowed by a new command/address/pass w ord sequence. A random read of the array 1 can access all locations without another password command sequence.

Figure 6. Random Read

Read

Password

If ACK, then

Password Matches

SDA

COMMAND

START

ACK

Sequential Read

The host can read sequentially within an array after the password acceptance sequence. The data output is sequential, with the data from address n followed by the data from n+1. The address counter for read operations increments all address bits, allowing the entire memory array contents to be serially read during one operation. At the end of the address space (address 3FFFh for array 0, 3Fh for array 1), the counter “rolls over” to address 0 and the X76F128 continues to output data for each acknowledge received. Refer to ﬁgure 7 for the address, acknowledge and data transfer sequence. An acknowledge must follow each 8-bit data transfer. After the last bit has been read, a stop condition is generated without a preceding acknowledge.

Read

Password

ACK

Wait t

ACK Polling

Command

ACK

Repeated

ACK POLLING

START

COMMAND

NACK

Figure 7. Sequential Read

COMMAND

START

SDA

If ACK, then

Password Matches

ACK POLLING

COMMAND

START

NACK

ACK

A15

ACK

A14

A15

A13

A14

A12

ACK

A13

A11

A10A9A8

Read

Password

A12

A11

A10A9A8

A7A6A5A4A3A2A1

ACK

A7A6A5A4A3A2A1

ACK

Data X

Read

Password

ACK

Data 0

START

ACK

A7A6A5A4A3A2A1

Wait t

Repeated

ACK Polling

Command

ACK

Data Y

Data X

STOP

7052 FM 11

STOP

7052 FM 12

Page 8

X76F128

PASSWORDS

The sequence in Figure 8 shows how to change (program) the passwords. The programming of passwords is done twice prior to the nonvolatile write cycle in order to verify that the new password is consistent. After the eight bytes are entered in the second pass, a comparison takes place. A mismatch will cause the part to reset and enter into the standby mode.

Data ACK polling can be used to determine if a password has been loaded correctly, however the data ACK command must be issued less than 2ms after the stop bit.

Figure 8. Change Passwords

Old

Password

START

SDA

If ACK, then

Password Matches

COMMAND

ACK POLLING

COMMAND

START

ACK

Two bytes of “0”

After this time, it cannot be determined if the password has been loaded correctly, without trying the new password. To determine if the new password has been loaded correctly the data ACK polling command is issued immediately following the stop bit. If it returns an ACK, then the two passes of the new password entry do not match. If it returns a "no ACK" then the passwords match and a high voltage cycle is in progress. The high voltage cycle is complete when a subsequent data ACK command returns an "ACK".

There is no way to read any of the passw ords.

Old

Password

ACK

Wait t Repeated

ACK Polling

Command

ACK

New

Password

ACK

New

Password

NACK

New

Password

ACK

RESPONSE TO RESET

The X76F128 returns a unique 32 bits response to reset by implementing the following procedures:

goes LOW

• CS

• RST goes HIGH

• SCK toggles Low-HIGH-Low

ACK

Password

ACK

Data ACK

Polling

STOP

If immediate ACK, then New Password error

If immediate NACK, followed by ACK after ~5ms

ACK

then New Password OK

ACK

7052 FM 13

• RST goes LOW

• Each subsequent clock forces next response to reset bit onto SO pin.

For the X76F128, the 32 bit sequence is 19h, 28h, AAh, 55h with each byte output LSB ﬁrst. See Figure 11.

Page 9

X76F128

Figure 9. Reset Password

Reset Password

START

COMMAND

SDA

Reset

Password

Reset

Password

Wait t

Repeated

ACK Polling

Command

If ACK, then

Device reset

ACK POLLING

START

COMMAND

STOP

ACK

Figure 10. Reset Device

Reset

Password

ACK

SDA

START

Reset Device COMMAND

Figure 11. Response to RESET (RST)

RST

ACK

Reset

Password

ACK

Wait t

Repeated

ACK Polling

Command

ACK

NACK

If ACK, then

Device reset

ACK POLLING

START

COMMAND

NACK

ACK

7052 FM 14

STOP

ACK

7052 FM 15

SCK

LSB

3 2 2

1 8 7 0 8 4 2 0

"19" "SS""28"

ABSOLUTE MAXIMUM RATINGS*

Temperature under Bias ......................–65 ° C to +135 ° C

Storage T emperature ...........................–65 ° C to +150 ° C

V oltage on any Pin with

Respect to V

......................................–1V to +7V

D .C. Output Current..................................................5mA

Lead Temperature

(Soldering, 10 seconds).................................300 ° C

LSB

2 1 1 1 1

"AA"

*COMMENT

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this speciﬁcation is not implied. Exposure to absolute maxim um rating conditions for extended periods ma y affect de vice reliability.

LSB

7 5 3 1

7052 FM 16

Page 10

X76F128

RECOMMENDED OPERATING CONDITIONS

Temp Min. Max.

Commercial 0 ° C +70 ° C Extended –20

C +85 ° C

7052 FM T05 7052 FM T06

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Limits

Symbol Parameter

Supply Current

CC1

(3)

CC2

(1)

SB1

(1)

SB2

(2)

IL1

(2)

IH1

(2)

IL2

(2)

IH2

CAPACITANCE T

(Read)

Supply Current

(Write) VCC Supply Current

(Standby) VCC Supply Current

(Standby)

1 mA

3 mA

50 µA

1 µA

Input Leakage Current 10 µA Output Leakage Current 10 µA

Input LOW Voltage –0.5

Input HIGH Voltage

x 0.7 VCC + 0.5

Input LOW Voltage –0.5

Input HIGH Voltage

x 0.9 VCC + 0.5

x 0.3

x 0.1

Output LOW Voltage 0.4 V

= +25 ° C, f = 1MHz, V

= 5V

Symbol Test Max. Units Conditions

(3)

OUT

(3)

NOTES: (1) Must perform a stop command after a read command prior to measurement

(2) V

min. and V

(3) This parameter is periodically sampled and not 100% tested.

Output Capacitance (SDA) 8 pF Input Capacitance (RST, SCL, CS) 6 pF

max. are f or reference only and are not tested.

Supply Voltage Limits

X76F128 4.5V to 5.5V

X76F128 – 2.7 2.7V to 3.6V

Units Test ConditionsMin. Max.

= V

SCL

x 0.1/V

x 0.9 Levels @ 400 KHz,

SDA = Open

= V

x 0.1/V

x 0.9 Levels @ 400 KHz,

RST = CS f

SCL

SDA = Open RST = CS

= VCC x 0.1, VIH = VCC x 0.9

SCL

SDA

= V

= 400 KHz, f

= V

SCC

= V

= 400 KHz

SDA

Other = GND or VCC–0.3V V

= VSS to VCC

= VSS to V V V V V

OUT

VCC = 5.5V VCC = 5.5V VCC = 3.0V VCC = 3.0V

= 3mA

7052 FM T07

= 0V

I/O

= 0V

7052 FM T08

EQUIVALENT A.C. LOAD CIRCUIT A.C. TEST CONDITIONS

Input Pulse Levels

1.3KΩ

100pF

7052 FM 17

Input Rise and Fall Times 10ns Input and Output Timing Level Output Load 100pF

OUTPUT

1533Ω

OUTPUT

100pF

x 0.1 to VCC x 0.9

x 0.5

7052 FM T09

Page 11

X76F128

AC CHARACTERISTICS AC Specifications (Over the recommended operating conditions)

Symbol Parameter Min Typ

SCL

(1)

BUF

LOW

HIGH

SU:STA

HD:STA

SU:DAT

HD:DAT

SU:STO

SU:CS

HD:CS

SCL_RST

SCL Clock Frequency, X76F128 0 400 KHz SCH Clock Frequency, X76F128–2.7 0 250 KHz Pulse width of spikes which must be suppressed by

the input filter

50 100 ns

SCL LOW to SDA Data Out Valid 0.1 0.3 0.9 µs Time the bus must be free before a new transmit

can start

1.3 µs

Clock LOW Time 1.3 µs Clock HIGH Time 0.6 µs Start Condition Setup Time 0.6 µs Start Condition Hold Time 0.6 µs Data In Setup Time 100 ns Data In Hold Time 0 µs Stop Condition Setup Time 0.6 µs Data Output Hold Time 50 300 ns

SDA and SCL Rise Time SDA and SCL Fall Time

20 + 0.1 x C 20 + 0.1 x C

(2)

CS Setup Time 200 ns CS Hold Time 100 ns SCL Clock Frequency during Response to Reset 400 kHz

(1)

Max Units

300 ns 300 ns

NOL

RST

SU:RST

LOW_RST

HIGH_RST

RDV

CDV

DHZ

Notes: 1. Typical values are for TA = 25˚C and VCC = 5.0V Notes: 2. Cb = Total Capacitance of one bus line in pf.

Device Select to RST active 200 ns RST to SCL Non-Overlap 500 ns

RST High Time 2.25 µs Response to Reset Setup Time 1.25 µs Clock LOW during Response to Reset 1.25 µs Clock HIGH during Response to Reset 1.25 µs RST LOW to SDA Valid During Response to Reset 0 500 ns CLK LOW to SDA Valid During Response to Reset 0 500 ns

Device Deselect to SDA high impedance 0 500 ns

7052 FM T14

Page 12

X76F128

RESET AC SPECIFICATIONS Power Up Timing

Symbol Parameter Min. Typ

(1)

PUR

(1)

PUW

Notes: 1. Delays are measured from the time VCC is stable until the speciﬁed operation can be initiated. These parameters are periodically sampled

and not 100% tested.

2. T ypical v alues are for TA = 25˚C and VCC = 5.0V

Time from Power Up to Read 1 mS Time from Power Up to Write 5 mS

(2)

Nonvolatile Write Cycle Timing

Symbol Parameter Min. Typ.(1) Max. Units

(1)

Notes: 1. tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.

It is the minimum cycle time to be allowed for any non volatile write b y the user , unless Acknowledge P olling is used.

Write Cycle Time 5 10 mS

Max. Units

7052 FM T11

7052 FM T12

TIMING DIAGRAMS Bus Timing

SCL

SU:STA

SDA IN

SDA OUT

Write Cycle Timing

SCL

SDA

8th bit of last byte ACK

HD:STA

SU:DAT

HIGH

LOW

HD:DAT

Stop

Condition

SU:STO

Condition

Start

BUF

7052 FM 18

7052 FM 19

Page 13

X76F128

CS Timing Diagram (Selecting/Deselecting the Part)

SCL

SU:CS

from

master

RST Timing Diagram – Response to a Synchronous Reset

RST

CLK

I/O

NOL

RST

1st clk

pulse

RDV

NOL

SU:RST

DATA BIT (1)

HIGH_RST

2nd

clk

pulse

CDV

HD:CS

LOW_RST

DATA BIT (2)

3rd

clk

pulse

7052 FM 20

CLK

I/O

DATA BIT (N)

DATA BIT (N+1)

GUIDELINES FOR CALCULATING TYPICAL VALUES OF BUS PULL UP RESISTORS

100

80 60

MAX

MIN

40 20

Pull Up Resistance in KΩ

MIN

10080604020

MAX

tR = maximum allowable SDA rise time

Bus capacitance in pF

CCMAX

-------------------------- 1.8

OLMIN

------------------=

BUS

Ω= =

DHZ

(N+2)

7052 FM 21

7052 FM 22

Page 14

X76F128

PACKAGING INFORMATION

48-LEAD THIN QUAD FLAT PACK (TQFP) PACKAGE TYPE L

PIN 1

GAGE PLANE 0.25

7°±0°

INCHESMILLIMETERS

0.002

0.53

0.007

0.004

0.273 BSC

0.35 BSC

0.018

0.039TYP

0.006

0.057

0.011

0.008

0.030

DIM

c D E

Hd He

MIN MAX MIN MAX

0.05

1.35

0.17

0.090

0.15

1.45

0.27

0.200

7.0 BSC

0.5 BSC 0.02 BSC

9.0 BSC

0.45

0.75

1.00TYP

NOTES:

1.GAGE PLANE DIMENSION IS IN MM.

2.LEAD COPLANARITY SHALL BE 0.10MM [0.004] MAXIMUM.

3. MOLD FLASH NOT INCLUDED IN DIMENSIONS

7052 FM 23

Page 15

X76F128

0.088 (2.24) MIN EPOXY FREE AREA (TYP.)

0.069 (1.75) MIN EPOXY

0.420 ± 0.002 (10.67 ± 0.05)

8 PAD CHIP ON BOARD SMART CARD MODULE TYPE X

0.465 ± 0.002 (11.81 ± 0.05)

0.285 (7.24) MAX.

FREE AREA (TYP.)

0.270 (6.86) MAX.

R. 0.039 (1.00) (4X)

0.210 ± 0.002 (5.33 ± 0.05)

0.008 ± 0.001 (0.20 ± 0.03)

SECTION A-A

FR4 TAPE

0.105 ± 0.002 (2.67 ± 0.05)

TYP.

(8x)

0.233 ± 0.002 (5.92 ± 0.05)

GLOB SIZE

0.146 ± 0.002 (3.71 ± 0.05)

DIE

0.174 ± 0.002 (4.42 ± 0.05)

0.0235 (0.60) MAX.

0.015 (0.38) MAX.

0.008 (0.20) MAX.

COPPER, NICKEL PLATED, GOLD FLASH

R. 0.013 (0.33) (8x)

0.105 ± 0.002 (2.67 ± 0.05)

(8x)

NOTE:

1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)

3003 ILL 03.1

Page 16

X76F128

0.475 ± 0.010

(12.07 ± 0.25)

3° MAX.

DRAFT ANGLE

(ALL AROUND)

R.0.125

(3.18) (4x)

SMART CARD TYPE Y

(85.57 ± 0.05)

0.593 ± 0.002

(15.06 ± 0.05)

R. 0.030 (0.76) (4x)

3.369 ± 0.002

0.430 ± 0.002 (10.92 ± 0.05)

2.125 ± 0.002

(53.98 ± 0.05)

0.31 ± 0.0005

(.079 ± 0.0127)

MOLD GATE DETAIL

SECTION A-A

SCALE:5x

0.478 ± 0.002 (12.14 ± 0.05)

NOTES:

1.ALL DIMENSIONS ARE IN INCHES AND (MILLIMETERS).

2.SPECIFIED DIMS ARE MEASURED AT BOTTOM OF CAVITY.

3.MATERIAL: WHITE PVC MOLDED PLASTIC WITH ANTI-STATIC ADDITIVE.

4.SURFACE FINISH SUITABLE FOR OFFSET PRINTING.

3003 ILL 02.1

Page 17

X76F128

ORDERING INFORMATION

X76F128 X X –X

Device

VCC Limits

Blank = 5V ±10%

2.7 = 2.7V to 3.6V

Temperature Range

Blank = Commercial = 0°C to +70°C E = Extended = –20°C to +85°C

Package

L = 48-Lead TQFP H = Die in Waffle Packs W = Die in Wafer Form X = Smart Card Module Y = Smart Card

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemniﬁcation provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or ﬁtness for any purpose. Xicor, Inc. reserves the right to discontinue production and change speciﬁcations and prices at any time and without notice.

Xicor, Inc. assumes no responsibility f or the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents , licenses are implied.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prev ent such an occurence.

Xicor’s products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signiﬁcant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiv eness.