Page 1
X68C64
68XX Microcontroller Family Compatible
64K X68C64 8192 x 8 Bit
E2 Micro-Peripheral
FEATURES
• CONCURRENT READ WRITE
™
—Dual Plane Architecture
—Isolates Read/Write Functions
Between Planes
—Allows Continuous Execution of Code
From One Plane While Writing in
the Other Plane
• Multiplexed Address/Data Bus
—Direct Interface to Popular 8-bit
Microcontrollers, e.g., Motorola M6801/03,
M68HC11 Family
• High Performance CMOS
—Fast Access Time, 120ns
—Low Power
—60mA Maximum Active
—500µA Maximum Standby
• Software Data Protection
• Block Protect Register
—Individually Set Write Lock Out in 1K Blocks
• Toggle Bit Polling
—Early End of Write Detection
• Page Mode Write
—Allows up to 32 Bytes to be Written in
One Write Cycle
• High Reliability
—Endurance: 100,000 Write Cycles
—Data Retention: 100 Years
DESCRIPTION
The X68C64 is an 8K x 8 E2PROM fabricated with
advanced CMOS Textured Poly Floating Gate Technology. The X68C64 features a Multiplexed Address and
Data bus allowing a direct interface to a variety of
popular single-chip microcontrollers operating in expanded multiplexed mode without the need for additional interface circuitry.
The X68C64 is internally configured as two independent
4K x 8 memory arrays. This feature provides the ability
to perform nonvolatile memory updates in one array and
continue operation out of code stored in the other array;
effectively eliminating the need for an auxiliary memory
device for code storage.
To write to the X68C64, a three-byte command
sequence must precede the byte(s) being written. The
X68C64 also provides a second generation software
data protection scheme called Block Protect. Block
Protect can provide write lockout of the entire device or
selected 1K blocks. There are eight 1K x 8 blocks that
can be write protected individually in any combination
required by the user. Block Protect, in addition to Write
Control input, allows the different segments of the memory
to have varying degrees of alterability in normal system
operation.
FUNCTIONAL DIAGRAM
CE
R/W
E
SEL
A8–A11
AS
CONCURRENT READ WRITE™ is a trademark of Xicor, Inc.
© Xicor, Inc. 1991, 1995, 1996 Patents Pending Characteristics subject to change without notice
3868-2.6 9/16/96 T0/C0/D2 SH
CONTROL
LOGIC
L
A
T
C
H
E
S
Y DECODE
X
D
E
C
O
D
E
I/O & ADDRESS LATCHES AND BUFFERS
WC
SOFTWARE
DATA
PROTECT
1K BYTES
1K BYTES
1K BYTES
1K BYTES
1
A12
A12
A12
M
U
X
A/D0–A/D7
1K BYTES
1K BYTES
1K BYTES
1K BYTES
3868 FHD F02
Page 2
X68C64
PIN DESCRIPTIONS
Address/Data (A/D0–A/D7)
Multiplexed low-order addresses and data. The addresses flow into the device while AS is HIGH. After AS
transitions from a HIGH to LOW the addresses are
latched. Once the addresses are latched these pins
input data or output data depending on E, R/W, and CE.
Addresses (A8–A12)
High order addresses flow into the device when AS is
HIGH and are latched when AS goes LOW.
Chip Enable (CE)
The Chip Enable input must be HIGH to enable all read/
write operations. When CE is LOW and AS is LOW, the
X68C64 is placed in the low power standby mode.
Enable (E)
When used with a MC6801 or MC6803, the E input is tied
directly to the E output of the microcontroller.
Read/Write (R/W)
When used with a MC6801 or MC6803, the R/W input is
tied directly to the R/W output of the microcontroller.
Address Strobe (AS)
Addresses flow through the latches to address decoders
when AS is HIGH and are latched when AS transitions
from a HIGH to LOW.
Device Select (SEL)
Must be connected to VSS.
Write Control (WC)
The Write Control allows external circuitry to abort a
page load cycle once it has been initiated. This input is
useful in applications in which a power failure or processor RESET could interrupt a page load cycle. In this
case, the microcontroller might drive all signals HIGH,
causing bad data to be latched into the E2PROM. If the
Write Control input is driven HIGH (before t
TBLC
Max)
after Read/Write (R/W) goes HIGH, the write cycle will
be aborted.
PIN CONFIGURATION
DIP/SOIC
NC
A12
NC
NC
WC
SEL
A/D0
A/D1
A/D2
A/D3
A/D4
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
X68C64
24
V
23
R/W
22
AS
21
A8
20
A9
19
A11
18
E
17
A10
16
CE
15
A/D7
14
A/D6
13
A/D5
3868 FHD F01.1
CC
PIN NAMES
Symbol Description
AS Address Strobe
A/D0–A/D
A8–A
12
7
Address Inputs/Data I/O
Address Inputs
E Enable Input
R/W Read/Write Input
CE Chip Enable
WC Write Control
SEL Device Select—Connect to V
V
SS
V
CC
Ground
Supply Voltage
NC No Connect
SS
3868 PGM T01.1
When WC is LOW (tied to VSS) the X68C64 will be
enabled to perform write operations. When WC is HIGH
normal read operations may be performed, but all attempts to write to the device will be disabled.
2
Page 3
X68C64
PRINCIPLES OF OPERATION
The X68C64 is a highly integrated peripheral device for
a wide variety of single-chip microcontrollers. The
X68C64 provides 8K bytes of E2PROM which can be
used either for Program Storage, Data Storage, or a
combination of both in systems based upon Von
Neumann (68XX) architectures. The X68C64 incorporates the interface circuitry normally needed to decode
the control signals and demultiplex the Address/Data
bus to provide a “Seamless” interface.
The interface inputs on the X68C64 are configured such
that it is possible to directly connect them to the proper
interface signals of the appropriate single-chip
microcontroller.
The X68C64 is internally organized as two independent
planes of 4K bytes of memory with the A12 input selecting which of the two planes of memory are to be
accessed. While the processor is executing code out of
one plane, write operations can take place in the other
plane, allowing the processor to continue execution of
code out of the X68C64 during a byte or page write to the
device.
The X68C64 also features an advanced implementation
of the Software Data Protection scheme, called Block
Protect, which allows the device to be broken into 8
independent sections of 1K bytes. Each of these sections can be independently enabled for write operations;
thereby allowing certain sections of the device to be
secured so that updates can only occur in a controlled
environment (e.g. in an automotive application, only at
an authorized service center). The desired set-up configuration is stored in a nonvolatile register, ensuring the
configuration data will be maintained after the device is
powered down.
The X68C64 also features a Write Control input (WC),
which serves as an external control over the completion
of a previously initiated page load cycle.
DEVICE OPERATION
Motorola 68XX operation requires the microcontroller’s
AS, E, and R/W outputs tied to the X68C64 AS, E, and
R/W inputs respectively.
The falling edge of AS will latch the addresses for both
a read and write operation. The state of R/W output
determines the operation to be performed, with the E
signal acting as a data strobe.
If R/W is HIGH and CE HIGH (read operation), data will
be output on A/D0–A/D7 after E transitions HIGH. If
R/W is LOW and CE is HIGH (write operation), data
presented at A/D0–A/D7 will be strobed into the X68C64
on the HIGH to LOW transition of E.
Typical Application
A/D0
A/D1
A/D2
A/D3
A/D4
A/D5
A/D6
A/D7
A8
A9
A10
A11
A12
CE
WC
AS
E
R/W
SEL
24
V
CC
V
SS
12X68C6468HC11A8
8 MHz
OSC.
31
PC0
32
PC1
33
PC2
34
PC3
30
XTAL
29
EXTAL
8
V
V
CC
CC
25
MODA
24
MODB
PC4
PC5
PC6
PC7
PB0
PB1
PB2
PB3
PB4
PB7
AS
R/W
35
36
37
38
16
15
14
13
12
9
26
27
E
28
7
8
9
10
11
13
14
15
21
20
17
19
2
16
5
22
18
23
6
The X68C64 also features the industry standard
E2PROM characteristics such a byte or page mode
write and Toggle Bit Polling.
3868 ILL F03.2
3
Page 4
X68C64
MODE SELECTION
CE E R/W Mode I/O Power
V
SS
X X Standby High Z Standby (CMOS)
LOW X X Standby High Z Standby (TTL)
HIGH HIGH HIGH Read D
HIGH LOW Write D
OUT
IN
Active
Active
PAGE WRITE OPERATION
Regardless of the microcontroller employed, the X68C64
supports page mode write operations. This allows the
microcontroller to write from one to thirty-two bytes of
data to the X68C64. Each individual write within a page
write operation must conform to the byte write timing
requirements. The rising edge of E starts a timer delaying the internal programming cycle 100µs. Therefore,
each successive write operation must begin within 100µs
of the last byte written. The following waveforms illustrate the sequence and timing requirements.
Page Write Timing Sequence for E Controlled Operation
OPERATION
CE
AS
A/D0–A/D
7
BYTE 0
A
IN
D
IN
BYTE 1
A
IN
BYTE 2 LAST BYTE READ (1)(2) AFTER tWC READY FOR
D
IN
A
D
IN
IN
A
D
IN
IN
A
D
IN
IN
NEXT WRITE OPERATION
A
3868 PGM T02.1
IN
A
IN
A8–A
R/W
12
E
A12=n
t
A12=n
BLC
A12=n
A12=n
Notes: (1) For each successive write within a page write cycle A5–A12 must be the same.
(2) Although it is not illustrated, the microcontroller may interleave read operations between the individual byte writes within the page
write operation. Two responses are possible.
a. Reading from the same plane being written (A12 of Read = A12 of Write) is effectively a Toggle Bit Polling operation.
b. Reading from the opposite plane being written (A12 of Read ≠ A12 of Write) true data will be returned, facilitating the use of a
single memory component as both program and data storage.
A12=x
t
WC
ADDR
Next Address
3868 FHD F07
4
Page 5
X68C64
CE
AS
A/D0–A/D
7
A8–A
12
E
R/W
A
IN
D
IN
A12=n
OPERATION
LAST BYTE
WRITTEN
I/O6=X X68C64 READY FOR
NEXT OPERATION
A
IN
D
OUT
A12=n
A
IN
D
OUT
A12=n
A
IN
D
OUT
A12=n
A
IN
A12=n
A
IN
ADDR
I/O6=X
I/O6=X
I/O6=X
D
OUT
Toggle Bit Polling
Because the X68C64 typical nonvolatile write cycle time
is less than the specified 5ms, Toggle Bit Polling has
been provided to determine the early completion of
write. During the internal programming cycle, I/O6 will
toggle from HIGH to LOW and LOW to HIGH on subsequent attempts to read the device. When the internal
Toggle Bit Polling E Control
cycle is complete, the toggling will cease and the device
will be accessible for additional read or write operations.
Due to the dual plane architecture, reads for polling must
occur in the plane that is being written; that is, the state
of A12 during a write must match the state of A12 during
Toggle Bit Polling.
3868 FHD F08
SYMBOL TABLE
WAVEFORM
INPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
OUTPUTS
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
5
Page 6
X68C64
DATA PROTECTION
The X68C64 provides two levels of data protection
through software control. There is a global software data
protection feature similar to the industry standard for
E2PROMs and a new Block Protect write lockout protection providing a secondary level of data security.
Writing with SDP
WRITE AA
TO X555
WRITE 55
TO XAAA
WRITE A0
TO X555
X = A12:
A
= 1 IF DATA TO BE WRITTEN IS WITHIN
12
ADDRESS 1000 TO 1FFF.
= 0 IF DATA TO BE WRITTEN IS WITHIN
A
12
ADDRESS 0000 TO 0FFF.
PERFORM BYTE
OR PAGE WRITE
OPERATIONS
WAIT t
WC
EXIT ROUTINE
3868 FHD F09
Software Data Protection
Software Data Protection (SDP) is employed to protect
the entire array against inadvertent writes. To write to
the X68C64, a three-byte command sequence must
precede the byte(s) being written.
All write operations, both the command sequence and
any data write operations, must conform to the page
write timing requirements.
Block Protect Write Lockout
The X68C64 provides a secondary level of data security
referred to as Block Protect write lockout. This is accessed through an extension of the SDP command
sequence. Block Protect allows the user to lockout
writes to any 1K x 8 blocks of memory. Unlike SDP which
prevents inadvertent writes, but still allows easy system
access to writing the memory, Block Protect will lockout
all attempts unless it is specifically disabled by the host.
This could be used to set a higher level of protection in
a system where a portion of the memory is used for
Program Storage and another portion is used as Data
Storage.
Setting write lockout is accomplished by writing a fivebyte command sequence, opening access to the Block
Protect Register (BPR). After the fifth byte is written, the
user writes to the BPR, selecting which blocks to protect
or unprotect. All write operations, both the command
sequence and writing the data to the BPR, must conform
to the page write timing requirements.
Block Protect Register Format
MSB LSB
7
1 = Protect, 0 = Unprotect Block Specified
5
6
43
2
1
0
BLOCK
ADDRESS
0000–03FF
0400–07FF
0800–0BFF
0C00–0FFF
1000–13FF
1400–17FF
1800–1BFF
1C00–1FFF
3868 FHD F11
Setting BPR Command Sequence
WRITE AA
TO X555
WRITE 55
TO XAAA
WRITE A0
TO X555
WRITE AA
TO X555
X = A12:
A
= 1 IF PROGRAM BEING EXECUTED IS
12
WITHIN 0000 TO 0FFF.
= 0 IF PROGRAM BEING EXECUTED
A
12
RESIDES WITHIN 1000 TO 1FFF.
WRITE C0
TO XAAA
WRITE BPR
MASK VALUE TO
ANY ADDRESS
WAIT t
WC
EXIT ROUTINE
3868 FHD F12
6
Page 7
X68C64
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias .................. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to VSS.................................. –1V to +7V
D.C. Output Current .............................................5mA
Lead Temperature
(Soldering, 10 seconds).............................. 300°C
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature Min. Max.
Commercial 0°C +70°C
Industrial –40°C +85°C
Supply Voltage Limits
X68C64 5V ±10%
3868 PGM T04.1
Military –55°C +125°C
3868 PGM T03.1
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Limits
Symbol Parameter Min. Max. Units Test Conditions
I
CC
I
SB1(CMOS)VCC
I
SB2(TTL)
I
LI
I
LO
(1)
V
lL
(1)
V
IH
V
OL
V
OH
VCC Current (Active) 60 mA CE = VIL, All I/O’s = Open,
Other Inputs = VCC, AS = V
IH
Current (Standby) 500 µA CE = VSS, All I/O’s = Open,Other
Inputs = V
– 0.3V, AS = V
CC
SS
VCC Current (Standby) 6 mA CE = VIH, All I/O’s = Open, Other
Inputs = VIH, AS = V
Input Leakage Current 10 µAV
Output Leakage Current 10 µAV
= VSS to V
IN
= VSS to VCC, E = V
OUT
IL
CC
IL
Input LOW Voltage –1 0.8 V
Input HIGH Voltage 2 VCC + 0.5 V
Output LOW Voltage 0.4 V IOL = 2.1mA
Output HIGH Voltage 2.4 V IOH = –400µA
3868 PGM T05.1
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
Symbol Test Max. Units Conditions
(2)
C
I/O
(2)
C
IN
Input/Output Capacitance 10 pF V
Input Capacitance 6 pF V
POWER-UP TIMING
Symbol Parameter Max. Units
(2)
t
PUR
(2)
t
PUW
Notes: (1) VIL min. and VIH max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
Power-Up to Read 1 ms
Power-Up to Write 5 ms
7
I/O
IN
= 0V
= 0V
3868 PGM T06
3868 PGM T07
Page 8
X68C64
A.C. CONDITIONS OF TEST
Input Pulse Levels 0V to 3V
TEST CIRCUIT
5V
Input Rise and
Fall Times 10ns
1.92KΩ
Input and Output
Timing Levels 1.5V
3868 PGM T08.1
OUTPUT
1.37KΩ
100pF
A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
E Controlled Read Cycle
Symbol Parameter Min. Max. Units
PW
t
ASL
t
AHL
t
ACC
t
DHR
t
CSL
PW
t
ES
t
EH
t
RWS
t
HZ
t
LZ
ASH
EH
(3)
(3)
Address Strobe Pulse Width 80 ns
Address Setup Time 20 ns
Address Hold Time 30 ns
Data Access Time 120 ns
Data Hold Time 0 ns
CE Setup Time 7 ns
E Pulse Width 150 ns
Enable Setup Time 30 ns
E Hold Time 20 ns
R/W Setup Time 20 ns
E LOW to High Z Output 50 ns
E HIGH to Low Z Output 0 ns
E Controlled Read Cycle
3868 FHD F04.2
3868 PGM T09.1
CE
t
A
IN
A8–A
CSL
t
AHL
t
ES
t
ACC
12
t
RWS
PW
ASH
AS
t
ASL
A/D0–A/D
7
A8–A
12
R/W
E
Note: (3) This parameter is periodically sampled and not 100% tested.
8
PW
EH
D
OUT
t
EH
t
t
EH
EH
t
DHR
t
HZ
3868 FHD F05.1
Page 9
X68C64
E Controlled Write Cycle
Symbol Parameter Min. Max. Units
PW
ASH
t
ASL
t
AHL
t
DSW
t
DHW
t
CSL
PW
EH
t
WC
t
ES
t
RWS
t
EH
t
BLC
E Controlled Write Cycle
CE
PW
AS
A/D0–A/D
A8–A
7
12
Address Strobe Pulse Width 80 ns
Address Setup Time 20 ns
Address Hold Time 30 ns
Data Setup Time 50 ns
Data Hold Time 30 ns
CE Setup Time 7 ns
E Pulse Width 120 ns
Write Cycle Time 5 ms
Enable Setup Time 30 ns
R/W Setup Time 20 ns
E Hold Time 20 ns
Byte Load Time (Page Write) 0.5 100 µs
t
EH
t
EH
t
EH
t
DHW
ASH
t
ASL
A
IN
A8–A
t
CSL
t
AHL
12
t
ES
t
DSW
D
IN
3868 PGM T10
R/W
t
RWS
E
PW
EH
3868 FHD F06
Note: (4) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation.
3868 FHD F06.1
9
Page 10
X68C64
PACKAGING INFORMATION
PIN 1 INDEX
PIN 1
24-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
1.265 (32.13)
1.230 (31.24)
1.100 (27.94)
REF.
0.557 (14.15)
0.530 (13.46)
0.080 (2.03)
0.065 (1.65)
SEATING
PLANE
0.150 (3.81)
0.125 (3.18)
0.110 (2.79)
0.090 (2.29)
0.065 (1.65)
0.040 (1.02)
0.625 (15.87)
0.600 (15.24)
TYP. 0.010 (0.25)
0°
15°
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
0.162 (4.11)
0.140 (3.56)
0.030 (0.76)
0.015 (0.38)
0.022 (0.56)
0.014 (0.36)
10
3926 FHD F03
Page 11
X68C64
PACKAGING INFORMATION
24-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
PIN 1 INDEX
(4X) 7°
0.050 (1.27)
0.010 (0.25)
0.020 (0.50)
PIN 1
X 45°
0.014 (0.35)
0.020 (0.50)
0.598 (15.20)
0.610 (15.49)
0.290 (7.37)
0.299 (7.60)
0.003 (0.10)
0.012 (0.30)
0.050" TYPICAL
0.393 (10.00)
0.420 (10.65)
0.092 (2.35)
0.105 (2.65)
0° – 8°
0.009 (0.22)
0.013 (0.33)
0.015 (0.40)
0.050 (1.27)
0.420"
FOOTPRINT
0.030" TYPICAL
24 PLACES
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
11
0.050"
TYPICAL
3926 FHD F24
Page 12
X68C64
ORDERING INFORMATION
X68C64 X X X
Device
VCC Limits
Blank = 5V ±10%
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +128°C
Package
P = 24-Lead Plastic DIP
S = 24-Lead Plastic SOIC
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are
implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and
additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
12
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