Page 1
X68257
68XX Microcontroller Family Compatible
256K X68257 32,768 x 8 Bit
E2 Micro-Peripheral
FEATURES
• Multiplexed Address/Data Bus
—Direct Interface to Popular 68HC11 Family
• High Performance CMOS
—Fast Access Time, 120ns
—Low Power
—60mA Active Maximum
—500µA Standby Maximum
• Software Data Protection
• Toggle Bit Polling
—Early End of Write Detection
• Page Mode Write
—Allows up to 128 Bytes to be Written in
One Write Cycle
• High Reliability
—Endurance: 10,000 Write Cycle
—Data Retention: 100 Years
• 28-Lead PDIP Package
• 28-Lead SOIC Package
• 32-Lead PLCC Package
FUNCTIONAL DIAGRAM
DESCRIPTION
The X68257 is an 32K x 8 E2PROM fabricated with
advanced CMOS Textured Poly Floating Gate Technology. The X68257 features a multiplexed address and
data bus allowing direct interface to a variety of popular
single-chip microcontrollers operating in expanded multiplexed mode without the need for additional interface
circuitry.
CE, CE
R/W
E
SEL
A8–A
AS
© Xicor, Inc. 1994, 1995, 1996 Patents Pending Characteristics subject to change without notice
6539-1.7 9/16/96 T0/C1/D2 SH
14
CONTROL
LOGIC
L
A
T
C
H
E
S
Y DECODE
SOFTWARE
DATA
PROTECT
X
D
E
C
O
D
E
I/O & ADDRESS LATCHES AND BUFFERS
1
32K x 8
E2PROM
A/D0–A/D
6539 ILL F02.2
7
Page 2
X68257
PIN DESCRIPTIONS
Address/Data (A/D0–A/D7)
Multiplexed low-order addresses and data. The addresses flow into the device while AS is HIGH. After AS
transitions from a HIGH to LOW the addresses are
latched. Once the addresses are latched these pins
input data or output data depending on R/W, SEL, and
CE.
Addresses (A8–A14)
High order addresses flow into the device when AS = V
IH
and are latched when AS goes LOW.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, AS is LOW, and CE
is LOW, the X68257 is placed in the low power standby
mode.
Chip Enable (CE)
Chip Enable is active HIGH. When CE is used to select
the device, the CE must be tied HIGH.
Program Store Enable (SEL)
When the X68257 is to be used in a 68XX-based
system, SEL is tied to VSS.
Read/Write (R/W)
When the X68257 is to be used in a 68XX-based
system, R/W is tied directly to the microcontroller’s R/W
output.
Address Strobe (AS)
Addresses flow through the latches to address decoders
when AS is HIGH and are latched when AS transitions
from a HIGH to LOW.
PIN NAMES
Symbol Description
AS Address Strobe
A/D0–A/D
A8–A
14
7
Address Inputs/Data I/O
Address Inputs
E Enable Input
R/W Read/Write Input
CE, CE Chip Enable
SEL Device Select—Connect to V
V
SS
V
CC
Ground
Supply Voltage
SS
NC No Connect
6539 PGM T01.2
PIN CONFIGURATION
SEL
A/D
A
A
SEL
A/D
A/D
A/D
V
CE
NC
NC
NC
NC
NC
NC
0
1
14
2
12
AS
3
4
CE
5
NC
6
NC
7
NC
8
NC
9
NC
10
11
0
12
1
13
2
14
SS
12
A
AS
3 2 1 32 31
430
5
6
7
8
9
10
11
12
13
15 16 17 18 19
14 20
2
A/D1A/D
PDIP
SOIC
X68257
PLCC
14
A
NC
X68257
SS
NC
V
28
V
27
R/W
26
A
25
A
24
A
23
A
22
E
21
A
20
CE
19
A/D
18
A/D
17
A/D
16
A/D
15
A/D
CC
13
V
A
R/W
29
28
27
26
25
24
23
22
21
5
A/D3A/D4A/D
CC
13
8
9
11
10
7
6
5
4
3
6539 FHD F01.3
A
8
A
9
A
11
NC
E
A
10
CE
A/D
7
A/D
6
6539 FHD F01A.5
2
Page 3
X68257
PRINCIPLES OF OPERATION
The X68257 is a highly integrated peripheral device for
a wide variety of single-chip microcontrollers. The X68257
provides 32K-bytes of 5V E2PROM which can be used
either for program storage, data storage, or a combination of both, in systems based upon Von Neumann
(68XX) architectures. The X68257 incorporates the
interface circuitry normally needed to decode the control
signals and demultiplex the address/data bus to provide
a “seamless” interface.
The interface inputs on the X68257 are configured such
that it is possible to directly connect them to the proper
interface signals of the appropriate single-chip microcontroller.
The X68257 features the industry standard 5V E2PROM
characteristics such as byte or page mode write and
Toggle Bit Polling.
Typical Application
U?
30
XTAL
29
EXTAL
39
RESET
41
IRQ
40
XIRQ
8
PA0
7
PA1
6
PA2
5
PA3
4
PA4
3
PA5
2
PA6
1
PA7
25
MODA
24
MODB
42
PD0
43
PD1
44
45
46
47
PD2
PD3
PD4
PD5
68HC11
MISO
MOSI
SCK
SS
DEVICE OPERATION
Motorola 68XX operation requires the microcontroller
AS, E, and R/W outputs to be tied to the X68257 AS, E,
and R/W inputs respectively.
The falling edge of AS will latch the addresses for both
a read and write operation. The state of the R/W output
determines the operation to be performed, with the E
signal acting as a data strobe.
If R/W is HIGH and CE is HIGH (read operation) data will
be output on A/D0–A/D7 after E transitions HIGH. If
R/W is LOW and CE is HIGH (write operation) data
present at A/D0–A/D7 will be strobed into the X68257 on
the HIGH to LOW transition of E.
U?
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
AS
R/W
PE0
PE1
PE2
PE3
VRH
VRL
31
32
33
34
35
36
37
38
16
15
14
13
12
11
10
9
26
28
27
E
17
18
19
20
22
21
11
12
12
15
16
17
18
19
25
24
21
23
26
27
22
2
1
5
3
A/D0
A/D1
A/D2
A/D3
A/D4
A/D5
A/D6
A/D7
A8
A9
A10
A11
A12
A13
A14
CE
AS
R/W
E
X68257
20
CE
SEL
6539 ILL F03.2
VCC
4
3
Page 4
X68257
MODE SELECTION
CE E R/W Mode I/O Power
V
SS
X X Standby High Z Standby (CMOS)
LOW X X Standby High Z Standby (TTL)
HIGH HIGH HIGH Read D
HIGH LOW Write D
OUT
IN
Active
Active
PAGE WRITE OPERATION
Regardless of the microcontroller employed, the X68257
supports page mode write operations. This allows the
microcontroller to write from 1 to 128 bytes of data to the
X68257. Each individual write within a page write operation must conform to the byte write timing requirements.
The rising edge of E starts a timer delaying the internal
programming cycle 100µs. Therefore, each successive
write operation must begin within 100µs of the last byte
written. The following waveforms illustrate the sequence
and timing requirements.
Page Write Timing Sequence for E Controlled Operation
OPERATION
CE
AS
A/D0–A/D
7
BYTE 0
A
IN
D
IN
BYTE 1
A
IN
BYTE 2 LAST BYTE READ (1)(2) AFTER tWC READY FOR
D
IN
A
D
IN
IN
A
D
IN
IN
A
D
IN
IN
NEXT WRITE OPERATION
A
6539 PGM T02.2
IN
A
IN
A8–A
14
E
R/W
An
t
BLC
Note: (1) For each successive write within a page write cycle A7–A14 must be the same.
t
WC
ADDR
Next AddressAn An An An
6539 FHD F07.1
4
Page 5
X68257
Toggle Bit Polling
Because the typical write timing is less than the specified
5ms, Toggle Bit Polling has been provided to determine
the early end of write. During the internal programming
cycle I/O6 will toggle from “1” to “0” and “0” to “1” on
Toggle Bit Polling E Control
OPERATION
CE
AS
A/D0–A/D
A8–A
7
14
E
LAST BYTE
WRITTEN
A
D
IN
An
I/O6=XI/O6=X
A
D
IN
IN
OUT
An An An An
A
IN
subsequent attempts to read the device. When the
internal cycle is complete, the toggling will cease and the
device will be accessible for additional read or write
operations.
D
OUT
I/O6=X
A
IN
D
OUT
I/O6=X X68257 READY FOR
A
D
IN
OUT
NEXT OPERATION
A
ADDR
IN
R/W
6539 FHD F08.2
5
Page 6
X68257
Software Data Protection
Software Data Protection (SDP) is employed to protect
the entire array against inadvertent writes. To write to
the X68257, a three-byte command sequence must
precede the byte(s) being written.
All write operations, both the command sequence and
any data write operations must conform to the page write
timing requirements.
Writing with SDP
WRITE AA
TO 5555
WRITE 55
TO 2AAA
WRITE A0
TO 5555
SYMBOL TABLE
WAVEFORM
INPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
OUTPUTS
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
PERFORM BYTE
OR PAGE WRITE
OPERATIONS
WAIT t
WC
EXIT ROUTINE
6539 FHD F09.1
6
Page 7
X68257
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias .................. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to VSS.................................. –1V to +7V
D.C. Output Current .............................................5mA
Lead Temperature
(Soldering, 10 seconds).............................. 300°C
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature Min. Max.
Commercial 0°C +70°C
Industrial –40°C +85°C
Supply Voltage Limits
X68257 5V ±10%
6539 PGM T04.1
Military –55°C +125°C
6539 PGM T03.1
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Limits
Symbol Parameter Min. Max. Units Test Conditions
I
CC
I
SB1(CMOS)VCC
I
SB2(TTL)
I
LI
I
LO
(1)
V
lL
(1)
V
IH
V
OL
V
OH
VCC Current (Active) 60 mA CE = VIL, All I/O’s = Open,
Other Inputs = VCC, AS = V
IH
Current (Standby) 500 µA CE = VSS, All I/O’s = Open,Other
Inputs = V
– 0.3V, AS = V
CC
SS
VCC Current (Standby) 6 mA CE = VIH, All I/O’s = Open, Other
Inputs = VIH, AS = V
Input Leakage Current 10 µAV
Output Leakage Current 10 µAV
= VSS to V
IN
= VSS to VCC, E = V
OUT
IL
CC
IL
Input LOW Voltage –1 0.8 V
Input HIGH Voltage 2 VCC + 0.5 V
Output LOW Voltage 0.4 V IOL = 2.1mA
Output HIGH Voltage 2.4 V IOH = –400µA
6539 PGM T05.1
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
Symbol Test Max. Units Conditions
(2)
C
I/O
(2)
C
IN
Input/Output Capacitance 10 pF V
Input Capacitance 6 pF V
POWER-UP TIMING
Symbol Parameter Max. Units
(2)
t
PUR
(2)
t
PUW
Notes: (1) VIL min. and VIH max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
Power-Up to Read 1 ms
Power-Up to Write 5 ms
7
I/O
IN
= 0V
= 0V
6539 PGM T06
6539 PGM T07
Page 8
X68257
A.C. CONDITIONS OF TEST
Input Pulse Levels 0V to 3V
TEST CIRCUIT
5V
Input Rise and
Fall Times 10ns
1.92KΩ
Input and Output
Timing Levels 1.5V
6539 PGM T08.1
OUTPUT
1.37KΩ
100pF
A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
E Controlled Read Cycle
Symbol Parameter Min. Max. Units
PW
t
ASL
t
AHL
t
ACC
t
DHR
t
CSL
PW
t
ES
t
EH
t
RWS
t
HZ
t
LZ
ASH
EH
(3)
(3)
Address Strobe Pulse Width 80 ns
Address Setup Time 20 ns
Address Hold Time 30 ns
Data Access Time 120 ns
Data Hold Time 0 ns
CE Setup Time 7 ns
E Pulse Width 150 ns
Enable Setup Time 30 ns
E Hold Time 20 ns
R/W Setup Time 20 ns
E LOW to High Z Output 50 ns
E HIGH to Low Z Output 0 ns
E Controlled Read Cycle
6539 FHD F04.2
6539 PGM T09.1
CE
t
A
IN
A8–A
CSL
t
AHL
14
t
ES
t
RWS
t
ACC
PW
PW
ASH
AS
t
ASL
A/D0–A/D
Note: (3) This parameter is periodically sampled and not 100% tested.
A8–A
7
14
R/W
E
8
EH
D
OUT
t
EH
t
EH
t
DHR
t
HZ
t
EH
6539 FHD F05.2
Page 9
X68257
E Controlled Write Cycle
Symbol Parameter Min. Max. Units
PW
ASH
t
ASL
t
AHL
t
DSW
t
DHW
t
CSL
PW
EH
t
WC
t
ES
t
RWS
t
EH
6539 FHD F05.2
t
BLC
E Controlled Write Cycle
CE
AS
A/D0–A/D
A8–A
7
14
R/W
Address Strobe Pulse Width 80 ns
Address Setup Time 20 ns
Address Hold Time 30 ns
Data Setup Time 50 ns
Data Hold Time 30 ns
CE Setup Time 7 ns
E Pulse Width 120 ns
Write Cycle Time 5 ms
Enable Setup Time 30 ns
R/W Setup Time 20 ns
E Hold Time 20 ns
Byte Load Time (Page Write) 0.5 100 µs
6539 PGM T10
PW
ASH
t
ASL
t
A
IN
A8–A
CSL
t
AHL
14
t
ES
t
RWS
t
DSW
D
IN
t
EH
t
EH
t
EH
t
DHW
E
PW
EH
Note: (4) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation.
9
6539 FHD F06.2
Page 10
X68257
WR Controlled Write Cycle
Symbol Parameter Min. Max. Units
t
LHLL
t
AVLL
t
LLAX
t
DVWH
t
WHDX
t
ELLL
t
WLWH
t
WRS
t
WRH
t
BLC
t
WC
(7)
ALE Pulse Width 80 ns
Address Setup Time 20 ns
Address Hold Time 30 ns
Data Setup Time 50 ns
Data Hold Time 30 ns
Chip Enable Setup Time 7 ns
WR Pulse Width 120 ns
WR Setup Time 30 ns
WR Hold Time 20 ns
Byte Load Time (Page Write) 0.5 100 µs
Write Cycle Time 5 ms
WR Controlled Write Timing Diagram
OPERATION
CE
AS
A/D0–A/D
7
BYTE 0
A
IN
D
IN
BYTE 1
A
IN
D
IN
6539 PGM T11
BYTE 2 LAST BYTE READ (1)(2) AFTER tWC READY FOR
A
D
IN
IN
A
D
IN
IN
A
D
IN
IN
NEXT WRITE OPERATION
A
IN
A
IN
t
WC
ADDR
Next AddressAn An An An
6539 FHD F07.1
A8–A
R/W
14
E
An
t
BLC
Note: (7) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation.
10
Page 11
X68257
PACKAGING INFORMATION
28-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
PIN 1 INDEX
PIN 1
1.470 (37.34)
1.400 (35.56)
1.300 (33.02)
REF.
0.557 (14.15)
0.510 (12.95)
0.085 (2.16)
0.040 (1.02)
SEATING
PLANE
0.160 (4.06)
0.120 (3.05)
0.110 (2.79)
0.090 (2.29)
0.065 (1.65)
0.040 (1.02)
0.625 (15.88)
0.590 (14.99)
TYP. 0.010 (0.25)
0°
15°
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
0.160 (4.06)
0.125 (3.17)
0.030 (0.76)
0.015 (0.38)
0.022 (0.56)
0.014 (0.36)
11
3926 FHD F04
Page 12
X68257
PACKAGING INFORMATION
28-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0° – 8°
0.105 (2.67)
0.092 (2.34)
0.0200 (0.5080)
0.0100 (0.2540)
0.020 (0.508)
0.014 (0.356)
0.050 (1.270)
X 45°
0.713 (18.11)
0.697 (17.70)
BSC
0.013 (0.32)
0.008 (0.20)
0.42" MAX
0.299 (7.59)
0.290 (7.37)
0.012 (0.30)
0.003 (0.08)
0.050" TYPICAL
0.419 (10.64)
0.394 (10.01)
BASE PLANE
SEATING PLANE
0.050"
TYPICAL
0.0350 (0.8890)
0.0160 (0.4064)
FOOTPRINT
0.030" TYPICAL
28 PLACES
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES
3926 FHD F17
12
Page 13
X68257
PACKAGING INFORMATION
32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J
0.420 (10.67)
0.495 (12.57)
0.485 (12.32)
TYP. 0.490 (12.45)
0.453 (11.51)
0.447 (11.35)
TYP. 0.450 (11.43)
0.300 (7.62)
REF.
0.050 (1.27) TYP.
0.021 (0.53)
0.013 (0.33)
TYP. 0.017 (0.43)0.045 (1.14) x 45°
0.050"
TYPICAL
0.510"
TYPICAL
0.400"
FOOTPRINT
SEATING PLANE
±0.004 LEAD
CO – PLANARITY
0.015 (0.38)
0.095 (2.41)
0.060 (1.52)
0.140 (3.56)
0.100 (2.45)
TYP. 0.136 (3.45)
0.048 (1.22)
0.042 (1.07)
0.030" TYPICAL
32 PLACES
0.050"
TYPICAL
0.300"
REF
0.410"
—
PIN 1
0.595 (15.11)
0.585 (14.86)
TYP. 0.590 (14.99)
0.553 (14.05)
0.547 (13.89)
TYP. 0.550 (13.97)
0.400
REF.
(10.16)
3° TYP.
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
3926 FHD F13
13
Page 14
X68257
ORDERING INFORMATION
X68257 X X
Device
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
Package
P = 28-Lead Plastic DIP
S = 28-Lead SOIC
J = 32-Lead PLCC
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes
no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to
discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
US. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976;
4,980,859; 5,012,132; 5,003,197; 5,023,694. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use as critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure
of the life support device or system, or to affect its satety or effectiveness.
14
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