Datasheet X5083S8IZ Specification

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Page 1

DATASHEET

SCK SI

CS/WDI

1 2

3 4

8 7

6 5

X5083

RESET

X5083

/WDI

2 3

RESET

7 6

SCK SI

X5083

CPU Supervisor with 8Kbit SPI EEPROM

This device combines four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability.

Applying power to the device activates the power-on reset circuit which holds RESET allows the power supply and oscillator to stabilize before the processor can execute code.

The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET from three preset values. Once selected, the interval does not change, even after cycling the power.

The device’s low V

system from low voltage conditions, resetting the system when V asserted until V

falls below the minimum VCC trip point. RESET is

returns to the proper operating level and

stabilizes. Five industry standard V available, however, Intersil’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to finetune the threshold for applications requiring higher precision.

Pinouts

active for a period of time. This

signal. The user selects the interval

detection circuitry protects the user’s

thresholds are

TRIP

8 LD TSSOP

November 12, 2015

Features

•Low VCC detection and reset assertion

- Four standard reset threshold voltages

4.63V, 4.38V, 2.93V, 2.63V

- Re-program low V special programming sequence

- Reset signal valid to V

• Selectable time out watchdog timer

• Long battery life with low power consumption

- <50µA max standby current, watchdog on

- <1µA max standby current, watchdog off

- <400µA max active current during read

• 8Kbits of EEPROM

• Save critical data with Block Lock

- Block lock first or last page, any 1/4 or lower 1/2 of EEPROM array

• Built-in inadvertent write protection

- Write enable latch

- Write protect pin

• SPI Interface - 3.3MHz clock rate

• Minimize programming time

- 16 byte page write mode

- 5ms write cycle time (typical)

• SPI modes (0,0 & 1,1)

reset threshold voltage using

= 1V

™

memory

FN8127

Rev 4.00

• Available packages

- 8 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP

• Pb-free plus anneal available (RoHS compliant)

Applications

8 LD SOIC, 8 LD PDIP

FN8127 Rev 4.00 Page 1 of 21 November 12, 2015

• Communications Equipment

- Routers, Hubs, Switches

- Set Top Boxes

• Industrial Systems

- Process Control

- Intelligent Instrumentation

• Computer Systems

- Desktop Computers

- Network Servers

• Battery Powered Equipment

Page 2

X5083

RESET

SCK

VCC

VSS

RESET

SPI

VCC

VSS

X5083

2.7-5.0V

10K

WATCHDOG

TIMER

COMMAND

DECODE &

CONTROL

LOGIC

SCK

/WDI

POR AND LOW

GENERATION

TRIP

RESET (X5083)

VOLTAGE RESET

PROTECT LOGIC

8KBITS

EEPROM

WATCHDOG

DETECTOR

ARRAY

STATUS

TRANSITION

RESET

RESET & WATCHDOG

TIMEBASE

X5083

STANDARD V

TRIP

LEVEL SUFFIX

4.63V (+/-2.5%) -4.5A

4.38V (+/-2.5%) -4.5

2.93V (+/-2.5%) -2.7A

2.63V (+/-2.5%) -2.7

See “Ordering Information” on page 3 for more details

For Custom Settings, call Intersil.

Typical Application

Block Diagram

FN8127 Rev 4.00 Page 2 of 21 November 12, 2015

Page 3

X5083

Ordering Information

PART NUMBER RESET (ACTIVE LOW)

(Note 1)

X5083PIZ-4.5A (No longer available or supported)

X5083S8Z-4.5A X5083 ZAL 0 to 70 8 Ld SOIC M8.15E

X5083S8IZ-4.5A (Note 2) X5083 ZAM -40 to 85 8 Ld SOIC M8.15E

X5083S8Z X5083 Z

X5083S8IZ (Note 2) X5083 ZI -40 to 85 8 Ld SOIC M8.15E

X5083V8IZ (No longer available,

recommended replacement: X5083S8IZ)

X5083S8Z-2.7A X5083 ZAN

X5083S8IZ-2.7A* X5083 ZAP -40 to 85 8 Ld SOIC M8.15E

X5083S8Z-2.7* X5083 ZF

X5083S8IZ-2.7* X5083 ZG -40 to 85 8 Ld SOIC M8.15E

X5083V8IZ-2.7 (No longer available,

recommended replacement: X5083S8IZ-2.7)

NOTE:

1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

2. *Add "-T1" suffix for tape and reel.

*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.

PART

MARKING

X5083P ZAM

583 IZ -40 to 85 8 Ld TSSOP M8.173

583 GZ -40 to 85 8 Ld TSSOP M8.173

VCC RANGE

(V)

4.5-5.5 4.5-4.75

4.5-5.5 4.25-4.5

2.7-5.5 2.85-3.0

2.7-5.5 2.55-2.7

TRIP

RANGE (V)

TEMPERATURE

RANGE (°C)

-40 to 85 8 Ld PDIP* MDP0031

0 to 70 8 Ld SOIC M8.15E

PACKAGE

(RoHS Compliant)

PKG.

DWG. #

Pin Description

(SOIC/

PDIP)

13CS

24SOSerial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the

57SISerial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising edge

68SCKSerial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge of SCK latches in

35WP

46V

82V

7 1 RESET

TSSOP NAME FUNCTION

/WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a

nonvolatile write cycle is underway, the device will be in the standby power mode. CS placing it in the active power mode. Prior to the start of any operation after power-up, a HIGH to LOW transition on CS

is required. Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog time out period results in RESET

serial clock (SCK) clocks the data out.

of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first.

the opcode, address, or data bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin.

Write Protect. When WP is LOW, nonvolatile write operations to the memory are prohibited. This “Locks” the memory to protect it against inadvertent changes when WP

Ground

Supply Voltage

Reset Output. RESET is an active LOW, open drain output which goes active whenever VCC falls below the minimum V RESET watchdog time out period. A falling edge of CS about 1V and remains active for 250ms after the power supply stabilizes.

sense level. It will remain active until VCC rises above the minimum VCC sense level for 250ms.

goes active if the watchdog timer is enabled and CS remains either HIGH or LOW longer than the selectable

will reset the watchdog timer. RESET goes active on power-up at

is HIGH, the device operates normally.

LOW enables the device,

going active.

FN8127 Rev 4.00 Page 3 of 21 November 12, 2015

Page 4

X5083

01234567

SCK

06h

012345678910 20 21 22 23

16 Bits

0001h

02h

VP = 15-18V

00h

WREN Write Address Data

FIGURE 1. SET V

TRIP

LEVEL SEQUENCE (V

= DESIRED V

TRIP

VALUE)

Principles of Operation

Power-on Reset

Application of power to the X5083 activates a power-on reset circuit. This circuit goes LOW at 1V and pulls the RESET active. This signal prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. RESET

active also blocks communication to the device through the SPI interface. When V

exceeds the device V

circuit releases RESET executing code. While V

value for 200ms (nominal) the

TRIP

, allowing the processor to begin

< V

communications to the

TRIP

device are inhibited.

Low Voltage Monitoring

During operation, the X5083 monitors the VCC level and asserts RESET V

. The RESET signal prevents the microprocessor from

TRIP

if supply voltage falls below a preset minimum

operating in a power fail or brownout condition and terminates any SPI communication in progress. The RESET

signal remains active until the voltage drops below 1V. It also remains active until V

When VCC falls below V

returns and exceeds V

, any communications in progress

TRIP

for 200ms.

TRIP

are terminated and communications are inhibited until V exceeds V

TRIP

for t

PURST

Watchdog Timer

The watchdog timer circuit monitors the microprocessor activity by monitoring the WDI input. The microprocessor must toggle the CS

/WDI pin periodically to prevent a RESET signal. The CS/WDI pin must be toggled from HIGH to LOW prior to the expiration of the watchdog time out period. The state of two nonvolatile control bits in the status register determine the watchdog timer period. The microprocessor can change these watchdog bits with no action taken by the microprocessor these bits remain unchanged, even after total power failure.

VCC Threshold Reset Procedure

The X5083 is shipped with a standard VCC threshold (V voltage. This value will not change over normal operating and storage conditions. However, in applications where the standard V needed in the V

is not exactly right, or if higher precision is

TRIP

value, the X5083 threshold may be

TRIP

adjusted. The procedure is described below, and uses the application of a high voltage control signal.

Setting the V

This procedure is used to set the V value. For example, if the current V V

is 4.6V, this procedure will directly make the change. If

TRIP

Voltage

to a higher voltage

TRIP

is 4.4V and the new

TRIP

the new setting is to be lower than the current setting, then it is necessary to reset the trip point before setting the new value.

To set the new V threshold voltage to the V programming voltage V followed by a write of Data 00h to address 01h. CS on the write operation initiates the V sequence. Bring WP

voltage, apply the desired V

TRIP

pin and tie the WP pin to the

. Then send a WREN command,

programming

TRIP

LOW to complete the operation.

TRIP

going HIGH

Note: This operation also writes 00h to array address 01h.

Resetting the V

This procedure is used to set the V level. For example, if the current V V

must be 4.0V, then the V

TRIP

is reset, the new V

Voltage

TRIP

to a “native” voltage

TRIP

is 4.4V and the new

TRIP

must be reset. When V

is something less than 1.7V. This

TRIP

procedure must be used to set the voltage to a lower value.

To reset the new V threshold voltage to the Vcc pin and tie the WP programming voltage V followed by a write of data 00h to address 03h. CS on the write operation initiates the V sequence. Bring WP

voltage, apply the desired V

TRIP

. Then send a WREN command,

programming

LOW to complete the operation.

TRIP

pin to the

going HIGH

Note: This operation also writes 00h to array address 03h.

TRIP

)

TRIP

FN8127 Rev 4.00 Page 4 of 21 November 12, 2015

Page 5

X5083

01234567

SCK

06h

012345678910 20 21 22 23

16 Bits

0003h

02h

VP = 15-18V

00h

WREN

Write

Address

Data

FIGURE 2. RESET V

TRIP

LEVEL SEQUENCE (VCC > 3V. WP = 15-18V)

2 3 4

7 6

X5083

TRIP

Adj.

RESET

4.7K

SCK

µC

Adjust

Run

FIGURE 3. SAMPLE V

TRIP

RESET CIRCUIT

FN8127 Rev 4.00 Page 5 of 21 November 12, 2015

Page 6

X5083

TRIP

Programming

Apply 5V to V

Decrement V

RESET pin

goes active?

Measured V

TRIP

Desired V

TRIP

DONE

Execute

Sequence

Reset V

TRIP

Set VCC = VCC Applied =

Desired V

TRIP

Execute

Sequence

Set V

TRIP

New VCC Applied =

Old V

Applied + Error

= VCC - 50mV)

Execute

Sequence

Reset V

TRIP

New VCC Applied =

Old V

Applied - Error

Error  –Emax

–Emax < Error < Emax

YES

Error



Emax

Emax = Maximum Desired Error

FIGURE 4. V

TRIP

PROGRAMMING SEQUENCE

FN8127 Rev 4.00 Page 6 of 21 November 12, 2015

Page 7

X5083

SPI Serial Memory

The memory portion of the device is a CMOS serial EEPROM array with Intersil’s block lock protection. The array is internally organized as x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus.

The device utilizes Intersil’s proprietary Direct Write providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years.

The device is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families.

The device monitors the bus and asserts RESET watchdog timer is enabled and there is no bus activity within the user selectable time out period or the supply voltage falls below a preset minimum V

TRIP

The device contains an 8-bit instruction register. It is accessed via the SI input, with data being clocked in on the rising edge of SCK. CS

must be LOW during the entire operation.

All instructions (Table 1), addresses and data are transferred MSB first. Data input on the SI line is latched on the first rising edge of SCK after CS

goes LOW. Data is output on the SO line by the falling edge of SCK. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off.

™

cell,

output if the

instruction will set the latch and the WRDI instruction will reset the latch (Figure 7). This latch is automatically reset upon a power-up condition and after the completion of a valid Write Cycle.

Status Register

The RDSR instruction provides access to the status register. The status register may be read at any time, even during a write cycle. The status register is formatted as follows.

Status Register/Block Lock/WDT Byte

765 4 3 210

0 0 0 WD1 WD0 BL2 BL1 BL0

Block Lock Memory

Intersil’s block lock memory provides a flexible mechanism to store and lock system ID and parametric information. There are seven distinct block lock memory areas within the array which vary in size from one page to as much as half of the entire array. These areas and associated address ranges are block locked by writing the appropriate two byte block lock instruction to the device as described in Table 1 and Figure 9. Once a block lock instruction has been completed, that block lock setup is held in the nonvolatile status register until the next block lock instruction is issued. The sections of the memory array that are block locked can be read but not written until block lock is removed or changed.

Write Enable Latch

The device contains a Write Enable Latch. This latch must be SET before a Write Operation is initiated. The WREN

TABLE 1. INSTRUCTION SET AND BLOCK LOCK PROTECTION BYTE DEFINITION

INSTRUCTION FORMAT INSTRUCTION NAME AND OPERATION

0000 0110 WREN: set the write enable latch (write enable operation)

0000 0100 WRDI: reset the write enable latch (write disable operation)

0000 0001 Write status instruction—followed by:

0000 0101 READ STATUS: reads status register & provides write in progress status on SO pin

0000 0010 WRITE: write operation followed by address and data

0000 0011 READ: read operation followed by address

Block lock/WDT byte: (See Figure 1)

000WD 000WD 000WD 000WD 000WD 000WD 000WD 000WD

WD2000 --->no block lock: 00h-00h--->none of the array

WD2001 --->block lock Q1: 0000h-00FFh--->lower quadrant (Q1)

WD2010 --->block lock Q2: 0100h-01FFh--->Q2

WD2011 --->block lock Q3: 0200h-02FFh--->Q3

WD2100 --->block lock Q4: 0300h-03FFh--->upper quadrant (Q4)

WD2101 --->block lock H1: 0000h-01FFh--->lower half of the array (H1)

WD2110 --->block lock P0: 0000h-000Fh--->lower page (P0)

WD2111 --->block lock Pn: 03F0h-03FFh--->upper page (PN)

FN8127 Rev 4.00 Page 7 of 21 November 12, 2015

Page 8

X5083

Watchdog Timer

The watchdog timer bits, WD0 and WD1, select the watchdog time out period. These nonvolatile bits are programmed with the WRSR instruction. A change to the Watchdog Timer, either setting a new time out period or turning it off or on, takes effect, following either the next command (read or write) or cycling the power to the device.

The recommended procedure for changing the Watch-dog Timer settings is to do a WREN, followed by a write status register command. Then execute a soft-ware loop to read the status register until the MSB of the status byte is zero. A valid alternative is to do a WREN, followed by a write status register command. Then wait 10ms and do a read status command.

TABLE 2. WATCHDOG TIMER DEFINITION

STATUS REGISTER BITS

0 0 1.4s

0 1 600ms

1 0 200ms

1 1 disabled (factory default)

WATCHDOG TIME OUT

(TYPICAL)WD1 WD0

Read Sequence

When reading from the EEPROM memory array, CS is first pulled low to select the device. The 8-bit READ instruction is transmitted to the device, followed by the 16-bit address. After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to address $0000 allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS

high. Refer to the

read EEPROM array sequence (Figure 5).

To read the status register, the CS

line is first pulled low to select the device followed by the 8-bit RDSR instruction. After the RDSR opcode is sent, the contents of the status register are shifted out on the SO line. Refer to the read status register sequence (Figure 6).

Write Sequence

Prior to any attempt to write data into the device, the “Write Enable” Latch (WEL) must first be set by issuing the WREN instruction (Figure 7). CS instruction is clocked into the device. After all eight bits of the instruction are transmitted, CS user continues the write operation without taking CS after issuing the WREN instruction, the write operation will be ignored.

is first taken LOW, then the WREN

must then be taken HIGH. If the

HIGH

To write data to the EEPROM memory array, the user then issues the WRITE instruction followed by the 16 bit address and then the data to be written. Any unused address bits are specified to be “0’s”. The WRITE operation minimally takes 32 clocks. CS

must go low and remain low for the duration of the operation. If the address counter reaches the end of a page and the clock continues, the counter will roll back to the first address of the same page and overwrite any data that may have been previously written.

For a write operation (byte or page write) to be completed, CS can only be brought HIGH after bit 0 of the last data byte to be written is clocked in. If it is brought HIGH at any other time, the write operation will not be completed (Figure 8).

To write to the status register, the WRSR instruction is followed by the data to be written (Figure 9). Data bits 5, 6 and 7 must be “0”.

Read Status Operation

If there is not a nonvolatile write in progress, the read status instruction returns the block lock setting from the status register which contains the watchdog timer bits WD1, WD0, and the block lock bits IDL2-IDL0 (Figure 6). The block lock bits define the block lock condition (Table 1). The watchdog timer bits set the operation of the watchdog timer (Table 2). The other bits are reserved and will return ’0’ when read. See Figure 6.

During an internal nonvolatile write operaiton, the Read Status Instruction returns a HIGH on SO in the first bit following the RDSR instruction (the MSB). The remaining bits in the output status byte are undefined. Repeated Read Status Instructions return the MSB as a ‘1’ until the nonvolatile write cycle is complete. When the nonvolatile write cycle is completed, the RDSR instruction returns a ‘0’ in the MSB position with the remaining bits of the status register undefined. Subsequent RDSR instructions return the Status Register Contents. See Figure 10.

RESET Operation

The RESET output is designed to go LOW whenever VCC has dropped below the minimum trip point and/or the watchdog timer has reached its programmable time out limit.

The RESET

output is an open drain output and requires a pull

up resistor.

Operational Notes

The device powers-up in the following state:

• The device is in the low power standby state.

• A HIGH to LOW transition on CS

active state and receive an instruction.

• SO pin is high impedance.

• The write enable latch is reset.

• Reset signal is active for t

is required to enter an

PURST

FN8127 Rev 4.00 Page 8 of 21 November 12, 2015

Page 9

X5083

0123456789

SCK

High Impedance

Read Instruction

(1 Byte)

Byte Address (2 Byte)

Data Out

1514 3210

20 21 22 23 24 25 26 27 28 29 30

76543210

FIGURE 5. READ OPERATION SEQUENCE

01234567

SCK

Read Status Instruction

SO = Status Reg When no Nonvolatile

Write Cycle

...

B L 2

L 1

B L 0

D 0

D 1

FIGURE 6. READ STATUS OPERATION SEQUENCE

Data Protection

The following circuitry has been included to prevent inadvertent writes:

• A WREN instruction must be issued to set the write enable latch.

•CS must come HIGH at the proper clock count in order to start a nonvolatile write cycle.

• When V inhibited.

is below V

, communications to the device are

TRIP

FN8127 Rev 4.00 Page 9 of 21 November 12, 2015

Page 10

X5083

01234567

SCK

High Impedance

Instruction

(1 Byte)

FIGURE 7. WREN/WRDI SEQUENCE

32 33 34 35 36 37 38 39

SCK

012345678910

SCK

Instruction 16 Bit Address

Data Byte 1

76543210

40 41 42 43 44 45 46 47

Data Byte 2

76543210

Data Byte 3

76543210

Data Byte N

15 14 13 3 2 1 0

20 21 22 23 24 25 26 27 28 29 30 31

654 321 0

FIGURE 8. EEPROM ARRAY WRITE SEQUENCE

0123456789

SCK

High Impedance

Instruction

10 11 12 13 14 15

Data Byte

65432 10

D 1

D 0

L 1

L 0

FIGURE 9. STATUS REGISTER WRITE SEQUENCE

FN8127 Rev 4.00 Page 10 of 21 November 12, 2015

Page 11

X5083

01234567

SCK

SO MSB HIGH while in the Nonvolatile write cycle

01234567

READ STATUS INSTRUCTION

SO MSB still HIGH indicates Nonvolatile write cycle still in progress

01234567

SCK

01234567

READ STATUS INSTRUCTION

1st detected SO MSB LOW indicates end of Nonvolatile write cycle

43210

WD1

WD0

BL2

BL1

BL0

NONVOLATILE WRITE IN PROGRESS

NONVOLATILE WRITE ENDS

FIGURE 10. READ NONVOLATILE WRITE STATUS

FN8127 Rev 4.00 Page 11 of 21 November 12, 2015

Page 12

X5083

012345

SCK

INSTRUCTION

Non-volatile

Write

Operation

Wait tWC after a write for new operation, if not using polling procedure

FIGURE 11. END OF NONVOLATILE WRITE (NO POLLING)

WAVEFORM INPUTS OUTPUTS

Must be steady

Will be steady

May change from LOW to HIGH

Will change from LOW to HIGH

May change from HIGH to LOW

Will change from HIGH to LOW

Don’t Care: Changes Allowed

Changing: State Not Known

N/A Center Line

is High Impedance

Symbol Table

FN8127 Rev 4.00 Page 12 of 21 November 12, 2015

Page 13

X5083

Absolute Maximum Ratings Operating Conditions

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . .-65°C to 135°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to 150°C

Voltage on Any Pin with Respect To V

. . . . . . . . . . . . . -1.0V to 7V

D.C. Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA

Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Temperature Range

Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C

Range

-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

Blank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V

DC Electrical Specifications (Over the recommended operating conditions unless otherwise specified.)

LIMITS

SYMBOL PARAMETER TEST CONDITIONS

CC1

CC2

SB1

SB2

SB3

(Note 1) Input LOW Voltage -0.5 V

VIH (Note 1) Input HIGH Voltage V

OL1

OL2

OL3

OH1

OH2

OH3

OLRS

VCC Write Current (Active) SCK = VCC x 0.1/VCC x 0.9 @ 5MHz,

SO = Open

VCC Read Current (Active) SCK = VCC x 0.1/VCC x 0.9 @ 5MHz,

SO = Open

VCC Standby Current WDT = OFF CS = VCC, VIN = VSS or VCC,

= 5.5V

VCC Standby Current WDT = ON CS = VCC, VIN = VSS or VCC,

= 5.5V

VCC Standby Current WDT = ON CS = VCC, VIN = VSS or VCC,

= 3.6V

Input Leakage Current VIN = VSS to VCC 0.110µA

Output Leakage Current V

= VSS to V

OUT

0.1 10 µA

x 0.7 V

Output LOW Voltage VCC > 3.3V, IOL = 2.1mA 0.4 V

Output LOW Voltage 2V < VCC  3.3V, IOL = 1mA 0.4 V

Output LOW Voltage VCC  2V, IOL = 0.5mA 0.4 V

Output HIGH Voltage VCC > 3.3V, IOH = -1.0mA V

Output HIGH Voltage 2V < VCC  3.3V, IOH = -0.4mA V

Output HIGH Voltage VCC  2V, IOH = -0.25mA V

Reset Output LOW Voltage I

= 1mA 0.4 V

- 0.8 V

- 0.4 V

- 0.2 V

5mA

0.4 mA

1µA

50 µA

20 µA

x 0.3 V

+ 0.5 V

UNITMIN TYP MAX

Power-Up Timing

SYMBOL PARAMETER MIN MAX UNIT

(Note 2) Power-up to read operation 1 ms

PUR

(Note 2) Power-up to write operation 5 ms

PUW

Capacitance T

= +25°C, f = 1MHz, VCC = 5V

SYMBOL TEST MAX UNIT CONDITIONS

(Note 2) Output capacitance (SO, RESET, RESET) 8 pF V

OUT

(Note 2) Input capacitance (SCK, SI, CS, WP)6pFV

OUT

= 0V

NOTES:

min. and VIH max. are for reference only and are not tested.

1. V

2. This parameter is periodically sampled and not 100% tested.

FN8127 Rev 4.00 Page 13 of 21 November 12, 2015

Page 14

X5083

100pF

3.3k

RESET

30pF

1.64k

OUTPUT

Equivalent A.C. Load Circuit at 5V V

A.C. Test Conditions

Input pulse levels VCC x 0.1 to VCC x 0.9

Input rise and fall times 10ns

Input and output timing level V

x 0.5

AC Electrical Specifications (Over recommended operating conditions, unless otherwise specified)

2.7V-5.5V

SYMBOL PARAMETER

DATA INPUT TIMING

SCK

CYC

LEAD

LAG

(Note 3) Input rise time 2µs

(Note 3) Input fall time 2µs

(Note 4) Write cycle time 10 ms

Clock frequency 0 3.3 MHz

Cycle time 300 ns

CS lead time 150 ns

CS lag time 150 ns

Clock HIGH time 130 ns

Clock LOW time 130 ns

Data setup time 20 ns

Data hold time 20 ns

CS deselect time 100 ns

DATA OUTPUT TIMING

SCK

DIS

(Note 3) Output rise time 50 ns

(Note 3) Output fall time 50 ns

Clock frequency 0 3.3 MHz

Output disable time 150 ns

Output valid from clock low 130 ns

Output hold time 0 ns

NOTES:

3. This parameter is periodically sampled and not 100% tested.

is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.

4. t

UNITMIN MAX

FN8127 Rev 4.00 Page 14 of 21 November 12, 2015

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X5083

SCK

MSB Out MSB–1 Out LSB Out

ADDR

LSB IN

CYC

DIS

LAG

SCK

MSB IN

LAG

LEAD

LSB IN

High Impedance

PURST

RPD

RESET

0 Volts

TRIP

Serial Output Timing

Serial Input Timing

Power-Up and Power-Down Timing

FN8127 Rev 4.00 Page 15 of 21 November 12, 2015

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X5083

CST

RESET

WDO

RST

WDO

RST

RESET

Output Timing

SYMBOL PARAMETER MIN TYP MAX UNIT

TRIP

Reset trip point voltage, X5083PT-4.5A (Note 6) Reset trip point voltage, X5083PT Reset trip point voltage, X5083PT-2.7A Reset trip point voltage, X5083PT-2.7

PURST

(Note 5) VCC detect to reset/output 500 ns

RPD

(Note 5) VCC fall time 0.1 ns

(Note 5) VCC rise time 0.1 ns

RVALID

Power-up reset time out 100 200 280 ms

Reset valid V

4.5

4.25

2.85

2.55

4.63

4.38

2.93

2.63

4.75

4.5

3.00

2.7

NOTES:

5. This parameter is periodically sampled and not 100% tested.

6. PT = Package/Temperature

CS vs. RESET Timing

RESET Output Timing

SYMBOL PARAMETER MIN TYP MAX UNIT

WDO

CST

RST

Watchdog time out period,

WD1 = 1, WD0 = 1(default) WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0

100 450

OFF

200 600

1.4

300 800

CS pulse width to reset the watchdog 400 ns

Reset time out 100 200 300 ms

ms ms

sec

FN8127 Rev 4.00 Page 16 of 21 November 12, 2015

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X5083

SCK

0001h (set)

TRIP

)

TSU

THD

VPH

VPS

TRIP

VPO

PCS

02h06h

0003h (reset)WREN Write

Addr.

00 Data

Programming Timing Diagram

TRIP

Programming Parameters

TRIP

PARAMETER DESCRIPTION MIN MAX UNIT

VPS

VPH

PCS

TSU

THD

VPO

TRAN

NOTES:

7. V

TRIP

8. For custom V

program enable voltage setup time 1 µs

TRIP

program enable voltage hold time 1 µs

TRIP

programming CS inactive time 1 µs

TRIP

setup time 1µs

TRIP

hold (stable) time 10 ms

TRIP

write cycle time 10 ms

TRIP

program enable voltage off time (between successive adjustments) 0 µs

TRIP

program recovery period (between successive adjustments) 10 ms

TRIP

Programming voltage 15 18 V

programmed voltage range 2.0 5.0 V

TRIP

program variation after programming (0-75°C). (programmed at 25°C) -25 +25 mV

TRIP

programming parameters are periodically sampled and are not 100% tested.

settings, Contact Factory.

TRIP

FN8127 Rev 4.00 Page 17 of 21 November 12, 2015

Page 18

X5083

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision.

DATE REVISION CHANGE

November 12, 2015 FN8127.4 Updated Ordering Information table on page 3.

Added Revision History and About Intersil sections. Updated POD MDP0027 to POD M8.15E.

About Intersil

Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.

For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com

You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.

Reliability reports are also available from our website at www.intersil.com/support.

FN8127 Rev 4.00 Page 18 of 21 November 12, 2015

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X5083

Unless otherwise specified, tolerance : Decimal ± 0.05

The pin #1 identifier may be either a mold or mark feature.

Interlead flash or protrusions shall not exceed 0.25mm per side.

Dimension does not include interlead flash or protrusions.

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

Dimensions are in millimeters.1.

NOTES:

DETAIL "A"

SIDE VIEW “A

TYPICAL RECOMMENDED LAND PATTERN

TOP VIEW

0.25 AMC B

0.10 C

ID MARK

PIN NO.1

(0.35) x 45°

SEATING PLANE

GAUGE PLANE

0.25

(5.40)

(1.50)

4.90 ± 0.10

3.90 ± 0.10

1.27

0.43 ± 0.076

0.63 ±0.23

4° ± 4°

DETAIL "A"

0.22 ± 0.03

0.175 ± 0.075

1.45 ± 0.1

1.75 MAX

(1.27)

(0.60)

6.0 ± 0.20

Reference to JEDEC MS-012.

SIDE VIEW “B”

Package Outline Drawing

M8.15E

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

Rev 0, 08/09

FN8127 Rev 4.00 Page 19 of 21 November 12, 2015

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X5083

NOTE 5

SEATING PLANE

PIN #1 INDEX

12 N/2

Plastic Dual-In-Line Packages (PDIP)

MDP0031 PLASTIC DUAL-IN-LINE PACKAGE

SYMBOL PDIP8 PDIP14 PDIP16 PDIP18 PDIP20 TOLERANCE NOTES

A 0.210 0.210 0.210 0.210 0.210 MAX

A1 0.015 0.015 0.015 0.015 0.015 MIN

A2 0.130 0.130 0.130 0.130 0.130 ±0.005

b 0.018 0.018 0.018 0.018 0.018 ±0.002

b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015

c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002

D 0.375 0.750 0.750 0.890 1.020 ±0.010 1

E 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010

E1 0.250 0.250 0.250 0.250 0.250 ±0.005 2

e 0.100 0.100 0.100 0.100 0.100 Basic

eA 0.300 0.300 0.300 0.300 0.300 Basic

eB 0.345 0.345 0.345 0.345 0.345 ±0.025

L 0.125 0.125 0.125 0.125 0.125 ±0.010

N 8 14 16 18 20 Reference

Rev. B 2/99

NOTES:

1. Plastic or metal protrusions of 0.010” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.

4. Dimension eB is measured with the lead tips unconstrained.

5. 8 and 16 lead packages have half end-leads as shown.

FN8127 Rev 4.00 Page 20 of 21 November 12, 2015

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X5083



INDEX AREA

123

-B-

0.10(0.004) C AM BS

-A-

-C-

SEATING PLANE

0.10(0.004)

0.25(0.010) BM M

0.25

0.010

GAUGE

PLANE

NOTES:

1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)

0.05(0.002)

Thin Shrink Small Outline Plastic Packages (TSSOP)

M8.173

8 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

NOTESMIN MAX MIN MAX

A - 0.047 - 1.20 -

A1 0.002 0.006 0.05 0.15 -

A2 0.031 0.051 0.80 1.05 -

b 0.0075 0.0118 0.19 0.30 9

c 0.0035 0.0079 0.09 0.20 -

D 0.116 0.120 2.95 3.05 3

E1 0.169 0.177 4.30 4.50 4

e 0.026 BSC 0.65 BSC -

E 0.246 0.256 6.25 6.50 -

L 0.0177 0.0295 0.45 0.75 6

N8 87



Rev. 1 12/00

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Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

FN8127 Rev 4.00 Page 21 of 21 November 12, 2015

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted

in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

For information regarding Intersil Corporation and its products, see www.intersil.com

For additional products, see www.intersil.com/en/products.html