Datasheet X28HT010R-25, X28HT010R-20, X28HT010K-25, X28HT010K-20, X28HT010F-25 Datasheet (XICOR)

X28HT010

1M X28HT010 128K x 8 Bit

High Temperature, 5 Volt, Byte Alterable E2PROM

FEATURES

• 175°C Full Functionality

• Simple Byte and Page Write

—Single 5V Supply
—Self-Timed

—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem

• Highly Reliable Direct Write™ Cell

—Endurance: 10,000 Write Cycles
—Data Retention: 100 Years
—Higher Temperature Functionality is Possible

by Operating in the Byte Mode.

PIN CONFIGURATIONS

DESCRIPTION

The Xicor X28HT010 is a 128K x 8 E2PROM, fabricated
with Xicor's proprietary, high performance, floating gate
CMOS technology which provides Xicor products supe­rior high temperature performance characteristics. Like
all Xicor programmable non-volatile memories the
X28HT010 is a 5V only device. The X28HT010 features
the JEDEC approved pinout for byte-wide memories,
compatible with industry standard EPROMs.

The X28HT010 supports a 256-byte page write opera­tion, effectively providing a 19µs/byte write cycle and
enabling the entire memory to be typically written in less
than 2.5 seconds.

Xicor E2PROMs are designed and tested for applica­tions requiring extended endurance. Data retention is
specified to be greater than 100 years.

V

I/O
I/O
I/O

V

FLAT PACK

CERDIP

SOIC (R)

PGA

1

BB

A
A
A

16
15
12

A
A
A
A
A
A
A
A

SS

2
3
4
5

7

6

6

7

5

8

4
3
2
1
0
0
1
2

X28HT010

9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

6613 FHD F02

V
WE
NC
A
A
A
A
A
OE
A
CE
I/O
I/O
I/O
I/O
I/O

CC

14
13
8
9
11

10

I/O

I/O

I/O

I/O

0

2

15

17

A

0

14

A

3

11

A

5

9

A

7

7

A

15

5

A

16

4

I/O

16

(BOTTOM VIEW)

2NC36

V

3

A

1

13

A

2

12

A

4

10

A

6

8

A

12

6

7
6

3

19

V

1

SS

18

X28HT010

V

CC

BB

1NC35WE33

I/O

5

21

I/O

20

NC

34

6

22

CE

I/O

4

7

23

24

OE

A

10

25

26

A

A

11

A

NC

NC

9

28

A

8

13

30

A

14

31

27

29

32

5
4

6613 FHD F21

3

© Xicor, Inc. 1991, 1995, 1996 Patents Pending Characteristics subject to change without notice
6613-1.5 8/5/97 T2/C0/D0 EW

1

X28HT010

PIN DESCRIPTIONS
Addresses (A0–A16)

The Address inputs select an 8-bit memory location
during a read or write operation.

Chip Enable (CE)

The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consumption
is reduced.

Output Enable (OE)

The Output Enable input controls the data output buffers
and is used to initiate read operations.

Data In/Data Out (I/O0–I/O7)

Data is written to or read from the X28HT010 through the
I/O pins.

Write Enable (WE)

The Write Enable input controls the writing of data to the
X28HT010.

Back Bias Voltage (VBB)

It is required to provide -3V on pin 1. This negative
voltage improves higher temperature functionality.

PIN NAMES

Symbol Description

A0–A
I/O0–I/O

WE Write Enable
CE Chip Enable
OE Output Enable

V

BB

V

CC

V

SS

NC No Connect

16

Address Inputs

7

Data Input/Output

–3V
+5V
Ground

6613 PGM T01

FUNCTIONAL DIAGRAM

A8–A

A0–A

16

7

CE
OE

WE

V
V
V

CC
SS
BB

X BUFFERS

LATCHES AND

DECODER

Y BUFFERS

LATCHES AND

DECODER

CONTROL

LOGIC AND

TIMING

1M-BIT

E2PROM

ARRAY

I/O BUFFERS

AND LATCHES

I/O0–I/O

DATA INPUTS/OUTPUTS

7

6613 FHD F01

2

X28HT010

DEVICE OPERATION
Read

Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE
returning HIGH. This two line control architecture elimi­nates bus contention in a system environment. The data
bus will be in a high impedance state when either OE or
CE is HIGH.

Write

Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The X28HT010 supports both a
CE and WE controlled write cycle. That is, the address
is latched by the falling edge of either CE or WE,
whichever occurs last. Similarly, the data is latched
internally by the rising edge of either CE or WE, which­ever occurs first. A byte write operation, once initiated,
will automatically continue to completion, typically within
5ms.

Page Write Operation

The page write feature of the X28HT010 allows the
entire memory to be written in 5 seconds. Page write
allows two to two hundred fifty-six bytes of data to be
consecutively written to the X28HT010 prior to the
commencement of the internal programming cycle. The
host can fetch data from another device within the
system during a page write operation (change the source
address), but the page address (A8 through A16) for
each subsequent valid write cycle to the part during this
operation must be the same as the initial page address.

The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to two hundred fifty-six bytes
in the same manner as the first byte was written. Each
successive byte load cycle, started by the WE HIGH to
LOW transition, must begin within 100µs of the falling
edge of the preceding WE. If a subsequent WE HIGH to
LOW transition is not detected within 100µs, the internal
automatic programming cycle will commence. There is
no page write window limitation. Effectively the page
write window is infinitely wide, so long as the host
continues to access the device within the byte load cycle
time of 100µs.

HARDWARE DATA PROTECTION

• Default V

VCC is ≤3.4V.

Sense—All functions are inhibited when

CC

• Write inhibit—Holding either OE LOW, WE HIGH, or

CE HIGH will prevent an inadvertent write cycle
during power-up and power-down, maintaining data
integrity.

SYSTEM CONSIDERATIONS

Because the X28HT010 is frequently used in large
memory arrays it is provided with a two line control
architecture for both read and write operations. Proper
usage can provide the lowest possible power dissipation
and eliminate the possibility of contention where mul­tiple I/O pins share the same bus.

It has been demonstrated that markedly higher tem­perature performance can be obtained from this device
if CE is left enabled throughout the read and write
operation.

To gain the most benefit it is recommended that CE be
decoded from the address bus and be used as the
primary device selection input. Both OE and WE would
then be common among all devices in the array. For a
read operation this assures that all deselected devices
are in their standby mode and that only the selected
device(s) is outputting data on the bus.

Because the X28HT010 has two power modes, standby
and active, proper decoupling of the memory array is of
prime concern. Enabling CE will cause transient current
spikes. The magnitude of these spikes is dependent on
the output capacitive loading of the I/Os. Therefore, the
larger the array sharing a common bus, the larger the
transient spikes. The voltage peaks associated with the
current transients can be suppressed by the proper
selection and placement of decoupling capacitors. As a
minimum, it is recommended that a 0.1µF high fre­quency ceramic capacitor be used between VCC and
VSS at each device. Depending on the size of the array,
the value of the capacitor may have to be larger.

In addition, it is recommended that a 4.7µF electrolytic
bulk capacitor be placed between VCC and VSS for each
eight devices employed in the array. This bulk capacitor
is employed to overcome the voltage droop caused by
the inductive effects of the PC board traces.

The X28HT010 provides three hardware features that
protect nonvolatile data from inadvertent writes.

• Noise Protection—A WE pulse less than 10ns will not

initiate a write cycle.

3

X28HT010

ABSOLUTE MAXIMUM RATINGS*

Temperature under Bias

X28HT010 ................................. –55°C to +175°C

Voltage on any Pin with

Respect to V

.......................................

SS

–1V to +7V

D.C. Output Current .............................................5mA

Lead Temperature

(Soldering, 10 seconds).............................. 300°C

*COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

RECOMMEND OPERATING CONDITIONS

Temperature Min. Max.

High Temp. –40°C +175°C

6613 PGM T02.2

Supply Voltages Limits

X28HT010 5V ±5%

Back Bias Voltage: v –3V ±10%

6613 PGM T03.1

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)

Limits

Symbol Parameter Min. Max. Units Test Conditions

I

CC

VCC Current (Active) 50 mA CE = OE = VIL, WE = VIH,
(TTL Inputs) All I/O’s = Open, Address Inputs =

I

SB1

VCC Current (Standby) 3 mA CE = VIH, OE = V
(TTL Inputs) All I/O’s = Open, Other Inputs = V

I

LI

I

LO

(1)

V

lL

(1)

V

IH

V

OL

V

OH

I

BB

Notes: (1) VIL min. and VIH max. are for reference only and are not tested.

Input Leakage Current 20 µAVIN = VSS to V
Output Leakage Current 20 µAV
Input LOW Voltage –1 0.6 V
Input HIGH Voltage 2.2 VCC + 1 V
Output LOW Voltage 0.5 V IOL = 1mA
Output HIGH Voltage 2.6 V IOH = –400µA
Back Bias Current 200 µAVBB = –3V ±10%

.4V/2.4V Levels @ f = 5MHz

IL

CC

= VSS to VCC, CE = V

OUT

6613 PGM T04.2

IH

IH

4

X28HT010

POWER-UP TIMING

Symbol Parameter Max. Units

(2)

t

PUR

(2)

t

PUW

CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V

Symbol Parameter Max. Units Test Conditions

(2)

C

I/O

(2)

C

IN

ENDURANCE AND DATA RETENTION

Parameter Min. Max. Units

Endurance 10,000 Cycles per Byte
Data Retention 100 Years

Power-up to Read Operation 100 µs
Power-up to Write Operation 5 ms

Input/Output Capacitance 10 pF V
Input Capacitance 10 pF V

I/O
IN

6613 PGM T05

= 0V
= 0V

6613 PGM T06.1

6613 PGM T07

A.C. CONDITIONS OF TEST

Input Pulse Levels 0V to 3V
Input Rise and

Fall Times 10ns
Input and Output

MODE SELECTION

CE OE WE Mode I/O Power

L L H Read D
L H L Write D

H X X Standby and High Z Standby

Timing Levels 1.5V

6613 PGM T08.1

X L X Write Inhibit — —
X X H Write Inhibit — —

EQUIVALENT A.C. LOAD CIRCUIT

5V

1.92KΩ

OUTPUT

1.37KΩ

Note: (2) This parameter is periodically sampled and not 100%

tested.

100pF

6613 FHD F04.3

Write Inhibit

SYMBOL TABLE

WAVEFORM

INPUTS

Must be
steady

May change
from LOW
to HIGH

May change
from HIGH
to LOW

Don’t Care:
Changes
Allowed

N/A

OUT
IN

OUTPUTS

Will be
steady

Will change
from LOW
to HIGH

Will change
from HIGH
to LOW

Changing:
State Not
Known

Center Line
is High
Impedance

Active
Active

6613 PGM T09

5

X28HT010

A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Read Cycle Limits

X28HT010-20 X28HT010-25

Symbol Parameter Min. Max. Min. Max. Units

t

RC

t

CE

t

AA

t

OE

(3)

t

LZ

(3)

t

OLZ

(3)

t

HZ

(3)

t

OHZ

t

OH

Read Cycle

ADDRESS

CE

Read Cycle Time 200 250 ns
Chip Enable Access Time 200 250 ns
Address Access Time 200 250 ns
Output Enable Access Time 50 50 ns

CE LOW to Active Output 0 0 ns
OE LOW to Active Output 0 0 ns
CE HIGH to High Z Output 50 50 ns
OE HIGH to High Z Output 50 50 ns

Output Hold from Address Change 0 0 ns

6613 PGM T10.2

t

RC

t

CE

t

OE

OE

WE

DATA I/O

Note: (3) t

V

IH

t

OLZ

t

LZ

HIGH Z

min.,tHZ, t

LZ

CL = 5pF, from the point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.

min., and t

OLZ

are periodically sampled and not 100% tested. tHZ max. and t

OHZ

DATA VALID

6

t

t

OH

AA

t

HZ

DATA VALID

max. are measured, with

OHZ

t

OHZ

6613 FHD F05

X28HT010

Write Cycle Limits

Symbol Parameter Min. Max. Units

(4)

t

WC

t

AS

t

AH

t

CS

t

CH

t

CW

t

OES

t

OEH

t

WP

t

WPH

t

DV

t

DS

t

DH

t

DW

t

BLC

Write Cycle Time 10 ms
Address Setup Time 20 ns
Address Hold Time 100 ns
Write Setup Time 0 ns
Write Hold Time 0 ns

CE Pulse Width 200 ns
OE HIGH Setup Time 10 ns
OE HIGH Hold Time 10 ns
WE Pulse Width 200 ns
WE HIGH Recovery 200 ns

Data Valid 1 µs
Data Setup 100 ns
Data Hold 25 ns
Delay to Next Write 10 µs
Byte Load Cycle 0.4 100 µs

6613 PGM T11.1

WE Controlled Write Cycle

t

WC

ADDRESS

t

AS

t

CS

CE

OE

WE

DATA IN

DATA OUT

Notes: (4) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum

time the device requires to complete internal write operation.

t

OES

t

DV

t

AH

t

WP

DATA VALID

t

DS

t

OEH

HIGH Z

t

t

CH

DH

t

WPH

6613 FHD F06

7

X28HT010

CE Controlled Write Cycle

ADDRESS

CE

t

OES

t

AS

t

AH

t

CW

t

WC

t

WPH

OE

WE

DATA IN

DATA OUT

Page Write Cycle

(5)

OE

CE

WE

t

WP

t

CS

t

DV

t

WPH

t

BLC

t

DS

HIGH Z

t

OEH

DATA VALID

t

t

CH

DH

6613 FHD F07

ADDRESS *

(6)

I/O

BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 BYTE n+2

*For each successive write within the page write operation, A8–A16 should be the same or
writes to an unknown address could occur.

LAST BYTE

t

WC

6613 FHD F08

Notes: (5) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE

HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively
performing a polling operation.

(6) The timings shown above are unique to page write operations. Individual byte load operations within the page write must

conform to either the CE or WE controlled write cycle timing.

8

X28HT010

PACKAGING INFORMATION

32-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D

PIN 1

1.690 (42.95)
MAX.

0.610 (15.49)

0.500 (12.70)

0.005 (0.13) MIN.

0.100 (2.54) MAX.

SEATING

0.150 (3.8)
MIN.

0.200 (5.08)

0.150 (3.18)

PLANE

0.065 (1.65)

0.110 (2.79)

0.090 (2.29)

TYP. 0.018 (0.46)

0.015 (0.33)

0.008 (0.20)

0.033 (0.84)

TYP. 0.055 (1.40)

0.620 (15.75)

0.590 (14.99)

TYP. 0.614 (15.60)

0°

15°

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

0.232 (5.90) MAX.

0.060 (1.52)

0.015 (0.38)

0.023 (0.58)

0.014 (0.36)

TYP. 0.018 (0.46)

3926 FHD F09

9

X28HT010

PACKAGING INFORMATION

0.830 (21.08) MAX.

32-LEAD CERAMIC FLAT PACK TYPE F

1.228 (31.19)

1.000 (25.40)
PIN 1 INDEX

132

0.019 (0.48)

0.015 (0.38)

0.050 (1.27) BSC

0.007 (0.18)

0.004 (0.10)

0.045 (1.14) MAX.

0.005 (0.13) MIN.

0.488

0.430 (10.93)

0.370 (9.40)

0.270 (6.86)

0.347 (8.82)

0.330 (8.38)

0.030 (0.76)
MIN

0.045 (1.14)

0.026 (0.66)

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

0.120 (3.05)

0.090 (2.29)

3926 FHD F20

10

X28HT010

PACKAGING INFORMATION

36-LEAD CERAMIC PIN GRID ARRAY PACKAGE TYPE K

15 17 19 21 22

13

14 16 18 20 23

A

24

0.008 (0.20)

TYP. 0.180 (.010)

(4.57 ± .25)

4 CORNERS

0.770 (19.56)

0.750 (19.05)
SQ

12 11 25 26

10 9 27

8 7 29 30

5 2 36 34 32

6 31

4 3 1 35 33

TYP. 0.180 (.010)

(4.57 ± .25)

4 CORNERS

PIN 1 INDEX

A

28

TYP. 0.100 (2.54)

ALL LEADS

NOTE: LEADS 5, 14, 23, & 32

0.050 (1.27)

0.120 (3.05)

0.100 (2.54)

0.072 (1.83)

0.062 (1.57)

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

11

A

A

0.020 (0.51)

0.016 (0.41)

0.185 (4.70)

0.175 (4.45)

3926 FHD F21

X28HT010

PACKAGING INFORMATION

32-LEAD CERAMIC SMALL OUTLINE GULL WING PACKAGE TYPE R

0.340

±0.007

SEE DETAIL “A”
FOR LEAD
INFORMATION

0.165 TYP.

0.060 NOM.

0.020 MIN.

0.015 R TYP.

0.840
MAX.

0.0192

0.0138

0.050

0.440 MAX.

0.560 NOM.

0.750

±0.005

0.560"

TYPICAL

FOOTPRINT

0.035 TYP.

DETAIL “A”

0.050"

TYPICAL

0.015 R
TYP.

0.030" TYPICAL
32 PLACES

0.035 MIN.

0.050"

TYPICAL

NOTES:

1. ALL DIMENSIONS IN INCHES

2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES

3926 FHD F27

12

X28HT010

ORDERING INFORMATION

X28HT010 X X -X

Device

Access Time

–25 = 250ns
–20 = 200ns

Temperature Range

Blank = 25°C to +175°C

Package

D = 32-Lead Cerdip
F = 32-Lead Flat Pack
K = 36-Lead Pin Grid Array
R = 32-Lead Ceramic SOIC

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are
implied.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and
additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and back-up features to prevent such an occurence.

Xicor's products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.

13