Datasheet X28HC256KMB-90, X28HC256KMB-70, X28HC256KMB-15, X28HC256KMB-12, X28HC256KM-90 Datasheet (XICOR)
...Page 1
X28HC256
256K X28HC256 32K x 8 Bit
5 Volt, Byte Alterable E2PROM
FEATURES
• Access Time: 70ns
• Simple Byte and Page Write
—Single 5V Supply
—No External High Voltages or VPP Control
Circuits
—Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
• Low Power CMOS:
—Active: 60mA
—Standby: 500µA
• Software Data Protection
—Protects Data Against System Level
Inadvertent Writes
• High Speed Page Write Capability
• Highly Reliable Direct Write
—Endurance: 100,000 Write Cycles
—Data Retention: 100 Years
™
Cell
• Early End of Write Detection
—DATA Polling
—Toggle Bit Polling
DESCRIPTION
The X28HC256 is a second generation high performance CMOS 32K x 8 E2PROM. It is fabricated with
Xicor’s proprietary, textured poly floating gate technology, providing a highly reliable 5 Volt only nonvolatile
memory.
The X28HC256 supports a 128-byte page write operation, effectively providing a 24µs/byte write cycle and
enabling the entire memory to be typically rewritten in
less than 0.8 seconds. The X28HC256 also features
DATA Polling and Toggle Bit Polling, two methods of
providing early end of write detection. The X28HC256
also supports the JEDEC standard Software Data Protection feature for protecting against inadvertent writes
during power-up and power-down.
Endurance for the X28HC256 is specified as a minimum
100,000 write cycles per byte and an inherent data
retention of 100 years.
PIN CONFIGURATION
PLASTIC DIP
CERDIP
FLAT PACK
SOIC
A14
1
A
2
12
A
3
7
A
4
6
A
5
5
A
6
4
A
7
3
X28HC256
A
8
2
A
9
1
A
10
0
I/O
11
0
I/O
12
1
I/O
13
2
V
14
SS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
3859 FHD F02
V
WE
A
A
A
A
OE
A
CE
I/O
I/O
I/O
I/0
I/O
CC
13
8
9
11
10
LCC
PLCC
A7A12A14NC
4 3 2 1 32 31 30
5
A
6
6
A
5
7
A
4
8
A
3
A
2
A
1
A
0
7
NC
6
I/O
0
5
4
3
X28HC256
9
10
11
12
13
14 15 16 17 18 19 20
2
SS
I/O1I/O
NC
V
13
VCCWE
A
29
28
27
26
25
24
23
22
21
5
I/O3I/O4I/O
3859 FHD F03
A
A
A
NC
OE
A
CE
I/O
I/O
TSOP
A
1
2
A
2
8
9
11
10
1
A
3
0
I/O
4
0
I/O
5
1
I/O
6
2
NC
I/O
I/O
I/O
I/O
I/O
A
SS
NC
CE
7
8
9
10
3
11
4
12
5
13
6
14
7
15
16
10
X28HC256
3859 ILL F22
V
7
6
A
32
3
A
31
4
A
30
5
A
29
6
A
28
7
A
27
12
26
A
14
25
NC
24
V
CC
23
NC
22
WE
21
A
13
20
A
8
19
A
9
18
A
11
17
OE
©Xicor, Inc. 1991, 1995 Patents Pending Characteristics subject to change without notice
3859-2.8 8/5/97 T1/C0/D0 EW
1
Page 2
X28HC256
11
I/O
0
10
A
0
14
V
SS
9
A
1
8
A
2
7
A
3
6
A
4
5
A
5
2
A
12
28
V
CC
12
I/O
1
13
I/O
2
15
I/O
3
4
A
6
3
A
7
1
16
I/O
4
20
CE
22
OE
24
A
9
17
I/O
5
27
WE
19
I/O
7
21
A
10
23
A
11
25
A
8
18
I/O
6
26
A
13
X28HC256
(BOTTOM VIEW)
A
14
PIN DESCRIPTIONS
Addresses (A0–A14)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consumption
is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers
and is used to initiate read operations.
Data In/Data Out (I/O0–I/O7)
Data is written to or read from the X28HC256 through
the I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28HC256.
PIN NAMES
Symbol Description
A0–A
14
I/O0–I/O
7
Address Inputs
Data Input/Output
WE Write Enable
CE Chip Enable
OE Output Enable
V
CC
V
SS
+5V
Ground
NC No Connect
PIN CONFIGURATION
PGA
3859 PGM T01
FUNCTIONAL DIAGRAM
3859 FHD F04
256K-BIT
E2PROM
ARRAY
A0–A
X BUFFERS
LATCHES AND
DECODER
14
ADDRESS
INPUTS
Y BUFFERS
LATCHES AND
I/O BUFFERS
AND LATCHES
DECODER
I/O0–I/O
7
DATA INPUTS/OUTPUTS
CE
OE
WE
V
V
CC
SS
CONTROL
LOGIC AND
TIMING
3859 FHD F01
3859 FHD F01
2
Page 3
X28HC256
DEVICE OPERATION
Read
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE
returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data
bus will be in a high impedance state when either OE or
CE is HIGH.
Write
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The X28HC256 supports both a
CE and WE controlled write cycle. That is, the address
is latched by the falling edge of either CE or WE,
whichever occurs last. Similarly, the data is latched
internally by the rising edge of either CE or WE,
whichever occurs first. A byte write operation, once
initiated, will automatically continue to completion, typically within 3ms.
Page Write Operation
The page write feature of the X28HC256 allows the
entire memory to be written in typically 0.8 seconds.
Page write allows up to one hundred twenty-eight bytes
of data to be consecutively written to the X28HC256
prior to the commencement of the internal programming
cycle. The host can fetch data from another device
within the system during a page write operation (change
the source address), but the page address (A7 through
A14) for each subsequent valid write cycle to the part
during this operation must be the same as the initial
page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to one hundred twentyseven bytes in the same manner as the first byte was
written. Each successive byte load cycle, started by the
WE HIGH to LOW transition, must begin within 100µs of
the falling edge of the preceding WE. If a subsequent
WE HIGH to LOW transition is not detected within
100µs, the internal automatic programming cycle will
commence. There is no page write window limitation.
Effectively the page write window is infinitely wide, so
long as the host continues to access the device within
the byte load cycle time of 100µs.
Write Operation Status Bits
The X28HC256 provides the user two write operation
status bits. These can be used to optimize a system write
cycle time. The status bits are mapped onto the I/O bus as
shown in Figure 1.
Figure 1. Status Bit Assignment
5TBDP 43210I/O
RESERVED
TOGGLE BIT
DATA POLLING
3859 FHD F11
DATA Polling (I/O7)
The X28HC256 features DATA Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a simple
bit test operation to determine the status of the
X28HC256, eliminating additional interrupt inputs or
external hardware. During the internal programming
cycle, any attempt to read the last byte written will
produce the complement of that data on I/O7 (i.e., write
data = 0xxx xxxx, read data = 1xxx xxxx). Once the
programming cycle is complete, I/O7 will reflect true
data.
Toggle Bit (I/O6)
The X28HC256 also provides another method for determining when the internal write cycle is complete. During
the internal programming cycle I/O6 will toggle from
HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read and write operations.
3
Page 4
X28HC256
DATA POLLING I/O
7
Figure 2. DATA Polling Bus Sequence
LAST
WRITE
WE
CE
OE
V
A0–A
I/O
IH
7
An An An An An An
14
HIGH Z
Figure 3. DATA Polling Software Flow
WRITE DATA
V
OH
V
OL
An
X28HC256
READY
3859 FHD F12
DATA Polling can effectively halve the time for writing to
the X28HC256. The timing diagram in Figure 2 illustrates the sequence of events on the bus. The software
flow diagram in Figure 3 illustrates one method of
implementing the routine.
WRITES
COMPLETE?
YES
SAVE LAST DATA
AND ADDRESS
READ LAST
ADDRESS
IO
7
COMPARE?
YES
X28HC256
READY
NO
NO
3859 FHD F13
4
Page 5
X28HC256
THE TOGGLE BIT I/O
6
Figure 4. Toggle Bit Bus Sequence
LAST
WRITE
WE
CE
OE
V
I/O
6
* I/O6 beginning and ending state of I/O6 will vary.
OH
*
Figure 5. Toggle Bit Software Flow
LAST WRITE
YES
LOAD ACCUM
FROM ADDR n
HIGH Z
V
OL
*
X28HC256
READY
3859 FHD F14
The Toggle Bit can eliminate the software housekeeping
chore of saving and fetching the last address and data
written to a device in order to implement DATA Polling.
This can be especially helpful in an array comprised of
multiple X28HC256 memories that is frequently updated. The timing diagram in Figure 4 illustrates the
sequence of events on the bus. The software flow
diagram in Figure 5 illustrates a method for polling the
Toggle Bit.
COMPARE
ACCUM WITH
ADDR n
COMPARE
OK?
YES
X28HC256
READY
NO
3859 FHD F15
5
Page 6
X28HC256
HARDWARE DATA PROTECTION
The X28HC256 provides two hardware features that
protect nonvolatile data from inadvertent writes.
•Default V
when V
Sense—All write functions are inhibited
CC
is ≤ 3.5V Typically.
CC
•Write Inhibit—Holding either OE LOW, WE HIGH, or
CE HIGH will prevent an inadvertent write cycle during
power-up and power-down, maintaining data integrity.
SOFTWARE DATA PROTECTION
The X28HC256 offers a software controlled data protection feature. The X28HC256 is shipped from Xicor with
the software data protection NOT ENABLED; that is, the
device will be in the standard operating mode. In this
mode data should be protected during power-up/down
operations through the use of external circuits. The host
would then have open read and write access of the
device once VCC was stable.
The X28HC256 can be automatically protected during
power-up and power-down without the need for external
circuits by employing the software data protection feature. The internal software data protection circuit is
enabled after the first write operation utilizing the software algorithm. This circuit is nonvolatile and will remain
set for the life of the device unless the reset command
is issued.
Once the software protection is enabled, the X28HC256
is also protected from inadvertent and accidental writes
in the powered-up state. That is, the software algorithm
must be issued prior to writing additional data to the
device.
SOFTWARE ALGORITHM
Selecting the software data protection mode requires
the host system to precede data write operations by a
series of three write operations to three specific addresses. Refer to Figure 6 and 7 for the sequence. The
three-byte sequence opens the page write window
enabling the host to write from one to one hundred
twenty-eight bytes of data. Once the page load cycle has
been completed, the device will automatically be returned to the data protected state.
6
Page 7
X28HC256
SOFTWARE DATA PROTECTION
Figure 6. Timing Sequence—Byte or Page Write
V
CC
0V
CE
WE
DATA
ADDRESS
AA
5555
Figure 7. Write Sequence for
Software Data Protection
WRITE DATA AA
TO ADDRESS
5555
WRITE DATA 55
TO ADDRESS
2AAA
55
2AAA
A0
5555
≤t
≤t
BLC MAX
BLC MAX
(VCC)
WRITES
OK
BYTE
OR
PAGE
t
WC
WRITE
PROTECTED
3859 FHD F16
Regardless of whether the device has previously been
protected or not, once the software data protection
algorithm is used and data has been written, the
X28HC256 will automatically disable further writes unless another command is issued to cancel it. If no further
commands are issued the X28HC256 will be write
protected during power-down and after any subsequent
power-up.
Note: Once initiated, the sequence of write operations
should not be interrupted.
WRITE DATA A0
TO ADDRESS
5555
WRITE DATA XX
TO ANY
ADDRESS
WRITE LAST
BYTE TO
LAST ADDRESS
AFTER t
RE-ENTERS DATA
PROTECTED STATE
WC
BYTE/PAGE
LOAD ENABLED
OPTIONAL
BYTE OR
PAGE WRITE
ALLOWED
3859 FHD F06
7
Page 8
X28HC256
RESETTING SOFTWARE DATA PROTECTION
Figure 8. Reset Software Data Protection Timing Sequence
V
CC
DATA
ADDRESS
CE
WE
AA
5555
55
2AAA
Figure 9. Write Sequence for resetting
Software Data Protection
WRITE DATA AA
TO ADDRESS
5555
WRITE DATA 55
TO ADDRESS
2AAA
WRITE DATA 80
TO ADDRESS
5555
80
5555
AA
5555
55
2AAA
20
5555
t
WC
STANDARD
OPERATING
MODE
3859 FHD F18
In the event the user wants to deactivate the software
data protection feature for testing or reprogramming in
an E2PROM programmer, the following six step algorithm will reset the internal protection circuit. After tWC,
the X28HC256 will be in standard operating mode.
Note: Once initiated, the sequence of write operations
should not be interrupted.
WRITE DATA AA
TO ADDRESS
5555
WRITE DATA 55
TO ADDRESS
2AAA
WRITE DATA 20
TO ADDRESS
5555
AFTER tWC,
RE-ENTERS
UNPROTECTED
STATE
3859 FHD F19
8
Page 9
X28HC256
SYSTEM CONSIDERATIONS
Because the X28HC256 is frequently used in large
memory arrays it is provided with a two line control
architecture for both read and write operations. Proper
usage can provide the lowest possible power dissipation
and eliminate the possibility of contention where multiple I/O pins share the same bus.
To gain the most benefit it is recommended that CE be
decoded from the address bus and be used as the
primary device selection input. Both OE and WE would
then be common among all devices in the array. For a
read operation this assures that all deselected devices
are in their standby mode and that only the selected
device(s) is outputting data on the bus.
Because the X28HC256 has two power modes, standby
and active, proper decoupling of the memory array is of
prime concern. Enabling CE will cause transient current
spikes. The magnitude of these spikes is dependent on
the output capacitive loading of the l/Os. Therefore, the
larger the array sharing a common bus, the larger the
transient spikes. The voltage peaks associated with the
current transients can be suppressed by the proper
selection and placement of decoupling capacitors. As a
minimum, it is recommended that a 0.1µF high frequency ceramic capacitor be used between VCC and
VSS at each device. Depending on the size of the array,
the value of the capacitor may have to be larger.
In addition, it is recommended that a 4.7µF electrolytic
bulk capacitor be placed between VCC and VSS for each
eight devices employed in the array. This bulk capacitor
is employed to overcome the voltage droop caused by
the inductive effects of the PC board traces.
9
Page 10
X28HC256
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias
X28HC256 .................................. –10°C to +85°C
X28HC256I, X28HC256M ......... –65°C to +135°C
Storage Temperature .......................–65°C to +150°C
Voltage on any Pin with
Respect to VSS.................................. –1V to +7V
D.C. Output Current ...........................................10mA
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Lead Temperature (Soldering, 10 seconds)...... 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature Min. Max.
Commercial 0°C +70°C
Industrial –40°C +85°C
Supply Voltage Limits
X28HC256 5V ±10%
3859 PGM T03.1
Military –55°C +125°C
3859 PGM T02.1
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Limits
Symbol Parameter Min. Typ.
I
CC
VCC Active Current 30 60 mA CE = OE = VIL, WE = VIH,
(7)
Max. Units Test Conditions
(TTL Inputs) All I/O’s = Open, Address Inputs =
.4V/2.4V Levels @ f = 10MHz
I
SB1
I
SB2
VCC Standby Current 1 2 mA CE = VIH, OE = VIL, All I/O’s =
(TTL Inputs) Open, Other Inputs = V
IH
VCC Standby Current 200 500 µA CE = VCC – 0.3V, OE = GND,
(CMOS Inputs) All I/Os = Open,
I
I
V
V
V
V
LI
LO
lL
IH
OL
OH
(2)
(2)
Other Inputs = V
Input Leakage Current 10 µAVIN = VSS to V
Output Leakage Current 10 µAV
= VSS to VCC, CE = V
OUT
Input LOW Voltage –1 0.8 V
Input HIGH Voltage 2 VCC + 1 V
Output LOW Voltage 0.4 V IOL = 6mA
Output HIGH Voltage 2.4 V IOH = –4mA
CC
CC
– 0.3V
IH
3859 PGM T04.2
Notes: (1) Typical values are for TA = 25°C and nominal supply voltage.
(2) VIL min. and VIH max. are for reference only and are not tested.
10
Page 11
X28HC256
POWER-UP TIMING
Symbol Parameter Max. Units
(3)
t
PUR
(3)
t
PUW
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V.
Symbol Test Max. Units Conditions
(9)
C
I/O
(9)
C
IN
Input/Output Capacitance 10 pF V
Input Capacitance 6 pF V
ENDURANCE AND DATA RETENTION
Parameter Min. Max. Units
Endurance 100,000 Cycles
Data Retention 100 Years
Power-Up to Read 100 µs
Power-Up to Write 5 ms
I/O
IN
= 0V
= 0V
3859 PGM T05
3859 PGM T06.2
3859 PGM T07.3
A.C. CONDITIONS OF TEST
Input Pulse Levels 0V to 3V
Input Rise and
Fall Times 5ns
Input and Output
Timing Levels 1.5V
3859 PGM T08.1
MODE SELECTION
CE OE WE Mode I/O Power
L L H Read D
L H L Write D
H X X Standby and Write Inhibit High Z Standby
X L X Write Inhibit — —
X X H Write Inhibit — —
Note: (3) This parameter is periodically sampled and not 100%
tested.
EQUIVALENT A.C. LOAD CIRCUIT
5V
1.92KΩ
OUTPUT
1.37KΩ
30pF
3859 FHD F20.3
SYMBOL TABLE
WAVEFORM
INPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
OUT
IN
OUTPUTS
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
Active
Active
3859 PGM T09
11
Page 12
X28HC256
A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Read Cycle Limits
X28HC256-70 X28HC256-90 X28HC256-12 X28HC256-15
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Units
(5)
t
RC
t
CE
t
AA
t
OE
tLZ
t
OLZ
tHZ
t
OHZ
t
OH
Read Cycle
Read Cycle Time 70 90 120 150 ns
(5)
Chip Enable Access Time 70 90 120 150 ns
(5)
Address Access Time 70 90 120 150 ns
Output Enable Access Time 35 40 50 50 ns
(4)
CE LOW to Active Output 0 0 0 0 ns
(4)
OE LOW to Active Output 0 0 0 0 ns
(4)
CE HIGH to High Z Output 35 40 50 50 ns
(4)
OE HIGH to High Z Output 35 40 50 50 ns
Output Hold From Address Change 0 0 0 0 ns
t
RC
3859 PGM T10.2
ADDRESS
t
CE
CE
t
OE
OE
V
WE
DATA I/O
Notes: (4) tLZ min., tHZ, t
(5) For faster 256K products, refer to X28VC256 product line.
IH
t
OLZ
t
LZ
HIGH Z
min. and t
from the point whin CE, OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
OLZ
are periodically sampled and not 100% tested, tHZ and t
OHZ
DATA VALID
t
t
OH
AA
t
HZ
DATA VALID
are measured, with CL = 5pF,
OHZ
t
OHZ
3859 FHD F05
12
Page 13
X28HC256
Write Cycle Limits
Symbol Parameter Min. Typ.
(7)
t
WC
t
AS
t
AH
t
CS
t
CH
t
CW
t
OES
t
OEH
t
WP
t
WPH
t
DV
t
DS
t
DH
t
DW
t
BLC
(8)
(8)
Write Cycle Time 3 5 ms
Address Setup Time 0 ns
Address Hold Time 50 ns
Write Setup Time 0 ns
Write Hold Time 0 ns
CE Pulse Width 50 ns
OE HIGH Setup Time 0 ns
OE HIGH Hold Time 0 ns
WE Pulse Width 50 ns
WE HIGH Recovery (page write only) 50 ns
Data Valid 1 µs
Data Setup 50 ns
Data Hold 0 ns
Delay to Next Write after Polling is True 10 µs
Byte Load Cycle 0.15 100 µs
(6)
Max. Units
3859 PGM T11.3
WE Controlled Write Cycle
t
WC
ADDRESS
t
AS
t
CS
CE
OE
WE
DATA IN
DATA OUT
Notes: (6) Typical values are for TA = 25°C and nominal supply voltage.
(7) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation.
(8) t
and tDW are periodically sampled and not 100% tested.
WPH
t
OES
t
AH
t
WP
t
OEH
DATA VALID
t
DS
HIGH Z
t
t
CH
DH
3859 FHD F06
13
Page 14
X28HC256
CE Controlled Write Cycle
ADDRESS
CE
t
AS
t
AH
t
CW
t
WC
OE
WE
DATA IN
DATA OUT
Page Write Cycle
(9)
OE
CE
WE
t
OES
t
WP
t
CS
t
WPH
t
BLC
t
DS
HIGH Z
t
OEH
DATA VALID
t
CH
t
DH
3859 FHD F07
ADDRESS
(10)
I/O
BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 BYTE n+2
*For each successive write within the page write operation, A7–A14 should be the same or
writes to an unknown address could occur.
LAST BYTE
t
WC
3859 FHD F08
Notes: (9) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and
WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW
effectively performing a polling operation.
(10) The timings shown above are unique to page write operations. Individual byte load operations within the page write must
conform to either the CE or WE controlled write cycle timing.
14
Page 15
X28HC256
DATA Polling Timing Diagram
ADDRESS
CE
WE
OE
I/O
7
Toggle Bit Timing Diagram
CE
WE
OE
A
N
DIN=X D
(11)
t
OEH
(11)
t
OEH
A
N
=X D
OUT
t
WC
A
N
t
OES
t
DW
=X
OUT
3859 FHD F09
t
OES
I/O
6
*I/O
beginning and ending state will vary, depending upon actual tWC.
6
Note: (11) Polling operations are by definition read cycles and are therefore subject to read cycle timings.
HIGH Z
*
t
WC
t
DW
*
3859 FHD F10
15
Page 16
X28HC256
PACKAGING INFORMATION
PIN 1 INDEX
PIN 1
28-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
1.460 (37.08)
1.400 (35.56)
1.300 (33.02)
REF.
0.550 (13.97)
0.510 (12.95)
0.085 (2.16)
0.040 (1.02)
SEATING
PLANE
0.150 (3.81)
0.125 (3.17)
0.110 (2.79)
0.090 (2.29)
0.020 (0.51)
0.016 (0.41)
3926 FHD F04
TYP. 0.010 (0.25)
0.062 (1.57)
0.050 (1.27)
0.610 (15.49)
0.590 (14.99)
0°
15°
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
0.160 (4.06)
0.125 (3.17)
0.030 (0.76)
0.015 (0.38)
16
Page 17
X28HC256
PACKAGING INFORMATION
28-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D
PIN 1
1.490 (37.85)
1.435 (36.45)
1.30 (33.02)
REF.
0.610 (15.49)
0.500 (12.70)
0.100 (2.54)
0.035 (0.89)
SEATING
PLANE
0.200 (5.08)
0.125 (3.18)
0.110 (2.79)
0.090 (2.29)
TYP. 0.100 (2.54)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
TYP. 0.010 (0.25)
0.070 (1.78)
0.030 (0.76)
TYP. 0.055 (1.40)
0.620 (15.75)
0.590 (14.99)
TYP. 0.614 (15.60)
0.225 (5.72)
0.140 (3.56)
0.060 (1.52)
0.015 (0.38)
0.026 (0.66)
0.014 (0.36)
TYP. 0.018 (0.46)
0°
15°
3926 FHD F08
17
Page 18
X28HC256
PACKAGING INFORMATION
32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J
0.420 (10.67)
0.495 (12.57)
0.485 (12.32)
TYP. 0.490 (12.45)
0.453 (11.51)
0.447 (11.35)
TYP. 0.450 (11.43)
0.300 (7.62)
REF.
0.050 (1.27) TYP.
0.021 (0.53)
0.013 (0.33)
TYP. 0.017 (0.43)0.045 (1.14) x 45°
SEATING PLANE
±0.004 LEAD
CO – PLANARITY
—
0.015 (0.38)
0.095 (2.41)
0.060 (1.52)
0.140 (3.56)
0.100 (2.45)
TYP. 0.136 (3.45)
0.048 (1.22)
0.042 (1.07)
PIN 1
0.595 (15.11)
0.585 (14.86)
TYP. 0.590 (14.99)
0.553 (14.05)
0.547 (13.89)
TYP. 0.550 (13.97)
0.400
REF.
(10.16)
3° TYP.
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
18
3926 FHD F13
3926 Fhd F13
Page 19
X28HC256
PACKAGING INFORMATION
28-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.1040 (2.6416)
0.0940 (2.3876)
0.0192 (0.4877)
0.0138 (0.3505)
0.7080 (17.9832)
0.7020 (17.8308)
0.050 (1.270)
BSC
0.0160 (0.4064)
0.0100 (0.2540)
X 45°
0.2980 (7.5692)
0.2920 (7.4168)
0.0110 (0.2794)
0.0040 (0.1016)
0.4160 (10.5664)
0.3980 (10.1092)
BASE PLANE
SEATING PLANE
0° – 8°
0.0350 (0.8890)
0.0160 (0.4064)
0.0125 (0.3175)
0.0090 (0.2311)
3926 FHD F17
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES
3. BACK EJECTOR PIN MARKED “KOREA”
4. CONTROLLING DIMENSION: INCHES (MM)
19
Page 20
X28HC256
PACKAGING INFORMATION
32-PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE TYPE E
0.015 (0.38)
0.003 (0.08)
0.200 (5.08)
BSC
0.028 (0.71)
0.022 (0.56)
(32) PLCS.
0.150 (3.81) BSC
PIN 1
0.050 (1.27) BSC
0.458 (11.63)
0.442 (11.22)
0.458 (11.63)
––
0.300 (7.62)
BSC
0.020 (0.51) x 45° REF.
0.095 (2.41)
0.075 (1.91)
0.022 (0.56)
0.006 (0.15)
0.055 (1.39)
0.045 (1.14)
TYP. (4) PLCS.
0.040 (1.02) x 45° REF.
TYP. (3) PLCS.
0.120 (3.05)
0.060 (1.52)
0.088 (2.24)
0.050 (1.27)
0.560 (14.22)
0.540 (13.71)
0.400 (10.16)
BSC
132
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. TOLERANCE: ±1% NTL ±0.005 (0.127)
PIN 1 INDEX CORDER
0.558 (14.17)
––
20
3926 FHD F14
3926 Fhd F14
Page 21
X28HC256
PACKAGING INFORMATION
28-LEAD CERAMIC PIN GRID ARRAY PACKAGE TYPE K
12 13 15 17 18
11 10 14 16 19
9 8 20 21
A
0.008
0.660 (16.76)
0.640 (16.26)
7 6 22 23
5 2 28 24 25
4 3 1 27 26
TYP. 0.100
ALL LEADS
PIN 1 INDEX
0.080
0.070
A
NOTE: LEADS 4,12,18 & 26
4 CORNERS
0.080
0.070
0.100
0.080
0.072
0.061
A
0.050
0.020
0.016
A
0.561 (14.25)
0.541 (13.75)
0.185 (4.70)
0.175 (4.44)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F15
21
Page 22
X28HC256
PACKAGING INFORMATION
28-LEAD CERAMIC FLAT PACK
0.740 (18.80)
MAX.
0.006 (0.15)
0.003 (0.08)
0.370 (9.40)
0.250 (6.35)
TYP. 0.300 2 PLCS.
PIN 1 INDEX
128
0.440 (11.18)
MAX.
0.180 (4.57)
MIN.
0.019 (0.48)
0.015 (0.38)
0.050 (1.27) BSC
0.045 (1.14) MAX.
0.130 (3.30)
0.090 (2.29)
0.045 (1.14)
0.025 (0.66)
0.030 (0.76)
MIN.
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
22
3926 FHD F16
Page 23
X28HC256
PACKAGING INFORMATION
SEE NOTE 2
8.02 (0.315)
7.98 (0.314)
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) TYPE T
SEE NOTE 2
12.50 (0.492)
12.30 (0.484)
PIN #1 IDENT.
O 0.76 (0.03)
0.50 (0.0197) BSC
0.26 (0.010)
0.14 (0.006)
1.18 (0.046)
1.02 (0.040)
FOOTPRINT
0.58 (0.023)
0.42 (0.017)
SOLDER PADS
14.15 (0.557)
13.83 (0.544)
14.80 ± 0.05
(0.583 ± 0.002)
0.30 ± 0.05
(0.012 ± 0.002)
TYPICAL
32 PLACES
0.17 (0.007)
0.03 (0.001)
1.30 ± 0.05
(0.051 ± 0.002)
0.17 (0.007)
0.03 (0.001)
SEATING
PLANE
15 EQ. SPC. 0.50 ± 0.04
0.0197 ± 0.016 = 7.50 ± 0.06
(0.295 ± 0.0024) OVERALL
TOL. NON-CUMULATIVE
0.50 ± 0.04
(0.0197 ± 0.0016)
NOTE:
1. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES IN PARENTHESES).
23
3926 ILL F38.1
Page 24
X28HC256
ORDERING INFORMATION
X28HC256 X X -X
Device
Access Time
–70 = 70ns
–90 = 90ns
–12 = 120ns
–15 = 150ns
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
MB = MIL-STD-883
Package
P = 28-Lead Plastic DIP
D = 28-Lead Cerdip
J = 32-Lead PLCC
S = 28-Lead Plastic SOIC
E = 32-Pad LCC
K = 28-Pin Pin Grid Array
F = 28-Lead Flat Pack
T = 32-Lead TSOP
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are
implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and
additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and back-up features to prevent such an occurrence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
24
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