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X2804C
4K X2804C 512 x 8 Bit
5 Volt, Byte Alterable E2PROM
FEATURES
• 90ns Access Time
• Simple Byte and Page Write
—Single 5V Supply
—No External High Voltages or VPP Control
Circuits
—Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
• High Performance Advanced NMOS Technology
• Fast Write Cycle Times
—16 Byte Page Write Operation
—Byte or Page Write Cycle: 5ms Typical
—Complete Memory Rewrite: 640ms Typical
—Effective Byte Write Cycle Time: 300µs
Typical
• DATA Polling
—Allows User to Minimize Write Cycle Time
• JEDEC Approved Byte-Wide Pinout
• High Reliability
—Endurance: 10,000 Cycles
—Data Retention: 100 Years
DESCRIPTION
The Xicor X2804C is a 512 x 8 E2PROM, fabricated with
an advanced, high performance N-channel floating gate
MOS technology. Like all Xicor Programmable nonvolatile memories it is a 5V only device. The X2804C
features the JEDEC approved pinout for byte-wide
memories, compatible with industry standard RAMs,
ROMs and EPROMs.
The X2804C supports a 16-byte page write operation,
typically providing a 300µs/byte write cycle, enabling the
entire memory to be written in less than 640ms. The
X2804C also features DATA Polling, a system software
support scheme used to indicate the early completion of
a write cycle.
Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years.
PIN CONFIGURATION
PLASTIC DIP
A
1
7
A
2
6
A
3
5
A
4
4
A
5
3
A
6
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
SS
©Xicor, Inc. 1993, 1995 Patents Pending Characteristics subject to change without notice
6612-1.3 3/27/96 T2/C1/D1 NS
7
8
9
10
11
12
X2804C
24
V
CC
23
A
8
22
NC
21
WE
20
OE
19
NC
18
CE
17
I/O
7
16
I/O
6
15
I/O
5
14
I/0
4
13
I/O
3
6612 FHD F02.1
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X2804C
PIN DESCRIPTIONS
Addresses (A0–A8)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all
read/write operations. When CE is HIGH, power consumption is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers
and is used to initiate read operations.
PIN NAMES
Symbol Description
A0–A
8
I/O0–I/O
7
Address Inputs
Data Input/Output
WE Write Enable
CE Chip Enable
OE Output Enable
V
CC
V
SS
+5V
Ground
NC No Connect
6612 PGM T01
FUNCTIONAL DIAGRAM
A0–A
ADDRESS
INPUTS
8
CE
OE
WE
V
V
CC
SS
X BUFFERS
LATCHES AND
DECODER
Y BUFFERS
LATCHES AND
DECODER
CONTROL
LOGIC
4.096-BIT
E2PROM
ARRAY
I/O BUFFERS
AND LATCHES
I/O0–I/O
DATA INPUTS/OUTPUTS
7
6612 FHD F01
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X2804C
DEVICE OPERATION
Read
Read operations are initiated by both OE and CE LOW
and WE HIGH. The read operation is terminated by
either CE or OE returning HIGH. This two line control
architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state
when either OE or CE is HIGH.
Write
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The X2804C supports both a CE
and WE controlled write cycle. That is, the address is
latched by the falling edge of either CE or WE, whichever
occurs last. Similarly, the data is latched internally by the
rising edge of either CE or WE, whichever occurs first.
A byte write operation, once initiated, will automatically
continue to completion, typically within 5ms.
Page Write Operation
The page write feature of the X2804C allows the entire
memory to be typically written in 450ms. Page write
allows two to sixteen bytes of data to be consecutively
written to the X2804C prior to the commencement of the
internal programming cycle. Although the host system
may read data from any other device in the system to
transfer to the X2804C, the destination page address of
the X2804C should be the same on each subsequent
strobe of the WE and CE inputs. That is, A4 through A
must be the same for each transfer of data to the
X2804C during a page write cycle.
The page write mode can be entered during any write
operation. Following the initial byte write cycle, the host
can write an additional one to fifteen bytes in the same
manner as the first byte was written. Each successive
10
byte load cycle, started by the WE HIGH to LOW
transition, must begin within 20µs of the falling edge of
the preceding WE. If a subsequent WE HIGH to LOW
transition is not detected within 20µs, the internal automatic programming cycle will commence. There is no
page write window limitation. The page write window is
infinitely wide, so long as the host continues to access
the device within the byte load cycle time of 20µs.
DATA Polling
The X2804C features DATA Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a simple
bit test operation to determine the status of the X2804C,
eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the
complement of that data on I/O7 (i.e., write data = 0xxx
xxxx, read data = 1xxx xxxx). Once the programming
cycle is complete, I/O7 will reflect true data.
WRITE PROTECTION
There are three features that protect the nonvolatile data
from inadvertent writes.
• Noise Protection—A WE pulse which is typically
less than 10ns will not initiate a write cycle.
•VCC Sense—All functions are inhibited when VCC is
≤3V, typically.
• Write Inhibit—Holding either OE LOW, WE HIGH,
or CE HIGH during power-up and power-down, will
inhibit inadvertent writes. Write cycle timing specifications must be observed concurrently.
ENDURANCE
Xicor E2PROMs are designed and tested for applications requiring extended endurance.
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X2804C
SYSTEM CONSIDERATIONS
Because the X2804C is frequently used in large memory
arrays, it is provided with a two line control architecture
for both read and write operations. Proper usage can
provide the lowest possible power dissipation and eliminate the possibility of contention where multiple I/O pins
share the same bus.
To gain the most benefit, it is recommended that CE be
decoded from the address bus and be used as the
primary device selection input. Both OE and WE would
then be common among all devices in the array. For a
read operation this assures that all deselected devices
are in their standby mode and that only the selected
device(s) is outputting data on the bus.
Because the X2804C has two power modes, standby
and active, proper decoupling of the memory array is of
prime concern. Enabling CE will cause transient current
spikes. The magnitude of these spikes is dependent on
the output capacitive loading of the l/Os. Therefore, the
larger the array sharing a common bus, the larger the
transient spikes. The voltage peaks associated with the
current transients can be suppressed by the proper
selection and placement of decoupling capacitors. As a
minimum, it is recommended that a 0.1µF high frequency ceramic capacitor be used between VCC and
VSS at each device. Depending on the size of the array,
the value of the capacitor may have to be larger.
In addition, it is recommended that a 4.7µF electrolytic
bulk capacitor be placed between VCC and VSS for each
eight devices employed in the array. This bulk capacitor
is employed to overcome the voltage droop caused by
the inductive effects of the PC board traces.
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X2804C
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias
X2804C....................................... –10°C to +85°C
X2804CI.....................................–65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to VSS.................................. –1V to +7V
D.C. Output Current .............................................5mA
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Lead Temperature (Soldering, 10 seconds)...... 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature Min. Max.
Commercial 0°C +70°C
Industrial –40°C +85°C
6612 PGM T02.2
Supply Voltage Limits
X2804C 5V ±10%
6612 PGM T03
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Limits
Symbol Parameter Min. Typ.
I
CC
VCC Current (Active) 70 110 mA CE = OE = V
(1)
Max. Units Test Conditions
IL
All I/O’s = Open
Other Inputs = V
I
SB
VCC Current (Standby) 35 50 mA CE = VIH, OE = V
CC
IL
All I/O’s = Open
Other Inputs = V
I
LI
I
LO
(2)
V
lL
(2)
V
IH
V
OL
V
OH
Input Leakage Current 10 µAV
Output Leakage Current 10 µAV
= VSS to V
IN
= VSS to VCC, CE = V
OUT
Input LOW Voltage –1 0.8 V
Input HIGH Voltage 2 VCC +1 V
Output LOW Voltage 0.4 V IOL = 2.1mA
Output HIGH Voltage 2.4 V IOH = –400µA
CC
CC
IH
6612 PGM T02.1
Notes: (1) Typical values are for TA = 25°C and nominal supply voltage and are not tested.
(2) VIL min. and VIH max. are for reference only and are not tested.
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X2804C
ENDURANCE AND DATA RETENTION
Parameter Min. Max. Unit
Minimum Endurance 10,000 Cycles/Byte
Data Retention 100 Years
POWER-UP TIMING
Symbol Parameter Typ.
(3)
t
PUR
t
PUW
(3)
Power-Up to Read Operation 1 ms
Power-Up to Write Operation 5 ms
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
Symbol Test Max. Units Conditions
(3)
C
I/O
(3)
C
IN
Input/Output Capacitance 10 pF V
Input Capacitance 6 pF V
(1)
Units
I/O
IN
= 0V
= 0V
6612 PGM T03
6612 PGM T04
6612 PGM T05.1
A.C. CONDITIONS OF TEST
Input Pulse Levels 0V to 3V
Input Rise and
Fall Times 5ns
Input and Output
Timing Levels 1.5V
3852 PGM T06.1
MODE SELECTION
CE OE WE Mode I/O Power
L L H Read D
L H L Write D
H X X Standby and Write Inhibit High Z Standby
X L X Write Inhibit — —
X X H Write Inhibit — —
Note: (3) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUITS
5V
1.92KΩ
OUTPUT
1.37KΩ
100pF
6612 FHD F22.3
OUT
IN
Active
Active
6612 PGM T07
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X2804C
A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Read Cycle Limits
X2804C-90 X2804C-15 X2804C-20 X2804C-25
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Units
t
RC
t
CE
t
AA
t
OE
(4)
t
LZ
(4)
t
OLZ
(4)
t
HZ
(4)
t
OHZ
t
OH
Read Cycle
Read Cycle Time 90 150 200 250 ns
Chip Enable Access Time 90 150 200 250 ns
Address Access Time 90 150 200 250 ns
Output Enable Access Time 60 80 100 100 ns
CE LOW to Active Output 0 0 0 0 ns
OE LOW to Active Output 0 0 0 0 ns
CE HIGH to High Z Output 50 60 60 60 ns
OE HIGH to High Z Output 50 60 60 60 ns
Output Hold from 0 0 0 0 ns
Address Change
6612 PGM T10.1
t
RC
ADDRESS
CE
OE
V
IH
WE
DATA I/O
Notes: (4) tLZ min., tHZ, t
HIGH Z
point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
OLZ
, and t
t
CE
t
OE
t
OLZ
t
LZ
DATA VALID
are periodically sampled and not 100% tested. tHZ max. and t
OHZ
t
t
OH
AA
t
HZ
DATA VALID
max. are measured from the
OHZ
t
OHZ
6612 FHD F04
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X2804C
Write Cycle Limits
X2804C-90 X2804C-15,-20,-25
Symbol Parameter Min. Max. Min. Max. Units
(5)
t
WC
t
t
t
t
t
WPH
t
t
t
AS
t
AH
t
CS
t
CH
CW
OES
OEH
WP
t
DV
t
DS
t
DH
DW
BLC
Write Cycle Time 10 10 ms
Address Setup Time 5 5 ns
Address Hold Time 80 100 ns
Write Setup Time 0 0 ns
Write Hold Time 0 0 ns
CE Pulse Width 80 100 ns
OE HIGH Setup Time 10 10 ns
OE HIGH Hold Time 5 10 ns
WE Pulse Width 80 100 ns
WE HIGH Recovery 50 50 ns
Data Valid 100 100 µs
Data Setup 35 50 ns
Data Hold 5 10 ns
Delay to Next Write 10 10 µs
Byte Load Cycle 1 100 1 100 µs
6612 PGM T09.1
WE Controlled Write Cycle
t
WC
ADDRESS
t
AS
t
CS
CE
OE
WE
DATA IN
DATA OUT
Notes: (5) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation. For faster tWC, please refer to X28C16 and
X28HC16 product data sheets.
t
OES
t
DV
t
AH
t
WP
t
OEH
DATA VALID
t
DS
HIGH Z
t
DH
t
CH
6612 FHD F05
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X2804C
CE Controlled Write Cycle
ADDRESS
CE
t
OES
t
AS
t
AH
t
CW
t
WC
OE
WE
DATA IN
DATA OUT
Page Mode Write Cycle
(6)
OE
CE
t
WE
WP
t
CS
t
DV
t
WPH
t
BLC
t
DS
HIGH Z
t
OEH
DATA VALID
t
t
CH
DH
6612 FHD F06
(7)
ADDR.*
I/O
BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 BYTE n+2
*For each successive write within the page write operation, A4–A10 should be the same or
writes to an unknown address could occur.
LAST BYTE
t
WC
6612 FHD F07.1
Notes: (6) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE
HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively
performing a polling operation.
(7) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform
to either the CE or WE controlled write cycle timing.
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X2804C
DATA Polling Timing Diagram
ADDRESS An
CE
WE
OE
I/O
7
Note: (10) Polling operations are by definition read cycles and are therefore subject to read cycle timings.
(10)
An An
t
OEH
DIN=X D
=X D
OUT
t
WC
SYMBOL TABLE
t
OES
OUT
t
DW
=X
6612 FHD F08
WAVEFORM
INPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
OUTPUTS
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
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X2804C
Normalized Active Supply Current
vs. Ambient Temperature
1.4
1.2
CC
1.0
0.8
NORMALIZED I
0.6
–55 +25 +125
AMBIENT TEMPERA TURE (°C)
VCC = 5V
6612 FHD F09.1
Normalized Access Time
vs. Ambient Temperature
1.4
VCC = 5V
Normalized Standby Supply Current
vs. Ambient Temperature
1.4
1.2
SB
1.0
0.8
NORMALIZED I
0.6
–55 +25 +125
AMBIENT TEMPERA TURE (°C)
VCC = 5V
6612 FHD F10.1
1.2
AA
1.0
0.8
NORMALIZED T
0.6
–55 +25 +125
AMBIENT TEMPERA TURE (°C)
6612 FHD F11.1
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X2804C
PACKAGING INFORMATION
PIN 1 INDEX
PIN 1
24-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
1.265 (32.13)
1.230 (31.24)
1.100 (27.94)
REF.
0.557 (14.15)
0.530 (13.46)
0.080 (2.03)
0.065 (1.65)
SEATING
PLANE
0.150 (3.81)
0.125 (3.18)
0.110 (2.79)
0.090 (2.29)
0.065 (1.65)
0.040 (1.02)
0.625 (15.87)
0.600 (15.24)
TYP. 0.010 (0.25)
0°
15°
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
0.162 (4.11)
0.140 (3.56)
0.030 (0.76)
0.015 (0.38)
0.022 (0.56)
0.014 (0.36)
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3926 FHD F03
Page 13
X2804C
ORDERING INFORMATION
X2804C X X -X
Device
Access Time
–90 = 90ns
–15 = 150ns
–20 = 200ns
–25 = 250ns
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Package
P = 24-Lead Plastic DIP
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