Datasheet X25F128SI-5, X25F128SI, X25F128SE-5, X25F128SE, X25F128S-5 Datasheet (XICOR)

A

PPLICATION NOTE

A V A I L A B L E

AN61 • AN75 • AN77 • AN79 • AN82

X25F128

SerialFlash™ Memory With Block Lock™ Protection

X25F128 16K x 8 Bits

FEATURES

• 1MHz Clock Rate

• SPI Serial Interface

• 16K X 8 Bits
—32 Byte Small Sector Program Mode

• Low Power CMOS
—<1µA Standby Current
—<5mA Active Current

• 1.8V – 3.6V or 5V “Univolt” Read and
Program Power Supply Versions

• Block Lock Protection
—Protect 1/4, 1/2 or all of E2PROM Array

• Built-in Inadvertent Program Protection
—Power-Up/Power-Down protection circuitry
—Program Enable Latch
—Program Protect Pin

• Self-Timed Program Cycle
—5ms Program Cycle Time (Maximum)

• High Reliability
—Endurance: 100,000 cycles per byte
—Data Retention: 100 Years
—ESD protection: 2000V on all pins

• 8-Lead PDlP Package

• 16-Lead 150 mil SOIC Package

DESCRIPTION

The X25F128 is a 131,072-bit CMOS SerialFlash
memory, internally organized 16K X 8. It features a
“Univolt” Program and Read voltage, Serial Peripheral
Interface (SPI), and software protocol allowing operation
on a simple three-wire bus. The bus signals are a clock
input (SCK), plus separate data in (SI) and data out (SO)
lines. Access to the device is controlled through a chip
select (CS) input, allowing any number of devices to
share the same bus.

The X25F128 also features two additional inputs that
provide the end user with added flexibility. By asserting
the HOLD input, the X25F128 will ignore transitions on
its inputs, thus allowing the host to service higher priority
interrupts. The PP input can be used as a hardwire input
to the X25F128 disabling all program attempts to the
status register, thus providing a mechanism for limiting
end user capability of altering 0, 1/4, 1/2, or all of the
memory.

The X25F128 utilizes Xicor’s proprietary flash cell, pro­viding a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.

FUNCTIONAL DIAGRAM

SI

SO

COMMAND

DECODE

SCK

CS

HOLD

PP

SerialFlash™ and Block Lock™ Protection are trademarks of Xicor, Inc.

© Xicor, Inc. 1995, 1996 Patents Pending Characteristics subject to change without notice
6829-1.9 4/7/97 T3/C0/D0 SH

AND CONTROL

LOGIC

PROGRAMMING

CONTROL LOGIC

X

DECODE

LOGIC

STATUS

REGISTER

1

DATA REGISTER

SECTOR DECODE LOGIC

32 8

MEMORY

ARRAY

HIGH VOLTAGE

CONTROL

6829 ILL F01.1

X25F128

PIN DESCRIPTIONS
Serial Output (SO)

SO is a push-pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.

Serial Input (SI)

SI is the serial data input pin. All opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the rising edge of the
serial clock.

Serial Clock (SCK)

The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the clock
input, while data on the SO pin change after the falling
edge of the clock input.

Chip Select (CS)

When CS is HIGH, the X25F128 is deselected and the
SO output pin is at high impedance and unless an
internal program operation is underway the X25F128
will be in the standby power mode. CS LOW enables
the X25F128, placing it in the active power mode. It
should be noted that after power-up, a HIGH to LOW
transition on CS is required prior to the start of any
operation.

Program Protect (PP)

When PP is LOW and the nonvolatile bit PPEN is “1”,
nonvolatile programming of the X25F128 status register
is disabled, but the part otherwise functions normally.
When PP is held HIGH, all functions, including nonvola-
tile programming operate normally. PP going LOW while
CS is still LOW will interrupt programming of the
X25F128 status register. If the internal program cycle
has already been initiated, PP going LOW will have no
effect on programming.

The PP pin function is blocked when the PPEN bit in
the status register is “0”. This allows the user to install the
X25F128 into a system with PP pin grounded and still
be able to program the status register. The PP pin
functions will be enabled when the PPEN bit is set “0”.

Hold (HOLD)
HOLD is used in conjunction with the CS pin to select the

device. Once the part is selected and a serial sequence
is underway, HOLD may be used to pause the serial
communication with the controller without resetting the
serial sequence. To pause, HOLD must be brought
LOW while SCK is LOW. To resume communication,
HOLD is brought HIGH, again while SCK is LOW. If the
pause feature is not used, HOLD should be held HIGH
at all times.

PIN CONFIGURATION

8-LEAD DIP

CS

1

SO

2

PP

V

SS

CS
SO
NC
NC
NC
NC
PP

V

SS

X25F128

3
4

16-LEAD SOIC

1
2
3
4

X25F128

5
6
7
8

16
15
14
13
12
11
10

8

V

CC

7

HOLD

6

SCK

5

SI

V

CC

HOLD
NC
NC
NC
NC
SCK

9

SI

6829 ILL F02.1

PIN NAMES

SYMBOL DESCRIPTION

CS Chip Select Input
SO Serial Output
SI Serial Input
SCK Serial Clock Input
PP Program Protect Input
V

SS

V

CC

Ground

Supply Voltage
HOLD Hold Input
NC No Connect

6829 PGM T01

2

X25F128

PRINCIPLES OF OPERATION

The X25F128 is a SerialFlash Memory designed
to interface directly with the synchronous serial periph­eral interface (SPI) of many popular microcontroller
families.

The X25F128 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on
the rising SCK. CS must be LOW and the HOLD and PP
inputs must be HIGH during the entire operation. The PP
input is “Don’t Care” if PPEN is set “0”.

Table 1 contains a list of the instructions and their
operation codes. All instructions, addresses and data
are transferred MSB first.

Data input is sampled on the first rising edge of SCK after
CS goes LOW. SCK is static, allowing the user to stop
the clock and then resume operations. If the clock line is
shared with other peripheral devices on the SPI bus, the
user can assert the HOLD input to place the X25F128
into a “PAUSE” condition. After releasing HOLD, the
X25F128 will resume operation from the point when
HOLD was first asserted.

Program Enable Latch

The X25F128 contains a program enable latch. This
latch must be SET before a program operation will be
completed internally. The PREN instruction will set the
latch and the PRDI instruction will reset the latch. This
latch is automatically reset on power-up and after the
completion of a sector program or status register write
cycle.

Status Register

The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a program cycle. The status register is

formatted as follows:

7 654 3 2 1 0

PPEN X X X BL1 BL0 PEL PIP

6829 PGM T02

PPEN, BL0, and BL1 are set by the PRSR instruction.
PEL and PIP are “read-only” and automatically set by
other operations.

The Programming-In-Process (PIP) bit indicates
whether the X25F128 is busy with a program operation.
When set to a “1” programming is in progress, when
set to a “0” no programming is in progress. During
programming, all other bits are set to “1”.

The Program Enable Latch (PEL) bit indicates the
status of the program enable latch. When set to a “1” the
latch is set; when set to a “0” the latch is reset.

The Block Lock (BL0 and BL1) bits are nonvolatile and
allow the user to select one of four levels of protection.
The X25F128 array is divided into four equal segments.
One, two, or all four of the segments may be locked. That
is, the user may read the segments, but will be unable to
alter (program) data within the selected segments. The
partitioning is controlled as illustrated below.

Status Register Bits Array Addresses

BL1 BL0 Locked

0 0 None
0 1 upper fourth
1 0 upper half
1 1 All

6829 PGM T03.1

Program-Protect Enable

The Program-Protect-Enable bit (PPEN) in the
X25F128 status register acts as an enable bit for the
PP pin.

Table 1. Instruction Set

Instruction Name Instruction Format* Operation

PREN 0000 0110 Set the Program Enable Latch (Enable Program Operations)

PRDI 0000 0100

Reset the Program Enable Latch (Disable Program Operations)
RDSR 0000 0101 Read Status Register
PRSR 0000 0001 Program Status Register
READ 0000 0011 Read from Memory Array beginning at Selected Address

PROGRAM 0000 0010

*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.

Program Memory Array beginning at Selected Address

(32 Bytes)

3

6829 PGM T04.1

X25F128

Locked Unlocked Status

PPEN PP PEL Blocks Blocks Register

0 X 0 Locked Locked Locked
0 X 1 Locked Programmable Programmable
1 LOW 0 Locked Locked Locked
1 LOW 1 Locked Programmable Locked
X HIGH 0 Locked Locked Locked
X HIGH 1 Locked Programmable Programmable

6829 PGM T05

The Program Protect (PP) pin and the nonvolatile
Program Protect Enable (PPEN) bit in the Status Reg­ister control the programmable hardware write protect
feature. Hardware program protection is enabled when
PP pin is LOW, and the PPEN bit is “1”. Hardware
program protection is disabled when either the PP pin is
HIGH or the PPEN bit is “0”. When the chip is hardware
program protected, nonvolatile programming of the Sta­tus Register in disabled, including the Block Lock bits
and the PPEN bit itself, as well as the Block Lock
sections in the memory array. Only the sections of the
memory array that are not Block Locked can be pro­grammed.

Note: Since the PPEN bit is program protected, it

cannot be changed back to a “0”, as long as
the PP pin is held LOW.

Clock and Data Timing

Data input on the SI line is latched on the rising edge of
SCK. Data is output on the SO line by the falling edge of
SCK.

Read Sequence

When reading from the SerialFlash memory array, CS is
first pulled LOW to select the device. The 8-bit READ
instruction is transmitted to the X25F128, followed by
the 16-bit address. After the read opcode and address
are sent, the data stored in the memory at the selected
address is shifted out on the SO line. The data stored in
memory at the next address can be read sequentially by
continuing to provide clock pulses. The address is
automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address is reached the address counter rolls over to
address $0000, allowing the read cycle to be continued
indefinitely. The read operation is

terminated by taking
CS HIGH. Refer to the Read SerialFlash Memory Array
Operation Sequence illustrated in Figure 1.

tion. After the read status register opcode is sent, the
contents of the status register are shifted out on the SO
line. The Read Status Register Sequence is illustrated
in Figure 2.

Programming Sequence

Prior to any attempt to program the X25F128, the
program enable latch must first be set by issuing the
PREN instruction (See Figure 3). CS is first taken LOW,
then the PREN instruction is clocked into the X25F128.
After all eight bits of the instruction are transmitted, CS
must then be taken HIGH. If the user continues the
programming operation without taking CS HIGH after
issuing the PREN instruction, the programming opera­tion will be ignored.

To program the SerialFlash memory array, the user
issues the PROGRAM instruction, followed by the ad­dress of the first location in the sector and then the data
to be programmed. The data is programmed in a 256­clock operation. CS must go LOW and remain LOW for
the duration of the operation. The 32 bytes must reside
in the same sector and cannot cross sector boundaries.
If the address counter reaches the end of the sector
and the clock continues, or if fewer than 32 bytes are
clocked in, the contents of the sector cannot be guaranteed.

For the program operation to be completed, CS can only
be brought HIGH after bit 0 of data byte 32 is clocked in.
If it is brought HIGH at any other time, the program
operation will not be completed. Refer to Figure 4 below
for a detailed illustration of the programming sequence
and time frames in which CS going HIGH is valid.

To program the status register, the PRSR instruction is
followed by the data to be programmed. Data bits 0, 1,
4, 5 and 6 must be “0”. This sequence is shown in Figure 5.

While the program cycle is in progress, following a
status register or memory write sequence, the status
register may be read to check the PIP bit. During this
time the PIP bit will be HIGH.

Hold Operation

The HOLD input should be HIGH (at VIH) under normal
operation. If a data transfer is to be interrupted HOLD
can be pulled LOW to suspend the transfer until it can
be resumed. The only restriction is that the SCK input
must be LOW when HOLD is first pulled LOW and SCK
must also be LOW when HOLD is released.

To read the status register, the CS line is first pulled
LOW to select the device followed by the 8-bit instruc-

The HOLD input may be tied HIGH either directly to V
or tied to VCC through a resistor.

4

CC

X25F128

Operational Notes

The device powers-up in the following state:

• The device is in the low power standby state.

• A HIGH to LOW transition on CS is required to
enter an active state and receive an instruction.

• SO pin is high impedance.

• The program enable latch is reset.

Data Protection

The following circuitry has been included to prevent
inadvertent programming:

• The program enable latch is reset upon power-up.

• A program enable instruction must be issued to set
the program enable latch.

• CS must come HIGH at the proper clock count in
order to start a program cycle.

Figure 1. Read SerialFlash Memory Array Operation Sequence

CS

012345678910 2021222324252627282930

SCK

INSTRUCTION 16 BIT ADDRESS

SI

151413 3210

SO

HIGH IMPEDANCE

Figure 2. Read Status Register Operation Sequence

CS

01234567891011121314

SCK

INSTRUCTION

SI

SO

HIGH IMPEDANCE

76543210

MSB

DATA OUT

76543210

MSB

6829 ILL F04

DATA OUT

6829 ILL F03

5

X25F128

Figure 3. Program Enable Latch Sequence

CS

01234567

SCK

SI

INSTRUCTION

SO

HIGH IMPEDANCE

6829 ILL F05.1

6

X25F128

Figure 4. Programming Sequence

CS

SCK

CS

SCK

012345678910

INSTRUCTION 16 BIT ADDRESS

SI

32 33 34 35 36 37 38 39

DATA BYTE 2

SI

76543210

20 21 22 23 24 25 26 27 28 29 30 31

151413 3210

40 41 42 43 44 45 46 47

DATA BYTE 3

76543210

DATA BYTE 1

76543210

DATA BYTE 32

6543210

6829 ILL F07

Figure 5. Program Status Register Operation Sequence

CS

0123456789

SCK

INSTRUCTION

SI

SO

HIGH IMPEDANCE

7

10 11 12 13 14 15

DATA BYTE

76543210

6829 ILL F08

X25F128

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias.................. –65°C to +135°C

Storage Temperature ....................... –65°C to +150°C

Voltage on any Pin with Respect to V

SS

.........

–1V to +7V

D.C. Output Current ............................................. 5mA

Lead Temperature

(Soldering, 10 Seconds) ............................. 300°C

*COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those listed in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

Temp Min. Max.

Commercial 0°C +70°C
Extended –20°C +85°C
Industrial –40°C +85°C

6829 PGM T06.1

Supply Voltage Limits

X25F128 1.8V to 3.6V
X25F128–5 4.5V to 5.5V

6829 PGM T07.1

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Limits

Symbol Parameter Min. Max. Units Test Conditions

I

CC

I

SB1

I

SB2

I

LI

I

LO

V
V
V
V
V
V

IL
IH
OL1
OH1
OL2
OH2

VCC Supply Current (Active) 5 mA SCK = VCC x 0.1/VCC x 0.9 @ 1MHz,

SO = OPEN, CS = V

(2)

VCC Supply Current (Standby) 1 µA CS = VCC, VIN = VSS or V

SS

VCC Supply Current (Standby) 10 µA CS = VCC, VIN = VSS or V
Input Leakage Current 10 µAVIN = VSS to V
Output Leakage Current 10 µAV

(1)

Input LOW Voltage –0.5 V

(1)

Input HIGH Voltage V

CC

x 0.7 V

x 0.3 V

CC

+ 0.5 V

CC

OUT

= VSS to V

CC

CC

Output LOW Voltage 0.4 V IOL = 1.5mA, VCC = 2.7V
Output HIGH Voltage V

– 0.3 V IOH = –0.4mA, VCC = 2.7V

CC

Output LOW Voltage 0.4 V IOL = 3mA, VCC = 5V
Output HIGH Voltage V

– 0.8 V IOH = –1.6mA, VCC = 5V

CC

CC, VCC
CC, VCC

6829 PGM T08.1

= 3.6V
= 5V

POWER-UP TIMING

Symbol Parameter Min. Max. Units

(3)

t

PUR

t

PUW

(3)

Power-up to Read Operation 1 ms
Power-up to Write Operation 5 ms

CAPACITANCE TA = 25°C, f = 1MHz, VCC = 5V.

Symbol Test Max. Units Conditions

(2)

C

OUT

(2)

C

IN

Notes: (1) VIL min. and VIH max. are for reference only and are not tested.

(2) This parameter is periodically sampled and not 100% tested.
(3) t

PUR

are periodically sampled and not 100% tested.

Output Capacitance (SO) 8 pF V
Input Capacitance (SCK, SI, CS, PP, HOLD)6 pF V

and t

are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters

PUW

8

OUT

IN

6829 PGM T09

= 0V

= 0V

6829 PGM T10

X25F128

EQUIVALENT A.C. LOAD CIRCUIT A.C. TEST CONDITIONS

Input Pulse Levels VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times 10ns

Input and Output Timing Level VCC x 0.5

1.64KΩ

OUTPUT

4.63KΩ

2.7V

OUTPUT

100pF

1.44KΩ

1.95KΩ

5V

100pF

6829 ILL F09.1

A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Data Input Timing

Symbol Parameter Min. Max. Units

f

SCK

t

CYC

t

LEAD

t

LAG

t

WH

t

WL

t

SU

t

H

(4)

t

RI

(4)

t

FI

t

HD

t

CD

t

CS

t

PC

(5)

Clock Frequency 0 1 MHz
Cycle Time 1000 ns

CS Lead Time 500 ns
CS Lag Time 500 ns

Clock HIGH Time 400 ns
Clock LOW Time 400 ns
Data Setup Time 100 ns
Data Hold Time 100 ns
Data In Rise Time 2 µs
Data In Fall Time 2 µs

HOLD Setup Time 200 ns
HOLD Hold Time 200 ns
CS Deselect Time 2 µs

Program Cycle Time 10 ms

6829 PGM T11

6829 PGM T12.1

Data Output Timing

Symbol Parameter Min. Max. Units

f

SCK

t

DIS

t

V

t

HO

(4)

t

RO

(4)

t

FO

(4)

t

LZ

(4)

t

HZ

Notes: (4) This parameter is periodically sampled and not 100% tested.

(5) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal

nonvolatile program cycle.

Clock Frequency 0 1 MHz
Output Disable Time 500 ns
Output Valid from Clock LOW 400 ns
Output Hold Time 0 ns
Output Rise Time 300 ns
Output Fall Time 300 ns

HOLD HIGH to Output in Low Z 100 ns
HOLD LOW to Output in High Z 100 ns

9

6829 PGM T13

X25F128

Serial Output Timing

CS

SCK

SO

SI

ADDR

LSB IN

Serial Input Timing

CS

t

CYC

t

V

t

HO

t

WH

t

WL

MSB OUT MSB–1 OUT LSB OUT

t

LEAD

t

LAG

t

DIS

6829 ILL F10

t

CS

t

LAG

SCK

SO

t

SU

SI

MSB IN

t

H

t

RI

t

FI

LSB IN

HIGH IMPEDANCE

6829 ILL F11

10

X25F128

Hold Timing

CS

SCK

SO

HOLD

t

HD

t

HZ

t

CD

t

CD

t

HD

t

LZ

SI

6829 ILL F12

11

X25F128

PACKAGING INFORMATION

8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P

0.430 (10.92)

0.360 (9.14)

0.260 (6.60)

0.240 (6.10)

PIN 1 INDEX

PIN 1

0.300

(7.62) REF.

0.060 (1.52)

0.020 (0.51)

HALF SHOULDER WIDTH ON

ALL END PINS OPTIONAL

SEATING

PLANE

0.150 (3.81)

0.125 (3.18)

0.015 (0.38)
MAX.

TYP. 0.010 (0.25)

0.110 (2.79)

0.090 (2.29)

0.325 (8.25)

0.300 (7.62)

0.065 (1.65)

0.045 (1.14)

0.020 (0.51)

0.016 (0.41)

NOTE:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH

0.145 (3.68)

0.128 (3.25)

0.025 (0.64)

0.015 (0.38)

0°

15°

12

3926 FHD F01

X25F128

PACKAGING INFORMATION

16-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S

PIN 1 INDEX

(4X) 7°

0.050 (1.27)

0.010 (0.25)

0.020 (0.50)

PIN 1

X 45°

0.014 (0.35)

0.020 (0.51)

0.386 (9.80)

0.394 (10.01)

0.150 (3.80)

0.158 (4.00)

0.004 (0.19)

0.010 (0.25)

0.228 (5.80)

0.244 (6.20)

0.053 (1.35)

0.069 (1.75)

0.050" Typical

0° – 8°

0.016 (0.410)

0.037 (0.937)

0.0075 (0.19)

0.012 (0.30)

0.250"

0.030" Typical

FOOTPRINT

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

13

0.050"
Typical

16 Places

3926 FHD F26

X25F128

ORDERING INFORMATION

Device

Part Mark Convention

X25F128

X25F128

P T –X

VCC Range

Blank = 1.8V to 3.6V
5 = 4.5V to 5.5V

Temperature Range

Blank = Commercial = 0°C to +70°C
E = Extended = –20°C to +85°C
I = Industrial = –40°C to +85°C

Package

P = 8-Lead Plastic DIP
S = 16-Lead SOIC

P = 8-Lead Plastic DIP
S = 16-Lead SOIC

X

Blank = 1.8V to 3.6V, 0°C to +70°C
5 = 4.5V to 5.5V, 0°C to +70°C
I5 = 4.5V to 5.5V, –40°C to +85°C

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are
implied.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and
additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and backup features to prevent such an occurrence.

Xicor's products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.

14