Datasheet X25F087S-5, X25F087S, X25F087PI-5, X25F087PI, X25F087P-5 Datasheet (XICOR)



8K

X25F087

SPI SerialFlash with Block Lock

FEATURES

• 1MHz Clock Rate

• SPI Modes (0,0 & 1,1)

• 1024 x 8 Bits
—16 Byte Small Sector Program Mode

• Low Power CMOS
—<1 µ A Standby Current
—<3mA Active Current during Program
—<400 µ A Active Current during Read

• 1.8V to 3.6V or 5V “Univolt” Read and Program
Power Supply Versions

• Block Lock Protection
—Block Lock Protect 0, any 1/4, 1st 1/2, First or

Last Sector of SerialFlash Array

• Built-in Inadvertent Program Protection
—Power-Up/Power-Down Protection Circuitry
—Program Enable Latch
—Program Protect Pin

• Self-Timed Program Cycle
—5ms Program Cycle Time (Typical)

• High Reliability
—Endurance: 100,000 Cycles/Byte
—Data Retention: 100 Years
—ESD: 2000V on all pins

• 8-Lead SOIC Package

• 8-Lead TSSOP Package

• 8-Pin Mini-DIP Package

1024 x 8 Bit

TM

Protection

DESCRIPTION

The X25F087 is a CMOS 8k-bit SerialFlash, internally
organized as 1024 x 8. The X25F087 features a Serial
Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus. The bus
signals are a clock input (SCK) plus separate data in (SI)
and data out (SO) lines. Access to the device is
controlled through a chip select (CS
number of devices to share the same bus .

There are eight options for programmable, nonvolatile,
Block Lock Protection available to the end user. These
options are implemented via special instructions
programmed to the part. The X25F087 also features a

pin that can be used for hardwire protection of the

PP
part, disabling all programming attempts, as well as a
Program Enable Latch that must be set bef ore a program
operation can be initiated.

The X25F087 utilizes Xicor’s proprietary Direct Write
cell, providing a minimum endurance of 100,000 cycles
per sector and a minimum data retention of 100 years.

) input, allowing any

TM

FUNCTIONAL DIAGRAM

SI

SO

SCK

CS

PP

Xicor, Inc. 1994, 1995, 1996 Patents Pending

7007-0.7 5/8/97 T1/C0/D0 SH

COMMAND

DECODE

AND

CONTROL

LOGIC

PROGRAM CONTROL LOGIC

X

DECODE

LOGIC

DATA REGISTER

Y DECODE LOGIC

816

32

SERIALFLASH

ARRAY

(1024 x 8)

HIGH VOLTAGE

CONTROL

1

7007 FRM 01

Characteristics subject to change without notice

X25F087

PIN DESCRIPTIONS
Serial Output (SO)

SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.

Serial Input (SI)

SI is a serial data input pin. All opcodes, byte addresses,
and data to be programmed to the memory are input on
this pin. Data is latched by the r ising edge of the serial
clock.

Serial Clock (SCK)

The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the clock
input, while data on the SO pin change after the falling
edge of the clock input.

Chip Select (CS

)

When CS is HIGH, the X25F087 is deselected and the
SO output pin is at high impedance and unless a nonvol­atile write cycle is underway, the X25F087 will be in the
standby power mode. CS LOW enables the X25F087,
placing it in the active power mode. It should be noted
that after power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.

Program Protect (PP)

When PP is LOW, nonvolatile writes to the X25F087 are
disabled, but the part otherwise functions normally . When
PP is held HIGH, all functions, including nonvolatile
writes, operate normally. PP going LOW while CS is still
LOW will interrupt a programming cycle to the X25F087.
If the nonvolatile write cycle has already been initiated,
PP going low will have no aff ect on this cycle.

PIN CONFIGURATION

8 PIN SOIC/DIP

CS

1

SO

*0.197"

V

V

0.122"

*SOIC Measurement

PP
SS

NC
CC

CS
SO

2
3
4

8 PINTSSOP

1
2
3
4

X25F087

*0.244"

X25F087

0.252"

V

8

CC

7

NC
SCK

6
5

SI

SCK

8

SI

7

V

6

SS

PP

5

Not to scale

7007 FRM 02

PIN NAMES

Symbol Description

CS

Chip Select Input

SO Serial Output

SI Serial Input

SCK Serial Clock Input

PP Program Protect Input

V

SS

V

CC

Ground
Supply Voltage

NC No Connect

7007 FRM T01

PRINCIPLES OF OPERATION

The X25F087 is a 1024 x 8 SerialFlash designed to inter­face directly with the synchronous Serial Peripheral Inter­face (SPI) of many popular microcontroller f amilies.

The X25F087 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on
the rising edge of SCK. CS

must be LOW and the PP
input must be HIGH during the entire operation. Table 1
contains a list of the instructions and their opcodes. All
instructions, addresses and data are transferred MSB first.

Data input is sampled on the first rising edge of SCK
after CS goes LOW. SCK is static, allowing the user to
stop the clock and then start it again to resume opera­tions where left off.

Program Enable Latch

The X25F087 contains a “Program Enable” latch. This
latch must be SET before a program operation is initi­ated. The PREN instruction will set the latch and the
PRDI instruction will reset the latch (Figure 4). This latch
is automatically reset upon a power-up condition and
after the completion of a sector program cycle.

Block Lock Protection

There are eight Block Lock Protection options. The pre­defined blocks and associated address ranges are pro­tected by programming the appropriate two byte
Program Status instruction to the device (Table 1 and
Figure 6). Once a Block Lock protect instruction has
been completed, that Block Lock Protection setup is held
in a nonvolatile Status Register (Figure 1) until the next
Program Status instruction is issued. The sections of the
memory array that are Block Lock protected can be read
but not programmed until Block Lock Protection is
removed or changed.

2

X25F087

Figure 1. Status Register/Block Lock Protection Byte

7 6 5 4 3 2 1 0
0 0 0 0 0 BL2 BL1 BL0

Note: Bits [7:3] specified to be “0’s”

7007 FRM T02

Read Sequence

When reading from the SerialFlash memory array, CS

is
first pulled LOW to select the device. The 8-bit READ
instruction is transmitted to the X25F087, followed b y the
16-bit address, of which the last 10 bits are used (bits
[15:10] specified to be "0’s"). After the READ opcode and
address are sent, the data stored in the memory at the
selected address is shifted out on the SO line. The data
stored in memory at the next address can be read
sequentially by continuing to provide clock pulses. The
address is automatically incremented to the next higher
address after each byte of data is shifted out. When the
highest address is reached (03FFh), the address counter
rolls over to address 0000h, allowing the read cycle to be
continued indefinitely. The read operation is ter minated
by taking CS

HIGH (Figure 2).

Sector Program Sequence

Prior to any attempt to program data into the X25F087,
the “Program Enable” latch must first be set by issuing
the PREN instruction (Table 1 and Figure 4). CS is first
taken LOW. Then the PREN instruction is clocked into
the X25F087. After all eight bits of the instruction are
transmitted, CS must then be taken HIGH. If the user
continues the program operation without taking CS HIGH
after issuing the PREN instruction, the program opera­tion will be ignored.

To program data to the SerialFlash memory array, the
user then issues the PROGRAM instruction, followed by
the 16 bit address of the first location in the sector and
then the 16 bytes of data to be programmed. Only the last
9 bits of the address are used and bits [15:9] are speci­fied to be "0’s". The entire write operation takes 152
clocks. CS must go LOW and remain LOW for the dura­tion of the operation. The host must program 16 bytes in
each write with the restriction that these bytes reside on
one sector. If the address counter reaches the end of the
sector and the clock continues, or if fewer than 16 bytes
are clocked in, the contents of the sector cannot be guar­anteed.

For a sector program operation to be completed, CS

can
only be brought HIGH after bit 0 of the last data byte to
be programmed is clocked in. If it is brought HIGH at any
other time, the program operation will not be completed.
(Figure 5)

Read Status Operation

If there is not a nonvolatile write in progress, the Read
Status instruction returns the Block Lock Protection byte
from the Status Register which contains the Block Lock
Protection bits BL2-BL0 (Figure 1). The Block Lock Pro­tection bits define the Block Lock Protection condition
(Figure 1 and Table1). The other bits are reserved and
will return "0’s" when read (Figure 3).

If a nonvolatile write is in progress, the Read Status
instruction returns the status of the internal wr ite opera­tion on SO. When the nonvolatile write cycle is com­pleted, the status register data is again read out.

During a nonvolatile write in progress, the SO pin will be
set HIGH. At the end of the nonvolatile write cycle, SO is
set to output the current bit from the status register.
Clocking SCK is valid during a nonvolatile write in
progress, but is not necessary. If the SCK line is clocked,
the pointer to the status register is also clocked, even
though the SO pin shows the status of the nonvolatile
write operation (Figure 3). When the pointer reaches the
end of the eight bit status register, it “rolls o v er” to the first
bit of the register.

Program Status Operation

Prior to any attempt to perform a Program Status Opera­tion, the PREN instruction must first be issued. This
instruction sets the “Program Enable” latch and allows
the part to respond to a Program Status sequence (Fig­ure 6). The Program Status instruction follows and con­sists of one command byte followed by one Block Lock
Protection byte (Figure 1). This byte contains the Block
Lock Protection bits BL2-BL0. The rest of the bits [7:3]
are unused and must be programmed as “0’s”. Bringing

HIGH after the two byte Program Status instruction

CS
initiates a nonvolatile write to the Status Register. Pro­gramming more than one byte to the Status Register will
overwrite the previously programmed Block Lock Protec­tion byte (Table 1).

3

X25F087

Data Protection

The following circuitry has been included to prev ent inad­vertant programming of data:

• The “Program Enable” latch is reset upon po w er-up .

• A PREN instruction must be issued to set the “Program
Enable” latch.

• CS must come HIGH at the proper clock count in order

Operational Notes

The X25F087 powers up in the follo wing state:

• The device is in the low power, standby state.

• A HIGH to LOW transition on CS
an active state and receive an instruction.

• SO pin is at high impedance.

• The “Program Enable” latch is reset.

to start a program cycle.

Table 1. Instruction Set and Block Lock Protection Byte Definition

Instruction

Format* Instruction Name and Operation

0000 0110 PREN: Set the Program Enable Latch (Program Enable Operation)
0000 0100 PRDI: Reset the Program Enable Latch (Program Disable Operation)
0000 0001

PROGRAM STATUS Instruction - followed by:
Block Lock Protection Byte: (Figure 1)

0000 0000 --->NO PROTECT: ---------------------------------->None of the Array
0000 0001 --->PROTECT Q1: --- 0000h - 00FFh ---------->Lower Quadrant (Q1)
0000 0010 --->PROTECT Q2: --- 0100h - 01FFh----------->Q2
0000 0011 --->PROTECT Q3: --- 0200h - 02FFh----------->Q3
0000 0100 --->PROTECT Q4: --- 0300h - 03FFh----------->Upper Quadrant (Q4)
0000 0101 --->PROTECT H1: --- 0000h - 01FFh----------->Lower Half of the Array (H1)
0000 0110 --->PROTECT S0: --- 0000h - 000Fh----------->Lower Sector (S0)
0000 0111 --->PROTECT Sn: --- 03F0h - 03FFh----------->Upper Sector (Sn)

is required to enter

0000 0101 READ STATUS: Reads Block Lock Protection & nonvolatile write in progress status on SO Pin
0000 0010 PROGRAM: Program operation followed by address and data
0000 0011 READ: Read operation followed by address

*Instructions are shown with MSB in leftmost position. Instructions are transferred MSB fi rst.

Figure 2. Read Operation Sequence

CS

SCK

SO

0 1 2 3 4 5 6 7 8 9

READ INSTRUCTION

(1 BYTE)

SI

HIGH IMPEDANCE

BYTE ADDRESS (2 BYTE) DATA OUT

15 14 3 2 1 0

20 21 22 23 24 25 26 27 28 29 30

7 6 5 4 3 2 1 0

7007 FRM T03

7007 FRM 03

4

X25F087

Figure 3. Read Status Operation Sequence

CS

0 1 2 3 4 5 6 7

SCK

READ STATUS

SI

SO

INSTRUCTION

NONVOLATILE WRITE IN PROGRESS

...
...

B

B
L
2

B
L
1

...

L

0

SO HIGH DURING

NONVOLATILE
WRITE CYCLE

Figure 4. Program Enable/Program Disable Sequence

CS

0 1 2 3 4 5 6 7

SCK

INSTRUCTION

(1 BYTE)

SI

SO

HIGH IMPEDANCE

SO = STATUS REG BIT

WHEN NO NONVOLATILE

WRITE CYCLE

7007 FRM 05

7007 FRM 04

5

X25F087

Figure 5. Sector Program Operation Sequence

CS

0 1 2 3 4 5 6 7 8 9 10

SCK

PROGRAM

INSTRUCTION

15 14 13 3 2 1 0

40 41 42 43 44 45 46 47

7 6 5 4 3 2 1 0

CS

SCK

SI

32 33 34 35 36 37 38 39

DATA BYTE 2

7 6 5 4 3 2 1 0

SI

Figure 6. Program Status Operation Sequence

CS

BYTE ADDRESS

(2 BYTE) DATA BYTE 1

DATA BYTE 3

20 21 22 23 24 25 26 27 28 29 30 31

7 6 5 4 3 2 1 0

146

145

6 5 4 3 2 1 0

147

148

DATA BYTE 16

149

150

151

7007 FRM 07.1

0 1 2 3 4 5 6 7 8 9

SCK

PROGRAM STATUS

INSTRUCTION

SI

SO

HIGH IMPEDANCE

ABSOLUTE MAXIMUM RATINGS*

Temperature under Bias...................–65 ° C to +135 ° C

Storage Temperature........................–65 ° C to +150 ° C

Voltage on any Pin with

Respect to V

...................................–1V to +7V

SS

D.C. Output Current..............................................5mA

Lead Temperature

(Soldering, 10 seconds)..............................300 ° C

10 11 12 13 14 15

BLOCK LOCK

PROTECTION BYTE

B

B
L

00000

2

B

L

L

1

0

7007 FRM 08

*COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maxim um rating con­ditions for extended periods ma y affect de vice reliability.

6

X25F087

RECOMMENDED OPERATING CONDITIONS

µ

µ

µ

Temperature Min. Max.

Commercial 0°C +70°C

Industrial –40°C +85°C

7007 FRM T04

Supply Voltage Limits

X25F087 1.8V to 3.6V

X25F087-5 4.5V to 5.5V

7007 FRM T05

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)

Limits

Symbol Parameter Min. Max. Units Test Conditions

I

CC1

I

CC2

I

SB

I

LI

I

LO

V
V

V
V
V
V
V
V

(1)

IL

(1)

IH
OL1
OH1
OL2
OH2
OL3
OH3

V

Read Current (Active) 1 mA SCK = V

CC

V

Write Current (Active) 3 mA SCK = V

CC

V

Supply Current (Standby) 1

CC

Input Leakage Current 10
Output Leakage Current 10
Input LOW Voltage –0.5 V
Input HIGH Voltage V

x 0.7 V

CC

CC
CC

x 0.3 V
+ 0.5 V

A
A
A

Output LOW Voltage 0.4 V
Output HIGH Voltage V

– 0.8 V

CC

Output LOW Voltage 0.4 V
Output HIGH Voltage V

– 0.4 V

CC

Output LOW Voltage 0.4 V
Output HIGH Voltage VCC – 0.2 V

x 0.1/V

CC

SO = Open, CS

x 0.1/V

CC

SO = Open, CS
CS

= V

- 0.1, V

CC

V

= V

to V

SS

= V

SS

= 5.5V, I
= 5.5V, I
= 3.6V, I
= 3.6V, I
= 1.8V, I
= 1.8V, I

to V

OL
OH
OL
OH
OL
OH

V

V
V
V
V
V
V

IN
OUT

CC
CC
CC
CC
CC
CC

x 0.9 @ 1MHz,

CC

= V

SS

x 0.9 @ 1MHz,

CC

= V

SS

= V

IN

CC

CC

= 2.1mA

= –1.0mA

= 1.0mA

= –0.4mA

= 0.5mA

= –0.25mA

SS

or V

CC

7007 FRM T06

POWER-UP TIMING

Symbol Parameter Min. Max. Units

(3)

t

PUR

t

PUW

CAPACITANCE T

Power-up to Read Operation 1 ms

(3)

Power-up to Write Operation 5 ms

= +25 ° C, f = 1MHz, V

A

CC

=5V.

Symbol Parameter Max. Units Conditions

(2)

C

OUT

(2)

C

IN

Notes: (1) V

(2) This parameter is periodically sampled and not 100% tested.
(3) t

Output Capacitance (SO) 8 pF V
Input Capacitance (SCK, SI, CS, PP) 6 pF VIN = 0V

Min. and V

IL

and t

PUR

are periodically sampled and not 100% tested.

Max. are f or ref erence only and are not 100% tested.

IH

are the delays required from the time V

PUW

is stable until the specified operation can be initiated. These parameters

CC

7

OUT

7007 FRM T07

= 0V

7007 FRM T08

X25F087

EQUIVALENT A.C. LOAD CIRCUIT

5V

3.3V

A.C. TEST CONDITIONS

Input Pulse Levels VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times 10ns

2061Ω

OUTPUT

3025Ω 30pF

2696Ω

OUTPUT

5288Ω 30pF

Input and Output Timing Level V

7007 FRM 09

A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Data Input Timing

Symbol Parameter Min. Max. Units

f

SCK

t

CYC

t

LEAD

t

LAG

t

WH

t

WL

t

SU

t

H

t

RI

t

FI

t

CS

t

WC

(4)

(4)

(5)

Clock Frequency 0 1 MHz
Cycle Time 1000 ns
CS Lead Time 500 ns
CS Lag Time 500 ns
Clock HIGH Time 400 ns
Clock LOW Time 400 ns
Data Setup Time 100 ns
Data Hold Time 100 ns
Data In Rise Time 2 µs

Data In Fall Time 2 µs
CS Deselect Time 2.0 µs

Write Cycle Time 10 ms

Data Output Timing

CC

X 0.5

7007 FRM T09

7007 FRM T10

Symbol Parameter Min. Max. Units

f

SCK

t

DIS

t

V

t

HO

(4)

t

RO

(4)

t

FO

Notes: (4) This parameter is periodically sampled and not 100% tested.

(5) tWC is the time from the rising edge of CS after a valid program sequence has been sent to the end of the self-timed internal nonvol-

atile write cycle.

Clock Frequency 0 1 MHz
Output Disable Time 500 ns
Output Valid from Clock LOW 400 ns
Output Hold Time 0 ns
Output Rise Time 300 ns

Output Fall Time 300 ns

8

7007 FRM T11

X25F087

Figure 7. Serial Output Timing

CS

SCK

SO

SI

ADDR

LSB IN

MSB OUT MSB–1 OUT LSB OUT

Figure 8. Serial Input Timing

CS

t

LEAD

SCK

t

SU

t

CYC

t

V

t

H

t

HO

t

WH

t

WL

t

CS

t

t

RI

FI

t

t

LAG

LAG

t

DIS

7007 FRM 10

SI

MSB IN

HIGH IMPEDANCE

SO

SYMBOL TABLE

WAVEFORM INPUTS OUTPUTS

Must be
steady

May change
from Low to
High

May change
from High to
Low

Don’t Care:
Changes
Allowed

N/A Center Line

LSB IN

7007 FRM 11

Will be
steady

Will change
from Low to
High

Will change
from High to
Low

Changing:
State Not
Known

is High
Impedance

9

X25F087

PACKAGING INFORMATION

8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S

PIN 1 INDEX

(4X) 7°

0.050 (1.27)

0.010 (0.25)

0.020 (0.50)

PIN 1

X 45°

0.014 (0.35)

0.019 (0.49)

0.188 (4.78)

0.197 (5.00)

0.150 (3.80)

0.158 (4.00)

0.004 (0.19)

0.010 (0.25)

0.228 (5.80)

0.244 (6.20)

0.053 (1.35)

0.069 (1.75)

0.050" TYPICAL

0° – 8°

0.0075 (0.19)

0.010 (0.25)

0.016 (0.410)

0.037 (0.937)

0.250"

NOTE:ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

10

0.050"
TYPICAL

0.030"

TYPICAL

8 PLACESFOOTPRINT

X25F087

PACKAGING INFORMATION

8-LEAD PLASTIC, TSSOP, PACKAGE TYPE V

.025 (.65) BSC

0° – 8°

.0075 (.19)

.0118 (.30)

.114 (2.9)
.122 (3.1)

.019 (.50)
.029 (.75)

DetailA (20X)

.169 (4.3)
.177 (4.5)

.047 (1.20)

.002 (.05)
.006 (.15)

.010 (.25)

Seating Plane

.252 (6.4) BSC

Gage Plane

.031 (.80)

.041 (1.05)

See Detail “A”

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

11

X25F087

PACKAGING INFORMATION

8-LEAD PLASTIC DUAL IN-LINE PACKAGETYPE P

0.430 (10.92)

0.360 (9.14)

0.260 (6.60)

0.240 (6.10)

PIN 1 INDEX

PIN 1

0.300

(7.62) REF.

0.060 (1.52)

0.020 (0.51)

HALF SHOULDER WIDTH ON

ALL END PINS OPTIONAL

SEATING

PLANE

0.150 (3.81)

0.125 (3.18)

0.110 (2.79)

0.090 (2.29)

0.015 (0.38)
MAX.

TYP. 0.010 (0.25)

0.325 (8.25)

0.300 (7.62)

0.145 (3.68)

0.128 (3.25)

0.025 (0.64)

0.015 (0.38)

0.065 (1.65)

0.045 (1.14)

0.020 (0.51)

0.016 (0.41)

NOTE:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH

0°
15°

12

X25F087

ORDERING INFORMATION

Device

Part Mark Convention

8-Lead TSSOP

EYWW

5F87XX

X25F087 P T

–X

VCC Range

Blank = 1.8V to 3.6V
5 = 4.5V to 5.5V

Temperature Range

Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C

Package

S = 8-Lead SOIC
V = 8-Lead TSSOP
P = 8-Lead Plastic DIP

8-Lead SOIC/PDIP

X25F087 X

XX

Blank = 8-Lead SOIC
P = 8-Lead Plastic DIP

Blank = 1.8 to 3.6V, 0 to +70°C
I = 1.8 to 3.6V, -40 to +85°C
AE = 2.5 to 5.5V, 0 to +70°C
AF = 2.5 to 5.5V, -40 to +85°C
5 = 4.5 to 5.5V, 0 to +70°C
I5 = 4.5 to 5.5V, -40 to +85°C

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc.
makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the
described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for an y purpose. Xicor, Inc. reserves the
right to discontinue production and change specifications and prices at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967;
4,883, 976. Foreign patents and additional patents pending.

LIFE RELA TED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prev ent such an occurence.

Xicor's products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain
life, and whose failure to perfor m, when properly used in accordance with instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its saf ety or effectiveness.

Blank = 1.8 to 3.6V, 0 to +70°C
I = 1.8 to 3.6V, -40 to +85°C
AE = 2.5 to 5.5V, 0 to +70°C
AF = 2.5 to 5.5V, -40 to +85°C
5 = 4.5 to 5.5V, 0 to +70°C
I5 = 4.5 to 5.5V, -40 to +85°C

13