Datasheet X25401SM, X25401SI, X25401S, X25401PM, X25401PI Datasheet (XICOR)

APPLICATION NOTE

AVAILABLE

X25401

AN56

256 Bit X25401 16 x 16 Bit

SPI Serial AUTOSTORE™ NOVRAM

FEATURES

• 1MHz Clock Rate

• AUTOSTORE™

—Automatically Performs a Store Operation
Upon Loss of V

NOVRAM

CC

• Single 5 Volt Supply

• Ideal for use with Single Chip Microcomputers

—Minimum I/O Interface
—SPI Mode (0,0 & 1,1) Serial Port Compatible
—Easily Interfaced to Microcontroller Ports

• Software and Hardware Control of Nonvolatile

Functions

• Auto Recall on Power-Up

• TTL and CMOS Compatible

• Low Power Dissipation

—Active Current: 10mA
—Standby Current: 50µA

• 8-Lead PDIP and 8-Lead SOIC Packages

• High Reliability

—Store Cycles: 1,000,000
—Data Retention: 100 Years

DESCRIPTION

The Xicor X25401 is a serial 256 bit NOVRAM featuring
a static RAM configured 16 x 16, overlaid bit-by-bit with
a nonvolatile E2PROM array. The X25401 features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in (SI)
and data out (SO) lines. Access to the device is con­trolled through a chip select (CS) input, allowing any
number of devices to share the same bus.

The Xicor NOVRAM design allows data to be transferred
between the two memory arrays by means of software
commands or external hardware inputs. A store opera­tion (RAM data to E2PROM) is completed in 5ms or less
and a recall operation (E2PROM data to RAM) is com­pleted in 2µs or less.

The X25401 also includes the AUTOSTORE feature, a
user selectable feature that automatically performs a
store operation when VCC falls below a preset threshold.

Xicor NOVRAMs are designed for unlimited write opera­tions to RAM, either from the host or recalls from E2PROM
and a minimum 1,000,000 store operations. Inherent data
retention is specified to be greater than 100 years.

FUNCTIONAL DIAGRAM

NONVOLATILE

E2PROM

STORE

STATIC

ROW

DECODE

CS (1)

SI (3)

SCK (2)

AUTOSTORE™ NOVRAM is a trademark of Xicor, Inc.
COPS is a trademark of National Semiconductor Corp.

© Xicor, Inc. 1992, 1995, 1996 Patents Pending Characteristics subject to change without notice
2051-1.5 8/1/97 T0/C0/D2 SH

INSTRUCTION

REGISTER

INSTRUCTION

DECODE

4-BIT

COUNTER

RAM

256-BIT

COLUMN
DECODE

1

RECALL

CONTROL

LOGIC

RECALL (6)
AS (7)

SO (4)

2051 FHD F01

X25401

Chip Select (CS)

The Chip Select input must be LOW to enable all read/
write operations. CS must remain LOW following a
Read or Write command until the data transfer is com­plete. CS HIGH places the X25401 in the low power
standby mode and resets the instruction register. There­fore, CS must be brought HIGH after the completion of
an operation in order to reset the instruction register in
preparation for the next command.

PIN CONFIGURATIONPIN DESCRIPTIONS

DIP/SOIC

CS

SCK

SO

1
2
3
4

X25401

SI

8

V

CC

7

AS

6

RECALL

5

V

SS

Serial Clock (SCK)

The Serial Clock input is used to clock all data into and
out of the device.

Serial Data In (SI)

SI is the serial data input.

Serial Data Out (SO)

SO is the serial data output. It is in the high impedance
state except during data output cycles in response to a
READ instruction.

AUTOSTORE Output (AS)
AS is an open drain output which, when asserted indi-

cates VCC has fallen below the AUTOSTORE thresh­old (V

). AS may be wire-ORed with multiple open

ASTH

drain outputs and used as an interrupt input to a micro­controller or as an input to a low power reset circuit.

RECALL
RECALL LOW will initiate an internal transfer of data

from E2PROM to the RAM array.

2051 FHD F02

PIN NAMES

Symbol Description

CS Chip Enable
SCK Serial Clock
SI Serial Data In
SO Serial Data Out

RECALL Recall Input
AS AUTOSTORE Output

V

CC

V

SS

+5V
Ground

2051 PGM T01

2

X25401

DEVICE OPERATION

The X25401 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on
the rising edge of SCK. CS must be LOW during the
entire data transfer operation.

Table 1 contains a list of the instructions and their
operation codes. The most significant bit (MSB) of all
instructions is a logic one (HIGH), bits 6 through 3 are
either RAM address bits (A) or don’t cares (X) and bits
2 through 0 are the operation codes. The X25401
requires the instruction to be shifted in with the MSB
first.

After CS is LOW, the X25401 will not begin to interpret
the data stream until a logic “1” has been shifted in on
SI. Therefore, CS may be brought LOW with SCK
running and SI LOW. SI must then go HIGH to indicate
the start condition of an instruction before the X25401
will begin any action.

In addition, the SCK clock is totally static. The user can
completely stop the clock and data shifting will be
stopped. Restarting the clock will resume shifting of
data.

reset upon power-up and must be intentionally set by
the user to enable any write or store operations. Al­though a recall operation is performed upon power-up,
the previous recall latch is not set by this operation.

WRDS and WREN

Internally the X25401 contains a “write enable” latch.
This latch must be set for either writes to the RAM or
store operations to the E2PROM. The WREN instruction
sets the latch and the WRDS instruction resets the latch,
disabling both RAM writes and E2PROM stores, effec­tively protecting the nonvolatile data from corruption. The
write enable latch is automatically reset on power-up.

STO

The software STO instruction will initiate a transfer of
data from RAM to E2PROM. In order to safeguard
against unwanted store operations, the following con­ditions must be true:

• STO instruction issued.

• The internal “write enable” latch must be set
(WREN instruction issued).

• The “previous recall” latch must be set (either a
software or hardware recall operation).

RCL and RECALL

Either a software RCL instruction or a LOW on the
RECALL input will initiate a transfer of E2PROM data
into RAM. This software or hardware recall operation
sets an internal “previous recall” latch. This latch is

Once the store cycle is initiated, all other device func­tions are inhibited. Upon completion of the store cycle,
the write enable latch is reset. Refer to Figure 4 for a
state diagram description of enabling/disabling condi­tions for store operations.

TABLE 1. INSTRUCTION SET

Instruction Format, I2 I1 I

0

Operation

WRDS (Figure 3) 1XXXX000 Reset Write Enable Latch (Disables Writes and Stores)
STO (Figure 3) 1XXXX001 Store RAM Data in E2PROM
ENAS 1XXXX010 Enable AUTOSTORE Feature
WRITE (Figure 2) 1AAAA011 Write Data into RAM Address AAAA
WREN (Figure 3) 1XXXX100 Set Write Enable Latch (Enables Writes and Stores)
RCL (Figure 3) 1XXXX101 Recall E2PROM Data into RAM
READ (Figure 1) 1AAAA11X Read Data from RAM Address AAAA

X = Don’t Care
A = Address

2051 PGM T11

3

X25401

WRITE

The WRITE instruction contains the 4-bit address of
the word to be written. The write instruction is immedi­ately followed by the 16-bit word to be written. CS must
remain LOW during the entire operation. CS must go
HIGH before the next rising edge of SCK. If CS is
brought HIGH prematurely (after the instruction but
before 16 bits of data are transferred), the instruction
register will be reset and the data that was shifted-in
will be written to RAM.

If CS is kept LOW for more than 24 SCK clock cycles
(8-bit instruction plus 16-bit data), the data already
shifted-in will be overwritten.

READ

The READ instruction contains the 4-bit address of the
word to be accessed. Unlike the other six instructions,
I0 of the instruction word is a “don’t care”. This provides
two advantages. In a design that ties both SI and SO
together, the absence of an eighth bit in the instruction
allows the host time to convert an I/O line from an
output to an input. Secondly, it allows for valid data
output during the ninth SCK clock cycle.

All data bits are clocked by the falling edge of SCK
(refer to Read Cycle Diagram).

LOW POWER MODE

When CS is HIGH, non-critical internal devices are
powered-down, placing the device in the standby power
mode, thereby minimizing power consumption.

AUTOSTORE Feature

The AUTOSTORE instruction (ENAS) sets the
“AUTOSTORE enable” latch, allowing the X25401 to
automatically perform a store operation when VCC falls
below the AUTOSTORE threshold (V

ASTH

).

WRITE PROTECTION

The X25401 provides two software write protection
mechanisms to prevent inadvertent stores of unknown
data.

Power-Up Condition

Upon power-up the “write enable” and “AUTOSTORE
enable” latches are in the reset state, disabling any
store operation.

Unknown Data Store

The “previous recall” latch must be set after power-up.
It may be set only by performing a software or hard­ware recall operation, which assures that data in all
RAM locations is valid.

SYSTEM CONSIDERATIONS
Power-Up Recall

The X25401 performs a power-up recall that transfers
the E2PROM contents to the RAM array. Although the
data may be read from the RAM array, this recall does
not set the “previous recall” latch. During this power-up
recall operation, all commands are ignored. Therefore,
the host should delay any operations with the X25401
a minimum of t

after VCC is stable.

PUR

4

X25401

Figure 1. RAM Read

CS

SCK

1

2345678

9 101112222324

SI

SO

1A 1AAA 1X*

*Bit 8 of Read Instructions is Don’t Care

Figure 2. RAM Write

CS

SK

DI

1

1A 1AAA 1

HIGH Z

2345678

0

D

0

D

D

2

D

D

3

2

D12D

1

9 101121222324

D

D

0

1

D14D

D

13

13D14D15

D

15

2051 FHD F09.1

2051 FHD F10.1

0

Figure 3. Non-Data Operations

CS

SCK

SI

1

2345678

1X I

XXX I

2

5

1

I

0

2051 FHD F11.1

X25401

Figure 4. X25401 State Diagram

POWER

ON

RAM READ

OR WRITE

WREN

COMMAND

POWER

OFF

AUTOSTORE
POWER DOWN

RAM

READ & WRITE

ENABLED

STORE ENABLED

AUTOSTORE

ENABLED

STO OR

WRDS CMD

ENAS COMMAND

STO OR

WRDS CMD

RAM

READ

ENABLED

RAM

READ

ENABLED

RAM

READ & WRITE

ENABLED

STORE

ENABLED

POWER-UP
RECALL

RAM READ

RCL COMMAND
OR RECALL

RAM READ

WREN
COMMAND

RAM READ
OR WRITE

2051 FHD F12.1

6

X25401

ABSOLUTE MAXIMUM RATINGS*

Temperature under Bias .................. –65°C to +135°C

Storage Temperature ....................... –65°C to +150°C

Voltage on any Pin with

Respect to V

.......................................

SS

–1V to +7V

D.C. Output Current ............................................. 5mA

Lead Temperature

(Soldering, 10 seconds).............................. 300°C

*COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

Temperature Min. Max.

Commercial 0°C +70°C
Industrial –40°C +85°C

Supply Voltage Limits

X25401 5V ±10%

2051 PGM T03.2

Military –55°C +125°C

2051 PGM T02.1

D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)

Limits

Symbol Parameter Min. Max. Units Test Conditions

l

CC1

I

CC2

VCC Supply Current 10 mA SCK = 0.4V/2.4V Levels @ 1MHz,
(TTL Inputs) SO = Open, All Other Inputs = V

VCC Supply Current 2 mA All Inputs = VIH, CS = V

IL

IH

(During AUTOSTORE) SO = Open, VCC = 4.3V

I

SB1

I

SB2

VCC Standby Current 1 mA SO = Open, CS = VIL,
(TTL Inputs) All Other Inputs = V

VCC Standby Current 50 µA SO = Open, CS = V

IH

SS

(CMOS Inputs) All Other Inputs = VCC – 0.3V

I

LI

I

LO

V

lL

V

IH

V

OL

V

OH

V

OL(AS)

(1)

(1)

Input Load Current 10 µAVIN = VSS to V
Output Leakage Current 10 µAV

= VSS to V

OUT

Input LOW Voltage –1 0.8 V
Input HIGH Voltage 2 VCC + 1 V
Output LOW Voltage 0.4 V IOL = 4.2mA
Output HIGH Voltage 2.4 V IOH = –2mA
Output LOW Voltage (AS) 0.4 V I

OL (AS)

= 1mA

CC

CC

2051 PGM T04.3

ENDURANCE AND DATA RETENTION

Parameter Min. Units

Endurance 100,000 Data Changes Per Bit
Store Cycles 1,000,000 Store Cycles
Data Retention 100 Years

CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V

Symbol Parameter Max. Units Test Conditions

(2)

C

OUT

(2)

C

IN

Notes: (1) VIL min. and VIH max. are for reference only and are not tested.

(2) This parameter is periodically sampled and not 100% tested.

Output Capacitance 8 pF V
Input Capacitance 6 pF V

7

OUT
IN

= 0V

2051 PGM T05

= 0V

2051 PGM T06.2

X25401

EQUIVALENT A.C. LOAD CIRCUIT

5V

A.C. CONDITIONS OF TEST

Input Pulse Levels 0V to 3V
Input Rise and

919Ω

Fall Times 10ns
Input and Output

OUTPUT

497Ω

100pF

2051 FHD F03

Timing Levels 1.5V

A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Read and Write Cycle Limits

Symbol Parameter Min. Max. Units

(3)

F

SK

t

SCKH

t

SCKL

t

DS

t

DH

t

PD1

t

PD

t

Z

t

CSS

t

CSH

t

CDS

SCK Frequency 1 MHz
SCK Positive Pulse Width 400 ns
SCK Negative Pulse Width 400 ns
Data Setup Time 400 ns
Data Hold Time 80 ns
SCK to Data Bit 0 Valid 375 ns
SCK to Data Valid 375 ns
Chip Select to Output High Z 1 µs
Chip Select Setup 800 ns
Chip Select Hold 350 ns
Chip Deselect 800 ns

POWER-UP TIMING

2051 PGM T07.1

2051 PGM T08.1

Symbol Parameter Max. Units

(4)

t

PUR

(4)

t

PUW

Notes: (3) SCK rise and fall times must be less than 50ns.

(4) t

and t

PUR

are periodically sampled and not 100% tested.

Power-up to Read Operation 200 µs
Power-up to Write or Store Operation 5 ms

are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters

PUW

8

2051 PGM T09

X25401

Write Cycle

SCK CYCLE #

SCK

1/F

SCK

t

SCKH

X12n

t

SCKL

Read Cycle

SK CYCLE #

SCK

CS

CS

SI

12 I1

SI

t

CSS

t

DS

678910n

t

DH

DON’T CARE

t

CSH

t

PD

t

CDS

2051 FHD F04.1

SO

t

PD1

HIGH Z HIGH Z

D0 D1 Dn

t

Z

2051 FHD F05.1

9

X25401

NONVOLATILE OPERATIONS

Operation RECALL Instruction Latch State State

Hardware Recall 0 NOP
Software Recall 1 RCL X X
Software Store 1 STO SET SET

ARRAY RECALL LIMITS

Symbol Parameter Min. Max. Units

Previous

Software Write Enable Recall Latch

(5)

XX

2051 PGM T10

t

RCC

t

RCP

t

RCZ

Recall Cycle Time 2 µs
Recall Pulse Width

(6)

500 ns

Recall to Output in High Z 500 ns

Recall Timing

t

RCC

t

RCP

RECALL

t

RCZ

SO

HIGH Z

SOFTWARE STORE CYCLE LIMITS

Symbol Parameter Min. Typ.

t

ST

Notes: (5) NOP designates when the X25401 is not currently executing an instruction.

(6) Recall rise time must be <10µs.
(7) Typical values are for TA = 25°C and nominal supply voltage.

Store Time After Clock 8 of STO Command 2 5 ms

(7)

2051 PGM T11

2051 FHD F06

Max. Units

2051 PGM T12.1

10

X25401

AUTOSTORE Cycle Limits

Symbol Parameter Min. Max. Units

V

ASTO

V

ASTH

V

ASEND

AUTOSTORE Cycle Time 5 ms
AUTOSTORE Threshold Voltage 4.0 4.3 V
AUTOSTORE Cycle End Voltage 3.5 V

AUTOSTORE Cycle Timing Diagrams

5
4
3
2

VOLTS (V)

1

STORE TIME

V

ASTH

0V

AS

V

CC

AUTOSTORE CYCLE IN PROGRESS

t

ASTO

TIME (ms)

V

CC

t

PUR

t

ASTO

t

PUR

V

ASTH

V

ASEND

2051 PGM T13

2051 FHD F08

SYMBOL TABLE

WAVEFORM

INPUTS

Must be
steady

May change
from LOW
to HIGH

May change
from HIGH
to LOW

Don’t Care:
Changes
Allowed

N/A

OUTPUTS

Will be
steady

Will change
from LOW
to HIGH

Will change
from HIGH
to LOW

Changing:
State Not
Known

Center Line
is High
Impedance

11

X25401

PACKAGING INFORMATION

8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P

0.430 (10.92)

0.360 (9.14)

0.260 (6.60)

0.240 (6.10)

PIN 1 INDEX

PIN 1

0.300

(7.62) REF.

0.060 (1.52)

0.020 (0.51)

HALF SHOULDER WIDTH ON

ALL END PINS OPTIONAL

SEATING

PLANE

0.150 (3.81)

0.125 (3.18)

0.015 (0.38)
MAX.

TYP. 0.010 (0.25)

0.110 (2.79)

0.090 (2.29)

0.325 (8.25)

0.300 (7.62)

0.065 (1.65)

0.045 (1.14)

0.020 (0.51)

0.016 (0.41)

NOTE:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH

0.145 (3.68)

0.128 (3.25)

0.025 (0.64)

0.015 (0.38)

0°

15°

12

3926 FHD F01

X25401

PACKAGING INFORMATION

8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S

PIN 1 INDEX

(4X) 7°

0.050 (1.27)

0.010 (0.25)

0.020 (0.50)

X 45°

PIN 1

0.014 (0.35)

0.019 (0.49)

0.188 (4.78)

0.197 (5.00)

0.150 (3.80)

0.158 (4.00)

0.004 (0.19)

0.010 (0.25)

0.228 (5.80)

0.244 (6.20)

0.053 (1.35)

0.069 (1.75)

0.050" TYPICAL

0° – 8°

0.0075 (0.19)

0.010 (0.25)

0.016 (0.410)

0.037 (0.937)

0.250"

FOOTPRINT

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

3926 FHD F22.1

13

0.050"
TYPICAL

0.030"

TYPICAL

8 PLACES

X25401

ORDERING INFORMATION

X25401 P T -V

Device

VCC Limits

Blank = 5V ±10%

Temperature Range

Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C

Package

P = 8-Lead Plastic DIP
S = 8-Lead SOIC

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes
no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to
discontinue production and change specifications and prices at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.

US. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967;
4,883,976. Foreign patents and additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence.

Xicor’s products are not authorized for use as critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure
of the life support device or system, or to affect its satety or effectiveness.

14