Datasheet X25128SM-2,7, X25128SM, X25128SI-2,7, X25128SI, X25128S14M-2,7 Datasheet (XICOR)
...Page 1
SPI Serial E
2
PROM with Block Lock
TM
Protection
128K
16K x 8 Bit
Xicor Inc. 1994, 1995, 1996 Patents Pending Characteristics subject to change without notice
3091-2.9 5/14/97 T2/C0/D2 SH
1
X25128
A
PPLICATION
N
OTE
AVAILABL E
AN61
FUNCTIONAL DIAGRAM
COMMAND
DECODE
AND
CONTROL
LOGIC
WRITE
CONTROL
AND
TIMING
LOGIC
WRITE
PROTECT
LOGIC
X DECODE
LOGIC
16K BYTE
ARRAY
16 X 256
Y DECODE
DATA REGISTER
SO
SI
SCK
CS
HOLD
WP
832
32 X 256
16 X 256
3091 FM F01
128
128
256
STATUS
REGISTER
FEATURES
•
2MHz Clock Rate
•
SPI Modes (0,0 & 1,1)
•
16K X 8 Bits
—32 Byte Page Mode
•
Low Power CMOS
—<1 µ A Standby Current
—<5mA Active Current
•
2.7V To 5.5V Power Supply
•
Block Lock Protection
—Protect 1/4, 1/2 or all of E
2
PROM Array
•
Built-in Inadvertent Write Protection
—Power-Up/Power-Down protection circuitry
—Write Enable Latch
—Write Protect Pin
•
Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
•
High Reliability
—Endurance: 100,000 cycles
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
•
14-Lead SOIC Package
•
16-Lead SOIC Package
•
8-Lead PDIP Package
DESCRIPTION
The X25128 is a CMOS 131,072-bit serial E
2
PROM,
internally organized as 16K x 8. The X25128 features
a Serial Peripheral Interface (SPI) and software
protocol allowing operation on a simple three-wire bus.
The bus signals are a clock input (SCK) plus separate
data in (SI) and data out (SO) lines. Access to the
device is controlled through a chip select (CS) input,
allowing any number of devices to share the same
bus.
The X25128 also features two additional inputs that
provide the end user with added flexibility. By
asserting the HOLD input, the X25128 will ignore transitions on its inputs, thus allowing the host to service
higher priority interrupts. The WP input can be used as
a hardwire input to the X25128 disabling all write
attempts to the status register, thus providing a mechanism for limiting end user capability of altering 0, 1/4,
1/2 or all of the memory .
The X25128 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
Page 2
X25128
2
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the r ising edge of
the serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes , addresses , or data present
on the SI pin are latched on the rising edge of the
clock input, while data on the SO pin change after the
falling edge of the clock input.
Chip Select (CS)
When CS is high, the X25128 is deselected and the
SO output pin is at high impedance and unless an
internal write operation is underway, the X25128 will
be in the standby power mode. CS low enables the
X25128, placing it in the active power mode. It should
be noted that after power-up, a high to low transition
on CS is required prior to the start of any operation.
Write Protect (WP)
When WP is low and the nonvolatile bit WPEN is “1”,
nonvolatile writes to the X25128 status register are
disabled, but the part otherwise functions normally.
When WP is held high, all functions, including nonvolatile writes operate normally. WP going low while CS is
still low will interrupt a write to the X25128 status
register. If the internal write cycle has already been
initiated, WP going low will have no eff ect on a write.
The WP pin function is blocked when the WPEN bit in
the status register is “0”. This allows the user to install
the X25128 in a system with WP pin grounded and still
be able to write to the status register. The WP pin functions will be enabled when the WPEN bit is set “0”.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought low while SCK is Low. To resume communication, HOLD is brought high, again while SCK is
low. If the pause feature is not used, HOLD
should be
held high at all times.
PIN CONFIGURATION
PIN NAMES
3091 FM T01
Symbol Description
CS
Chip Select Input
SO Serial Output
SI Serial Input
SCK Serial Clock Input
WP
Write Protect Input
V
SS
Ground
V
CC
Supply Voltage
HOLD
Hold Input
NC No Connect
3091 FM 02
Not to scale
14 Lead SOIC
NC
1
2
3
4
7
6
5
X24128
V
SS
NC
NC
NC
NC
.244”
.344”
8
9
10
11
12
14
13
NC
8 Lead PDIP
V
CC
HOLD
SCK
CS
1
2
3
4
6
7
8
X25128
V
SS
SI
5
.325”
.430”
SO
WP
CS
SO
WP
V
CC
HOLD
SCK
SI
16 Lead SOIC
NC
1
2
3
4
7
6
5
X25128
V
SS
NC
NC
NC
NC
NC
.244”
.394”
9
10
11
12
13
14
NC
8
16
15
NC
CS
SO
WP
V
CC
HOLD
SCK
SI
Page 3
X25128
3
PRINCIPLES OF OPERATION
The X25128 is a 8K x 8 E
2
PROM designed to interface directly with the synchronous serial peripheral
interface (SPI) of many popular microcontroller families.
The X25128 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in
on the rising SCK. CS
must be low and the HOLD and
WP inputs must be high during the entire operation.
The WP input is “Don’t Care” if WPEN is set “0”.
Table 1 contains a list of the instructions and their
opcodes. All instructions, addresses and data are
transferred MSB first.
Data input is sampled on the first rising edge of SCK
after CS
goes low. SCK is static, allowing the user to
stop the clock and then resume operations. If the clock
line is shared with other peripheral devices on the SPI
bus, the user can assert the HOLD input to place the
X25128 into a “PAUSE” condition. After releasing
HOLD, the X25128 will resume operation from the
point when HOLD was first asserted.
Write Enable Latch
The X25128 contains a “write enable” latch. This latch
must be SET before a write operation will be
completed internally . The WREN instruction will set the
latch and the WRDI instruction will reset the latch. This
latch is automatically reset upon a power-on condition
and after the completion of a byte, page, or status
register write cycle.
Status Register
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is
formatted as follows:
3091 FM T02
WPEN, BP0 and BP1 are set by the WRSR instruction. WEL and WIP are read-only and automatically set
by other operations.
The Write-In-Process (WIP) bit indicates whether the
X25128 is busy with a write operation. When set to a
“1”, a write is in progress, when set to a “0”, no write is
in progress. During a write, all other bits are set to “1”.
The Write Enable Latch (WEL) bit indicates the status
of the “write enable” latch. When set to a “1”, the latch
is set, when set to a “0”, the latch is reset.
The Block Protect (BP0 and BP1) bits are nonvolatile
and allows the user to select one of four levels of
protection. The X25128 is divided into four 32,768-bit
segments. One, two, or all four of the segments may
be protected. That is, the user may read the segments
but will be unable to alter (write) data within the
selected segments. The partitioning is controlled as
illustrated below .
3091 PGM T03
7 6 5 4 3 2 1 0
WPEN X X X BP1 BP0 WEL WIP
Status Register Bits
Array Addresses
ProtectedBP1 BP0
0 0 None
0 1 $3000–$3FFF
1 0 $2000–$3FFF
1 1 $0000–$3FFF
Table 1. Instruction Set
3091 PGM T04
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
Instruction Name Instruction Format* Operation
WREN 0000 0110 Set the Write Enable Latch (Enable Write Operations)
WRDI 0000 0100 Reset the Write Enable Latch (Disable Write Operations)
RDSR 0000 0101 Read Status Register
WRSR 0000 0001 Write Status Register
READ 0000 0011 Read Data from Memory Array beginning at selected address
WRITE 0000 0010
Write Data to Memory Array beginning at Selected Address
(1 to 32 Bytes)
Page 4
X25128
4
Write-Protect Enable
The Write-Protect-Enable (WPEN) is available for the
X25128 as a nonvolatile enable bit f or the WP
pin.
3091 PGM T05.1
The Write Protect (WP) pin and the nonvolatile Write
Protect Enable (WPEN) bit in the Status Register
control the programmable hardware write protect
feature. Hardware write protection is enabled when
WP pin is low, and the WPEN bit is “1”. Hardware write
protection is disabled when either the WP pin is high
or the WPEN bit is “0”. When the chip is hardware
write protected, nonvolatile writes are disabled to the
Status Register, including the Block Protect bits and
the WPEN bit itself, as well as the block-protected
sections in the memory array. Only the sections of the
memory array that are not block-protected can be
written.
Note: Since the WPEN bit is write protected, it
cannot be changed back to a “0”, as long as
the WP pin is held low .
Clock and Data Timing
Data input on the SI line is latched on the rising edge
of SCK. Data is output on the SO line by the falling
edge of SCK.
Read Sequence
When reading from the E
2
PROM array, CS is first
pulled low to select the device. The 8-bit read instruction is transmitted to the X25128, followed by the
16-bit address of which the last 14 are used. After the
read opcode and address are sent, the data stored in
the memory at the selected address is shifted out on
the SO line. The data stored in memory at the next
address can be read sequentially by continuing to
provide clock pulses. The address is automatically
incremented to the next higher address after each byte
of data is shifted out. When the highest address is
reached ($3FFF) the address counter rolls over to
address $0000 allowing the read cycle to be continued
indefinitely. The read operation is terminated by taking
CS
high. Refer to the read E
2
PROM array operation
sequence illustrated in Figure 1.
To read the status register the CS
line is first pulled
low to select the device followed by the 8-bit instruction. After the RDSR opcode is sent, the contents of
the status register are shifted out on the SO line. The
read status register sequence is illustrated in Figure 2.
Write Sequence
Prior to any attempt to write data into the X25128, the
“write enable” latch must first be set by issuing the
WREN instruction (See Figure 3). CS
is first taken low,
then the WREN instruction is clocked into the X25128.
After all eight bits of the instruction are transmitted, CS
must then be taken high. If the user continues the write
operation without taking CS high after issuing the
WREN instruction, the write operation will be ignored.
To write data to the E
2
PROM memory array, the user
issues the write instruction, followed by the address
and then the data to be written. This is minimally a
thirty-two clock operation. CS must go low and remain
low for the duration of the operation. The host may
continue to write up to 32 bytes of data to the X25128.
The only restriction is the 32 bytes must reside on the
same page. If the address counter reaches the end of
the page and the clock continues, the counter will “roll
over” to the first address of the page and overwrite any
data that may hav e been written.
For the write operation (byte or page write) to be
completed, CS can only be brought high after bit 0 of
data byte N is clocked in. If it is brought high at any
other time the write operation will not be completed.
Refer to Figures 4 and 5 below for a detailed illustration of the write sequences and time frames in which
CS going high are valid.
To write to the status register, the WRSR instruction is
followed by the data to be wr itten. Data bits 0, 1, 4, 5
and 6 must be “0”. This sequence is shown in Figure 6.
While the write is in progress, following a status
register or E
2
PROM write sequence, the status
register may be read to check the WIP bit. During this
time the WIP bit will be high.
Hold Operation
The HOLD input should be high (at V
IH
) under normal
operation. If a data transfer is to be interrupted HOLD
can be pulled low to suspend the transfer until it can
be resumed. The only restriction is the SCK input must
WPEN WP WEL
Protected
Blocks
Unprotected
Blocks
Status
Register
0 X 0 Protected Protected Protected
0 X 1 Protected Writable Writable
1 Low 0 Protected Protected Protected
1 Low 1 Protected Writable Protected
X High 0 Protected Protected Protected
X High 1 Protected Writable Writable
Page 5
X25128
5
be low when HOLD
is first pulled low and SCK must
also be low when HOLD is released.
The HOLD input may be tied high either directly to V
CC
or tied to V
CC
through a resistor.
Operational Notes
The X25128 powers-up in the follo wing state:
• The device is in the low pow er standby state .
• A high to low transition on CS
is required to enter an
active state and receive an instruction.
• SO pin is high impedance.
• The “write enable” latch is reset.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
• The “write enable” latch is reset upon pow er-up .
• A WREN instruction must be issued to set the “write
enable” latch.
• CS must come high at the proper clock count in
order to start a write cycle.
Figure 1. Read E
2
PROM Array Operation Sequence
Figure 2. Read Status Register Operation Sequence
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30
7 6 5 4 3 2 1 0
DATA OUT
CS
SCK
SI
SO
MSB
HIGH IMPEDANCE
INSTRUCTION 16 BITADDRESS
15 14 13 3 2 1 0
3091 FM F03
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
7 6 5 4 3 2 1 0
DATA OUT
CS
SCK
SI
SO
MSB
HIGH IMPEDANCE
INSTRUCTION
3091 FM F04
Page 6
X25128
6
Figure 3. Write Enable Latch Sequence
Figure 4. Byte Write Operation Sequence
0 1 2 3 4 5 6 7
3091 FM F05
CS
SI
SCK
HIGH IMPEDANCE
SO
0 1 2 3 4 5 6 7 8 9 10
CS
SCK
SI
SO
HIGH IMPEDANCE
INSTRUCTION 16 BITADDRESS DATA BYTE
7 6 5 4 3 2 1 015 14 13 3 2 1 0
20 21 22 23 24 25 26 27 28 29 30 31
3091 FM F06
Page 7
X25128
7
Figure 5. Page Write Operation Sequence
Figure 6. Write Status Register Operation Sequence
32 33 34 35 36 37 38 39
SCK
SI
CS
0 1 2 3 4 5 6 7 8 9 10
SCK
SI
INSTRUCTION 16 BITADDRESS DATA BYTE 1
7 6 5 4 3 2 1 0
CS
40 41 42 43 44 45 46 47
DATA BYTE 2
7 6 5 4 3 2 1 0
DATA BYTE 3
7 6 5 4 3 2 1 0
DATA BYTE N
15 14 13 3 2 1 0
20 21 22 23 24 25 26 27 28 29 30 31
6 5 4 3 2 1 0
3091 FM F07
0 1 2 3 4 5 6 7 8 9
CS
SCK
SI
SO
HIGH IMPEDANCE
INSTRUCTION DATA BYTE
7 6 5 4 3 2 1 0
10 11 12 13 14 15
3091 FM F08
Page 8
X25128
8
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias...................–65 ° C to +135 ° C
Storage Temperature........................–65 ° C to +150 ° C
Voltage on any Pin with
Respect to V
SS
....................................–1V to +7V
D.C. Output Current..............................................5mA
Lead Temperature
(Soldering, 10 seconds)..............................300 ° C
D.C. OPERATING CHARACTERISTICS
POWER-UP TIMING
3091 FM T09
CAPACITANCE T
A
= +25 ° C, f = 1MHz, V
CC
= 5V
3091 FM T10.1
Notes: (1) V
IL
min. and V
IH
max. are f or ref erence only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
(3) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated. These
parameters are periodically sampled and not 100% tested.
Limits
Symbol Parameter Min. Max. Units Test Conditions
I
CC
V
CC
Supply Current (Active) 5 mA SCK = V
CC
x 0.1/V
CC
x 0.9 @ 2 MHz,
SO = Open,
CS = V
SS
I
SB
V
CC
Supply Current (Standby) 1
µ
A CS = V
CC
, V
IN
= V
SS
or V
CC
I
LI
Input Leakage Current 10 µA VIN = VSS to V
CC
I
LO
Output Leakage Current 10 µA V
OUT
= VSS to V
CC
V
lL
(1)
Input LOW Voltage –1 VCC x 0.3 V
V
IH
(1)
Input HIGH Voltage VCC x 0.7 VCC + 0.5 V
V
OL1
Output LOW Voltage 0.4 V VCC = 5V, IOL = 3mA
V
OH1
Output HIGH Voltage VCC – 0.8 V VCC = 5V, IOH = -1.6mA
V
OL2
Output LOW Voltage 0.4 V VCC = 3V, IOL = 1.5mA
V
OH2
Output HIGH Voltage VCC – 0.3 V VCC = 3V, IOH = -0.4mA
Symbol Parameter Min. Max. Units
t
PUR
(3)
Power-up to Read Operation 1 ms
t
PUW
(3)
Power-up to Write Operation 5 ms
Symbol Test Max. Units Conditions
C
OUT
(2)
Output Capacitance (SO) 8 pF V
OUT
= 0V
C
IN
(2)
Input Capacitance (SCK, SI, CS, WP, HOLD) 6 pF VIN = 0V
RECOMMENDED OPERATING CONDITIONS
3091 FM T06.1
Temperature Min. Max.
Commercial 0°C +70°C
Industrial –40°C +85°C
Military –55°C +125°C
3091 FM T07.2
Supply Voltage Limits
X25128 5V ±10%
X25128-2.7 2.5V to 5.5V
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended per iods may
affect device reliability.
Page 9
X25128
9
A.C. OPERATING CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified.)
Data Input Timing
3091 FM T12.2
Data Output Timing
3091 FM T13.2
Notes: (4) This parameter is periodically sampled and not 100% tested.
(5) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal
nonvolatile write cycle.
Symbol Parameter Min. Max. Units
f
SCK
Clock Frequency 0 2 MHz
t
CYC
Cycle Time 500 ns
t
LEAD
CS Lead Time 250 ns
t
LAG
CS Lag Time 250 ns
t
WH
Clock HIGH Time 200 ns
t
WL
Clock LOW Time 200 ns
t
SU
Data Setup Time 50 ns
t
H
Data Hold Time 50 ns
t
RI
(4)
Data In Rise Time 2 µs
t
FI
(4)
Data In Fall Time 2 µs
t
HD
HOLD Setup Time 100 ns
t
CD
HOLD Hold Time 100 ns
t
CS
CS Deselect Time 2.0 µs
t
WC
(5)
Write Cycle Time 10 ms
Symbol Parameter Min. Max. Units
f
SCK
Clock Frequency 0 2 MHz
t
DIS
Output Disable Time 250 ns
t
V
Output Valid from Clock LOW 200 ns
t
HO
Output Hold Time 0 ns
t
RO
(4)
Output Rise Time 100 ns
t
FO
(4)
Output Fall Time 100 ns
t
LZ
(4)
HOLD HIGH to Output in Low Z 100 ns
t
HZ
(4)
HOLD LOW to Output in Low Z 100 ns
A.C. CONDITIONS OF TEST
3091 FM T11
Input Pulse Levels VCC x 0.1 to VCC x 0.9
Input Rise and Fall
Times
10ns
Input and Output
Timing Levels
V
CC
X 0.5
EQUIVALENT A.C. LOAD CIRCUIT
OUTPUT
3091 FM F09.1
5V
1.44KΩ
1.95KΩ
100pF
OUTPUT
3V
1.64KΩ
4.63KΩ
100pF
Page 10
X25128
10
Serial Output Timing
Serial Input Timing
SCK
CS
SO
SI
MSB OUT MSB–1 OUT LSB OUT
ADDR
LSB IN
t
CYC
t
V
t
HO
t
WL
t
WH
t
DIS
3091 FM F10.1
t
LAG
SCK
CS
SI
SO
MSB IN
t
SU
t
RI
t
LAG
3091 FM F11
t
LEAD
t
H
LSB IN
t
CS
t
FI
HIGH IMPEDANCE
Page 11
X25128
11
Hold Timing
Symbol Table
SCK
CS
SI
SO
t
HD
3091 FM F12.1
t
LZ
HOLD
t
CD
t
HZ
t
CD
t
HD
Must be
steady
Will be
steady
May change
from LOW
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
WAVEFORM INPUTS OUTPUTS
Page 12
X25128
12
PACKAGING INFORMATION
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
0.020 (0.51)
0.016 (0.41)
0.150 (3.81)
0.125 (3.18)
0.110 (2.79)
0.090 (2.29)
0.430 (10.92)
0.360 (9.14)
0.300
(7.62) REF.
PIN 1 INDEX
0.145 (3.68)
0.128 (3.25)
0.025 (0.64)
0.015 (0.38)
PIN 1
SEATING
PLANE
0.065 (1.65)
0.045 (1.14)
0.260 (6.60)
0.240 (6.10)
0.060 (1.52)
0.020 (0.51)
TYP.0.010 (0.25)
0°
15°
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
HALF SHOULDER WIDTH ON
ALL END PINS OPTIONAL
0.015 (0.38)
MAX.
0.325 (8.25)
0.300 (7.62)
7040 FM 18
Page 13
X25128
13
PACKAGING INFORMATION
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
0.014 (0.35)
0.020 (0.51)
PIN 1
PIN 1 INDEX
0.050 (1.27)
0.336 (8.55)
0.345 (8.75)
0.004 (0.10)
0.010 (0.25)
0.053 (1.35)
0.069 (1.75)
(4X) 7°
14-LEAD PLASTIC SMALL OUTLINE GULLWING PACKAGE TYPE S
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
0.250"
0.050"Typical
0.050"Typical
0.030"Typical
14 Places
FOOTPRINT
0.010 (0.25)
0.020 (0.50)
0.016 (0.410)
0.037 (0.937)
0.0075 (0.19)
0.010 (0.25)
0° – 8°
X 45°
Page 14
X25128
14
PACKAGING INFORMATION
16-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
0.014 (0.35)
0.020 (0.51)
PIN 1
PIN 1 INDEX
0.050 (1.27)
0.386 (9.80)
0.394 (10.01)
0.004 (0.19)
0.010 (0.25)
0.053 (1.35)
0.069 (1.75)
(4X) 7°
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
0.250"
0.050" Typical
0.030" Typical
16 Places
FOOTPRINT
0.010 (0.25)
0.020 (0.50)
0.016 (0.410)
0.037 (0.937)
0.0075 (0.19)
0.010 (0.25)
0° – 8°
X 45°
0.050"
Typical
Page 15
X25128
15
ORDERING INFORMATION
Part Mark Convention
Device
X25128 X X -X
VCC Range
Blank = 5V ±10%
2.7 = 2.7V to 5.5V
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Package
S = 16-Lead SOIC
Blank = 5V ±10%, 0°C to +70°C
I = 5V ±10%, –40°C to +85°C
M = 5V ±10%, –55°C to +125°C
F = 2.7V to 5.5V, 0°C to +70°C
X25128 X
X
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc.
makes no warranty, express, statutory, implied, or by descr iption regarding the information set forth herein or regarding the freedom of the
described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the
right to discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967;
4,883, 976. Foreign patents and additional patents pending.
LIFE RELA TED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prev ent such an occurence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain
life, and whose failure to perfor m, when properly used in accordance with instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its saf ety or eff ectiv eness .
S = 16-Lead SOIC
G = 2.7V to 5.5V, –40°C to +85°C
P = 8-Lead PDIP
P = 8-Lead PDIP
S14 = 14-Lead SOIC
S14 = 14-Lead SOIC
M = Military = –55°C to +125°C
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