Datasheet X25043S, X25043PI-2,7, X25043PI, X25043P, X25043P-2,7 Datasheet (XICOR)

X25043/45

1

DESCRIPTION

The X25043/45 combines three popular functions,
Watchdog Timer, Voltage Supervision, and E2PROM in
a single package. This combination lowers the system
cost and reduces the board space requirements.

The Watchdog Timer provides an independent protec­tion system for microcontrollers. During a system failure,
the X25043/45 watchdog will respond with a RESET/
RESET signal after a selectable time-out interval. The
user selects the interval from three preset values. Once
selected, the interval does not change, even after cy­cling the power.

The system is protected from low voltage conditions by
the X25043/45 low VCC detection circuits. When V

CC

drops below the minimum VCC trip point, the system is
reset. Reset is asserted until VCC returns and stabilizes.

The memory portion of the X25043/45 is a CMOS 4096­bit serial E2PROM, internally organized as 512 X 8. The
X25043/45 features a Serial Peripheral Interface (SPI)
and software protocol allowing operation on a simple
three-wire bus.

The X25043/45 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000 cycles
per byte and a minimum data retention of 100 years.

4K X25043/45 512 x 8 Bit

©Xicor, Inc. 1994, 1995, 1996 Patents Pending Characteristics subject to change without notice
3844-6.5 5/9/96 T4/C2/D2 NS

Direct Write™ is a trademark of Xicor, Inc.

Programmable Watchdog Supervisory E2PROM

FEATURES

• Programmable Watchdog Timer

• Low V

CC

Detection

• Reset Signal Valid to V

CC

= 1V

• 1MHz Clock Rate

• 512 X 8 Bits Serial E

2

PROM

—4 Byte Page Mode

• Low Power CMOS

—50µA Standby Current
—3mA Active Current

• 2.7V To 5.5V Power Supply

• Block Lock

TM

—Protect 1/4, 1/2 or all of E2PROM Array

• Built-in Inadvertent Write Protection

—Power-Up/Power-Down protection circuitry
—Write Latch
—Write Protect Pin

• High Reliability

—Endurance: 100,000 cycles per byte
—Data Retention: 100 Years
—ESD protection: 2000V on all pins

• Available Packages

—8-Lead PDlP
—8-Lead SOIC
—14-Lead TSSOP

• X25043 = Active LOW RESET

• X25045 = Active HIGH RESET

DIE PHOTOGRAPH

APPLICATION NOTES

AVAILABLE

AN11 • AN21

3844 ILL F01

PROGRAMMABLE

VOLTAGE

SENSOR

PROGRAMMABLE

VOLTAGE

SENSOR

RESET

CONTROL

LOGIC

RESET

CONTROL

LOGIC

HIGH VOLTAGE GENERATOR

AND

CONTROL

HIGH VOLTAGE GENERATOR

AND

CONTROL

4K BITS E2PROM

4K BITS E

2

PROM

W

A

T
C
H
D
O
G

T

I

M

E

R

W

A

T

C
H
D
O
G

T

I

M

E
R

SERIAL

INTERFACE

LOGIC

SERIAL

INTERFACE

LOGIC

X25043/45

2

PIN DESCRIPTIONS
Serial Output (SO)

SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.

Serial Input (SI)

SI is the serial data input pin. All opcodes, byte ad­dresses, and data to be written to the memory are input
on this pin. Data is latched by the rising edge of the serial
clock.

Serial Clock (SCK)

The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin is latched on the rising edge of the clock
input, while data on the SO pin changes after the falling
edge of the clock input.

Chip Select (CS)

When CS is HIGH, the X25043/45 is deselected and the
SO output pin is at high impedance and, unless an
internal write operation is underway, the X25043/45 will
be in the standby power mode. CS LOW enables the
X25043/45, placing it in the active power mode. It should
be noted that after power-up, a HIGH to LOW transition
on CS is required prior to the start of any operation.

Write Protect (WP)

When WP is LOW, nonvolatile writes to the X25043/45
are disabled, but the part otherwise functions normally.
When WP is held HIGH, all functions, including nonvola­tile writes operate normally. WP going LOW while CS is
still LOW will interrupt a write to the X25043/45. If the
internal write cycle has already been initiated, WP going
LOW will have no affect on a write.

Reset (RESET, RESET)

X25043/45, RESET/RESET is an active LOW/HIGH,
open drain output which goes active whenever V

CC

falls below the mimimum VCC sense level. It will remain
active until VCC rises above the minimum VCC sense
level for 200ms. RESET/RESET also goes active if
the Watchdog timer is enabled and CS remains either
HIGH or LOW longer than the Watchdog time-out
period. A falling edge of CS will reset the watchdog timer.

PIN NAMES

Symbol Description

CS Chip Select Input
SO Serial Output
SI Serial Input
SCK Serial Clock Input
WP Write Protect Input
V

SS

Ground

V

CC

Supply Voltage

RESET/RESET Reset Output

3844 PGM T01.1

PIN CONFIGURATION

3844 ILL F02.3

CS
SO

WP

V

SS

1
2
3
4

8
7
6
5

V

CC

RESET/RESET
SCK
SI

8-LEAD DIP/SOIC

X25043/45

14-LEAD TSSOP

X25043/45

CS
SO
NC
NC
NC

WP

V

SS

V

CC

RESET/RESET

NC
NC
NC
SCK
SI

14
13
12
11
10

9
8

1
2
3
4
5
6
7

X25043/45

3

PRINCIPLES OF OPERATION

The X25043/45 is a 512 x 8 E2PROM designed to
interface directly with the synchronous serial peripheral
interface (SPI) of many popular microcontroller families.

The X25043/45 contains an 8-bit instruction register. It
is accessed via the SI input, with data being clocked in
on the rising SCK. CS must be LOW and WP input must
be HIGH during the entire operation. The X25043/45
monitors the bus and provides a RESET/RESET output
if there is no bus activity within the preset time period.

Table 1 contains a list of the instructions and their
operation codes. All instructions, addresses and data
are transferred MSB first. Bit 3 of the Read and Write
instructions contain the higher order address bit, A8.

Data input is sampled on the first rising edge of SCK after
CS goes LOW. SCK is static, allowing the user to stop
the clock and then resume operations.

Write Enable Latch

The X25043/45 contains a “write enable” latch. This
latch must be SET before a write operation will be
completed internally. The WREN instruction will set the
latch and the WRDI instruction will reset the latch. This
latch is automatically reset upon a power-up condition
and after the completion of a byte, page, or status
register write cycle. The latch is also reset if WP is
brought LOW.

Status Register

The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format­ted as follows:

76543210
X X WD1 WD0 BL1 BL0 WEL WIP

3844 PGM T02

When issuing, WREN, WRDI and RDSR commands, it
is not necessary to send a byte address or data.

The Write-In-Process (WIP) bit indicates whether the
X25043/45 is busy with a write operation. When set to a
“1”, a write is in progress, when set to a “0”, no write is
in progress. During a write, all other bits are set to “1”.
The WIP bit is read-only.

The Write Enable Latch (WEL) bit indicates the status of
the “write enable” latch. When set to a “1”, the latch is set,
when set to a “0”, the latch is reset. The WEL bit is read­only and is set by the WREN instruction and reset by
WRDI instruction or successful completion of a write
cycle.

The Block Protect (BL0 and BL1) bits indicate the extent
of protection employed. These nonvolatile bits are set by
issuing the WRSR instruction and allows the user to
select one of four levels of protection and program the
watchdog timer. The X25043/45 is divided into four
1024-bit segments. One, two, or all four of the segments
may be locked. That is, the user may read the segments
but will be unable to alter (write) data within the selected
segments. The partitioning is controlled as illustrated
below with the state of BL1 and BL0.

Status Register Bits Array Addresses

BL1 BL0 Protected

0 0 None
0 1 $180–$1FF
1 0 $100–$1FF
1 1 $000–$1FF

3844 PGM T04

The Watchdog Timer (WD0 and WD1) bits allow setting
of the watchdog time-out function as shown in the table
below. These nonvolatile bits are set by issuing the
WRSR instruction.

Status Register Bits Watchdog Time-out

WD1 WD0 (Typical)

0 0 1.4 Seconds
0 1 600 Milliseconds
1 0 200 Milliseconds
1 1 Disabled

3844 PGM T03

X25043/45

4

Clock and Data Timing

Data input on the SI line is latched on the rising edge of
SCK. Data is output on the SO line by the falling edge of
SCK.

Read Sequence

When reading from the E2PROM memory array, CS is
first pulled LOW to select the device. The 8-bit READ
instruction is transmitted to the X25043/45, followed by
the 8-bit byte address. Bit 3 of the Read instruction
contains address A8. This bit is used to select the upper
or lower half of the device. After the read opcode and
byte address are sent, the data stored in the memory
at the selected address is shifted out on the SO line.
The data stored in memory at the next address can be
read sequentially by continuing to provide clock pulses.
The byte address is automatically incremented to the
next higher address after each byte of data is shifted
out. When the highest address is reached ($1FF) the
address counter rolls over to address $000, allowing
the read cycle to be continued indefinitely. The read
operation is terminated by taking CS HIGH. Refer to the
read E2PROM Array operation sequence illustrated in
Figure 1.

To read the status register the CS line is first pulled
LOW to select the device followed by the 8-bit RDSR
instruction. After the read status register opcode is
sent, the contents of the status register is shifted out on
the SO line as shown in Figure 2.

Write Sequence

Prior to any attempt to write data into the X25043/45 the
“write enable” latch must first be set by issuing
the WREN instruction (See Figure 3). CS is first taken
LOW, then the WREN instruction is clocked into the
X25043/45. After all eight bits of the instruction are

transmitted, CS must then be taken HIGH. If the user
continues the write operation without taking CS HIGH
after issuing the WREN instruction the write operation
will be ignored.

To write data to the E2PROM memory array, the user
issues the WRITE instruction, followed by the address
and then the data to be written. Bit 3 of the Write
instruction contains address A8. This bit is used to select
the upper or lower half of the device. This is minimally a
twenty-four clock operation. CS must go LOW and
remain LOW for the duration of the operation. The host
may continue to write up to four bytes of data to the
X25043/45. The only restriction is the four bytes must
reside on the same page. A page address begins with
address X XXXX XX00 and ends with X XXXX XX11. If
the byte address counter reaches X XXXX XX11 and the
clock continues the counter will roll back to the first
address of the page and overwrite any data that may
have been written.

For the write operation (byte or page write) to be
completed, CS can only be brought HIGH after the
twenty-fourth, thirty-second, fortieth, or forty-eighth
clock. If it is brought HIGH at any other time, the write
operation will not be completed. Refer to Figure 4 and 5
below for a detailed illustration of the write sequences.

While the write is in progress, following a status register
or E2PROM write sequence the status register may be
read to check the WIP bit. During this time the WIP bit will
be HIGH and all other bits in the status register will be
undefined.

RESET/RESET Operation

The RESET (X25043) output is designed to go LOW
whenever VCC has dropped below the minimum trip
point and/or the Watchdog timer has reached its pro­grammable time-out limit.

Table 1. Instruction Set

Instruction Name Instruction Format* Operation

WREN 0000 0110 Set the Write Enable Latch (Enable Write Operations)

WRDI 0000 0100 Reset the Write Enable Latch (Disable Write Operations)

RDSR 0000 0101 Read Status Register

WRSR 0000 0001 Write Status Register (Block Lock Bits)

READ 0000 A8011

Read Data from Memory Array beginning at selected
address

WRITE 0000 A8010

Write Data to Memory Array beginning at Selected Address
(1 to 4 Bytes)

3844 PGM T05.1

*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.

X25043/45

5

Figure 1. Read E2PROM Array Operation Sequence

The RESET (X25045) output is designed to go HIGH
whenever V

CC

has dropped below the minimum trip
point and/or the watchdog timer has reached its pro­grammable time-out limit.

Operational Notes

The X25043/45 powers-up in the following state:

• The device is in the low power standby state.

• A HIGH to LOW transition on CS is required to

enter an active state and receive an instruction.

• SO pin is high impedance.

• The “write enable” latch is reset.

Data Protection

The following circuitry has been included to prevent
inadvertent writes:

• The “write enable” latch is reset upon power-up.

• A WREN instruction must be issued to set the “write
enable” latch.

• CS must come HIGH at the proper clock count in
order to start a write cycle.

The “write enable” latch is reset when WP is brought
LOW.

Figure 2. Read Status Register Operation Sequence

01234567891011121314

76543210

DATA OUT

CS

SCK

SI

SO

MSB

HIGH IMPEDANCE

INSTRUCTION

3844 ILL F15

012345678910111213141516171819202122

3844 FHD F04

76543210

DATA OUT

CS

SCK

SI

SO

MSB

HIGH IMPEDANCE

INSTRUCTION BYTE ADDRESS

765432108

9TH BIT OF ADDRESS

X25043/45

6

Figure 3. Write Enable Latch Sequence

01234567891011121314151617181920212223

3844 FHD F06

CS

SCK

SI

SO

HIGH IMPEDANCE

INSTRUCTION BYTE ADDRESS

DATA BYTE

76543210

76543210

8

9TH BIT OF ADDRESS

Figure 4. Byte Write Operation Sequence

01234567

3844 FHD F05

CS

SI

SCK

HIGH IMPEDANCE

SO

SYMBOL TABLE

WAVEFORM

INPUTS

OUTPUTS

Must be
steady

Will be
steady

May change
from LOW
to HIGH

Will change
from LOW
to HIGH

May change
from HIGH
to LOW

Will change
from HIGH
to LOW

Don’t Care:
Changes
Allowed

Changing:
State Not
Known

N/A

Center Line
is High
Impedance

X25043/45

7

Figure 5. Page Write Operation Sequence

Figure 6. Write Status Register Operation Sequence

24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

SCK

SI

CS

01234567891011121314151617181920212223

3844 FHD F07

SCK

SI

INSTRUCTION BYTE ADDRESS

DATA BYTE 1

76543210

CS

40 41 42 43 44 45 46 47

DATA BYTE 2

76543210

DATA BYTE 3

76543210

DATA BYTE 4

76543210

76543210

8

9TH BIT OF ADDRESS

0123456789

CS

SCK

SI

SO

HIGH IMPEDANCE

INSTRUCTION

DATA BYTE

76543210

10 11 12 13 14 15

3844 ILL F08

X25043/45

8

Notes: (1) VIL min. and VIH max. are for reference only and are not tested.

(2) This parameter is periodically sampled and not 100% tested.

*COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
listed in the operational sections of this specification is
not implied. Exposure to absolute maximum rating con­ditions for extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS*

Temperature under Bias .................. –65°C to +135°C

Storage Temperature ....................... –65°C to +150°C

Voltage on any Pin with Respect to V

SS

......

–1.0V to +7V

D.C. Output Current .............................................5mA

Lead Temperature

(Soldering, 10 seconds).............................. 300°C

RECOMMENDED OPERATING CONDITIONS

Temp Min. Max.

Commercial 0°C70°C
Industrial –40°C +85°C

3844 PGM T06.1

CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V.

Symbol Test Max. Units Conditions

C

OUT

(2)

Output Capacitance (SO, RESET, RESET) 8 pF V

OUT

= 0V

C

IN

(2)

Input Capacitance (SCK, SI, CS, WP)6pFV

IN

= 0V

3844 PGM T10.2

POWER-UP TIMING

Symbol Parameter Min. Max. Units

t

PUR

(2)

Power-up to Read Operation 1 ms

t

PUW

(2)

Power-up to Write Operation 5 ms

3844 PGM T09

Supply Voltage Limits

X25043/45 5V ±10%
X25043/45-2.7 2.7 to 5.5V

3844 PGM T07.3

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Limits

Symbol Parameter Min. Max. Units Test Conditions

I

CC

VCC Supply Current (Active) 3 mA SCK = VCC x 0.1/VCC x 0.9 @ 1MHz,

SO = Open

I

SB1

VCC Standby Current 50 µA CS = V

CC

, VIN = VSS or VCC, VCC = 5.5

I

SB2

VCC Standby Current 20 µA CS = VCC, VIN = VSS or VCC, VCC = 2.7V

I

LI

Input Leakage Current 10 µAVIN = VSS to V

CC

I

LO

Output Leakage Current 10 µAV

OUT

= VSS to V

CC

V

IL

(1)

Input LOW Voltage –0.5 V

CC

x 0.3 V

V

IH

(1)

Input HIGH Voltage V

CC

x 0.7 V

CC

+ 0.5 V

V

OL

Output LOW Voltage 0.4 V IOL = 2mA

V

OH1

Output HIGH Voltage VCC–0.8 V IOH = –1.6mA, V

CC

= 4.5V

V

OH2

Output HIGH Voltage VCC–0.4 V IOH = –.4mA, V

CC

= 2.7V

VOLRS Reset Output LOW Voltage 0.4 V I

OL

= 1mA

3844 PGM T08.3

X25043/45

9

EQUIVALENT A.C. LOAD CIRCUIT AT 5V VCC A.C. TEST CONDITIONS

Input Pulse Levels VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times 10ns

Input and Output Timing Level VCC x 0.5

3844 PGM T11

Notes: (3) This parameter is periodically sampled and not 100% tested.

(4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal

nonvolatile write cycle.

A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Data Input Timing

Symbol Parameter Min. Max. Units

f

SCK

Clock Frequency 0 1 MHz

t

CYC

Cycle Time 1000 ns

t

LEAD

CS Lead Time 500 ns

t

LAG

CS Lag Time 500 ns

t

WH

Clock HIGH Time 500 ns

t

WL

Clock LOW Time 400 ns

t

SU

Data Setup Time 100 ns

t

H

Data Hold Time 100 ns

t

RI

(3)

Input Rise Time 2 µs

t

FI

(3)

Input Fall Time 2 µs

t

CS

CS Deselect Time 500 ns

t

WC

(4)

Write Cycle Time 10 ms

3844 PGM T12.2

5V

OUTPUT

100pF

3844 FHD F12.2

5V

4.6KΩ

RESET/RESET

100pF

Data Output Timing

Symbol Parameter Min. Max. Units

f

SCK

Clock Frequency 0 1 MHz

t

DIS

Output Disable Time 500 ns

t

V

Output Valid from Clock LOW 400 ns

t

HO

Output Hold Time 0 ns

t

RO

(3)

Output Rise Time 300 ns

t

FO

(3)

Output Fall Time 300 ns

3844 PGM T13.1

X25043/45

10

Serial Output Timing

Serial Input Timing

SCK

CS

SO

SI

MSB OUT MSB–1 OUT LSB OUT

ADDR
LSB IN

t

CYC

t

V

t

HO

t

WL

t

WH

t

DIS

3844 FHD F09

t

LAG

SCK

CS

SI

SO

MSB IN

t

SU

t

RI

t

LAG

3844 FHD F10

t

LEAD

t

H

LSB IN

t

CS

t

FI

HIGH IMPEDANCE

X25043/45

11

Power-Up and Power-Down Timing

Symbol Parameter Min. Typ. Max. Units

t

WDO

Watchdog Timeout Period,
WD1=1,WD0=0 100 200 300 ms
WD1=0,WD0=1 450 600 800 ms
WD1=0,WD0=0 1 1.4 2 sec

t

CST

CS Pulse Width to Reset the Watchdog 400 ns

t

RST

Reset Timeout 100 400 ms

3844 PGM T15.3

CS vs RESET/RESET Timing

Notes: (5) This parameter is periodically sampled and not 100% tested.

RESET Output Timing

Symbol Parameter Min. Typ. Max. Units

V

TRIP

Reset Trip Point Voltage, 5V Device 4.25 4.5 V
Reset Trip Point Voltage, 2.7V Device 2.55 2.7 V

t

PURST

Power-up Reset Timeout 100 400 ms

t

RPD

(5) V

CC

Detect to Reset/Output 500 ns

t

F

(5) V

CC

Fall Time 10 µs

t

R

(5) V

CC

Rise Time 0 ns

V

RVALID

Reset Valid V

CC

1V

3844 PGM T14.3

RESET/RESET Output Timing

VCC

3844 FHD F13.1

t

PURST

t

PURST

t

R

t

F

t

RPD

RESET (X25043)

0 Volts

V

TRIP

V

TRIP

RESET (X25045)

CS

3844 FHD F14.1

t

CST

RESET

t

WDO

t

RST

RESET

t

WDO

t

RST

X25043/45

12

PACKAGING INFORMATION

NOTE:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH

0.020 (0.51)

0.016 (0.41)

0.150 (3.81)

0.125 (3.18)

0.110 (2.79)

0.090 (2.29)

0.430 (10.92)

0.360 (9.14)

0.300

(7.62) REF.

PIN 1 INDEX

0.145 (3.68)

0.128 (3.25)

0.025 (0.64)

0.015 (0.38)

PIN 1

SEATING

PLANE

0.065 (1.65)

0.045 (1.14)

0.260 (6.60)

0.240 (6.10)

0.060 (1.52)

0.020 (0.51)

TYP. 0.010 (0.25)

0°

15°

8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P

HALF SHOULDER WIDTH ON

ALL END PINS OPTIONAL

0.015 (0.38)
MAX.

0.325 (8.25)

0.300 (7.62)

X25043/45

13

PACKAGING INFORMATION

0.150 (3.80)

0.158 (4.00)

0.228 (5.80)

0.244 (6.20)

0.014 (0.35)

0.019 (0.49)

PIN 1

PIN 1 INDEX

0.010 (0.25)

0.020 (0.50)

0.050 (1.27)

0.188 (4.78)

0.197 (5.00)

0.004 (0.19)

0.010 (0.25)

0.053 (1.35)

0.069 (1.75)

(4X) 7°

0.016 (0.410)

0.037 (0.937)

0.0075 (0.19)

0.010 (0.25)

0° – 8°

X 45°

8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

0.250"

0.050" TYPICAL

0.050"
TYPICAL

0.030"

TYPICAL

8 PLACES

FOOTPRINT

X25043/45

14

PACKAGING INFORMATION

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

14-LEAD PLASTIC, TSSOP PACKAGE TYPE V

See Detail “A”

.031 (.80)

.041 (1.05)

.169 (4.3)
.177 (4.5)

.252 (6.4) BSC

.025 (.65) BSC

.193 (4.9)
.200 (5.1)

.002 (.05)
.006 (.15)

.047 (1.20)

.0075 (.19)
.0118 (.30)

0° – 8°

.010 (.25)

.019 (.50)
.029 (.75)

Gage Plane

Seating Plane

Detail A (20X)

3926 FHD F32

X25043/45

15

Device

ORDERING INFORMATION

VCC Limits

Blank = 5V ±10%

2.7 = 2.7V to 5.5V

Temperature Range

Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C

Package

P = 8-Lead Plastic DIP
S = 8-Lead SOIC
V = 14-Lead TSSOP

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are
implied.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and
additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and back-up features to prevent such an occurrence.

Xicor's products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.

Part Mark Convention

X25043/45 P T -V

X25043/45 X

X

Blank = 8-Lead SOIC
P = 8-Lead Plastic DIP
V = 14-Lead TSSOP

Blank = 5V ±10%, 0°C to +70°C
I = 5V ±10%, –40°C to +85°C
F = 2.7V to 5.5V, 0°C to +70°C
G = 2.7V to 5.5V, –40°C to +85°C