Datasheet X25021PI, X25021P-3, X25021P-2,7, X25021P, X25021SI-3 Datasheet (XICOR)

X25021

1

2K X25021 256 x 8 Bit

©Xicor, Inc. 1995, 1996 Patents Pending Characteristics subject to change without notice
6615-1.5 6/10/96 T3/C1/D0 NS

Direct Write™ and Block Lock™ Protection is a trademark of Xicor, Inc.

SPI Serial E2PROM with Block Lock

TM

Protection

FEATURES

• 1MHz Clock Rate

• SPI Modes (0,1 & 1,0)

• 256 X 8 Bits

—4 Byte Page Mode

• Low Power CMOS

—10µA Standby Current
—3mA Active Current

• 2.7V To 5.5V Power Supply

• Block Lock Protection

—Protect 1/4, 1/2 or all of E2PROM Array

• Built-in Inadvertent Write Protection

—Power-Up/Power-Down protection circuitry
—Write Latch
—Write Protect Pin

• Self-Timed Write Cycle

—5ms Write Cycle Time (Typical)

• High Reliability

—Endurance: 100,000 cycles per byte
—Data Retention: 100 Years
—ESD protection: 2000V on all pins

• 8-Lead PDlP Package

• 8-Lead SOIC Package

DESCRIPTION

The X25021 is a CMOS 2048-bit serial E2PROM, inter­nally organized as 256 x 8. The X25021 features a Serial
Peripheral Interface (SPI) and software protocol allow­ing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in (SI)
and data out (SO) lines. Access to the device is con­trolled through a chip select (CS) input, allowing any
number of devices to share the same bus.

The X25021 also features two additional inputs that
provide the end user with added flexibility. By asserting
the HOLD input, the X25021 will ignore transitions on its
inputs, thus allowing the host to service higher priority
interrupts. The WP input can be used as a hardwire input
to the X25021 disabling all write attempts, thus providing
a mechanism for limiting end user capability of altering
the memory.

The X25021 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000 cycles
per byte and a minimum data retention of 100 years.

6615 FHD F01

FUNCTIONAL DIAGRAM

COMMAND

DECODE

AND

CONTROL

LOGIC

WRITE

CONTROL

AND

TIMING

LOGIC

WRITE

PROTECT

LOGIC

X DECODE

LOGIC

256 BYTE

ARRAY

16 X 32

Y DECODE

DATA REGISTER

16 X 32

32 X 32

SO

SI

SCK

CS

HOLD

WP

16

16

32

84

STATUS

REGISTER

X25021

2

PIN DESCRIPTIONS
Serial Output (SO)

SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the rising edge of the serial clock.

Serial Input (SI)

SI is the serial data input pin. All opcodes, byte ad­dresses, and data to be written to the memory are input
on this pin. Data is latched by the falling edge of the serial
clock.

Serial Clock (SCK)

The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the falling edge of the clock
input, while data on the SO pin change after the rising
edge of the clock input.

Chip Select (CS)

When CS is HIGH, the X25021 is deselected and the SO
output pin is at high impedance and unless an internal
write operation is underway, the X25021 will be in the
standby power mode. CS LOW enables the X25021,
placing it in the active power mode. It should be noted
that after power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.

Write Protect (WP)

When WP is LOW, nonvolatile writes to the X25021 are
disabled, but the part otherwise functions normally.
When WP is held HIGH, all functions, including nonvola-
tile writes operate normally. WP going LOW while CS is
still LOW will interrupt a write to the X25021. If the
internal write cycle has already been initiated, WP going
LOW will have no affect on a write.

Hold (HOLD)
HOLD is used in conjunction with the CS pin to select the

device. Once the part is selected and a serial sequence is
underway, HOLD may be used to pause the serial
communication with the controller without resetting the
serial sequence. To pause, HOLD must be brought LOW
while SCK is HIGH. To resume communication, HOLD is
brought HIGH, again while SCK is HIGH. If the pause
feature is not used, HOLD should be held HIGH at all
times.

PIN CONFIGURATION

PIN NAMES

Symbol Description

CS Chip Select Input
SO Serial Output
SI Serial Input
SCK Serial Clock Input
WP Write Protect Input
V

SS

Ground

V

CC

Supply Voltage

HOLD Hold Input

6615 PGM T01

6615 FHD F02

CS
SO

WP

V

SS

1
2
3
4

8
7
6
5

V

CC

HOLD
SCK
SI

DIP/SOIC

X25021

X25021

3

PRINCIPLES OF OPERATION

The X25021 is a 256 x 8 E2PROM designed to interface
directly with the synchronous serial peripheral interface
(SPI) of many popular microcontroller families.

The X25021 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on
the falling SCK. CS must be LOW during the entire
operation.

Table 1 contains a list of the instructions and their codes.
All instructions, addresses and data are transferred
MSB first.

Data input is sampled on the first falling edge of SCK
after CS goes LOW. SCK is static, allowing the user to
stop the clock and then resume operations. If the clock
line is shared with other peripheral devices on the SPI
bus, the user can assert the HOLD input to place the
X25021 into a “PAUSE” condition. After releasing HOLD,
the X25021 will resume operation from the point when
HOLD was first asserted.

Write Enable Latch

The X25021 contains a “write enable” latch. This latch
must be SET before a write operation will be completed
internally. The WREN instruction will set the latch and
the WRDI instruction will reset the latch. This latch is
automatically reset upon a power-up condition and after
the completion of a byte, page, or status register write
cycle.

Table 1. Instruction Set

Instruction Name Instruction Format* Operation

WREN 0000 0110 Set the Write Enable Latch (Enable Write Operations)

WRDI 0000 0100 Reset the Write Enable Latch (Disable Write Operations)

RDSR 0000 0101 Read Status Register

WRSR 0000 0001 Write Status Register

READ 0000 0011 Read Data from Memory Array beginning at selected address

WRITE 0000 0010 Write Data to Memory Array beginning at Selected Address

(1 to 32 Bytes)

6615 PGM T04

*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.

7 654 3 2 1 0
X X X X BP1 BP0 WEL WIP

6615 PGM T02

Status Register

The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format­ted as follows:

BP0 and BP1 are set by the WRSR instruction. WEL
and WIP are read-only and automatically set by other
operations.

The Write-In-Process (WIP) bit indicates whether the
X25021 is busy with a write operation. When set to a “1”,
a write is in progress, when set to a “0”, no write is in
progress. During a write, all other bits are set to “1”.

The Write Enable Latch (WEL) bit indicates the status of
the “write enable” latch. When set to a “1”, the latch is set,
when set to a “0”, the latch is reset.

The Block Protect (BP0 and BP1) bits are nonvolatile
and allow the user to select one of four levels of protec­tion. The X25021 is divided into four 1024-bit segments.
One, two, or all four of the segments may be protected.
That is, the user may read the segments but will be
unable to alter (write) data within the selected segments.
The partitioning is controlled as illustrated below.

Status Register Bits Array Addresses

BP1 BP0 Protected

0 0 None
0 1 $C0–$FF
1 0 $80–$FF
1 1 $00–$FF

6615 PGM T03

X25021

4

Clock and Data Timing

Data input on the SI line is latched on the falling edge of
SCK. Data is output on the SO line by the rising edge of
SCK.

Read Sequence

When reading from the E2PROM memory array, CS is
first pulled LOW to select the device. The 8-bit READ
instruction is transmitted to the X25021, followed by the
8-bit address. After the READ opcode and address are
sent, the data stored in the memory at the selected
address is shifted out on the SO line. The data stored
in memory at the next address can be read sequentially
by continuing to provide clock pulses. The address is
automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address is reached ($FF) the address counter rolls
over to address $00 allowing the read cycle to be
continued indefinitely. The read operation is termi­nated by taking CS HIGH. Refer to the read E2PROM
array operation sequence illustrated in Figure 1.

To read the status register, the CS line is first pulled
LOW to select the device followed by the 8-bit RDSR
instruction. After the read status register opcode is
sent, the contents of the status register are shifted out
on the SO line. Figure 2 illustrates the read status
register sequence.

Write Sequence

Prior to any attempt to write data into the X25021, the
“write enable” latch must first be set by issuing the
WREN instruction (See Figure 3). CS is first taken LOW,
then the WREN instruction is clocked into the X25021.
After all eight bits of the instruction are transmitted, CS
must then be taken HIGH. If the user continues the write
operation without taking CS HIGH after issuing the
WREN instruction, the write operation will be ignored.

To write data to the E2PROM memory array, the user
issues the WRITE instruction, followed by the address
and then the data to be written. This is minimally a
twenty-four clock operation. CS must go LOW and
remain LOW for the duration of the operation. The host
may continue to write up to 4 bytes of data to the X25021.
The only restriction is the 4 bytes must reside on the
same page. If the address counter reaches the end of
the page and the clock continues, the counter will “roll
over” to the first address of the page and overwrite any
data that may have been written.

For the write operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of
data byte N is clocked in. If it is brought HIGH at any other
time the write operation will not be completed. Refer to
Figures 4 and 5 below for a detailed illustration of the
write sequences and time frames in which CS going
HIGH are valid.

To write to the status register, the WRSR instruction is
followed by the data to be written. Data bits 0, 1, 4, 5, 6
and 7 must be “0”. Figure 6 illustrates this sequence.

While the write is in progress following a status register
or E2PROM write sequence, the status register may be
read to check the WIP bit. During this time the WIP bit will
be HIGH.

Hold Operation

The HOLD input should be HIGH (at VIH) under normal
operation. If a data transfer is to be interrupted HOLD
can be pulled LOW to suspend the transfer until it can be
resumed. The only restriction is the SCK input must be
HIGH when HOLD is first pulled LOW and SCK must
also be HIGH when HOLD is released.

The HOLD input may be tied HIGH either directly to V

CC

or tied to VCC through a resistor.

X25021

5

Figure 1. Read E2PROM Array Operation Sequence

Figure 2. Read Status Register Operation Sequence

Operational Notes

The X25021 powers-up in the following state:

• The device is in the low power standby state.

• A HIGH to LOW transition on CS is required to
enter an active state and receive an instruction.

• SO pin is high impedance.

• The “write enable” latch is reset.

Data Protection

The following circuitry has been included to prevent
inadvertent writes:

• The “write enable” latch is reset upon power-up.

• A WREN instruction must be issued to set the “write
enable” latch.

• CS must come HIGH at the proper clock count in
order to start a write cycle.

01234567891011121314

76543210

DATA OUT

CS

SCK

SI

SO

MSB

HIGH IMPEDANCE

INSTRUCTION

6615 ILL F13

012345678910111213141516171819202122

6615 FHD F14

76543210

DATA OUT

CS

SCK

SI

SO

MSB

HIGH IMPEDANCE

INSTRUCTION BYTE ADDRESS

76543210

X25021

6

Figure 3. Write Enable Latch Sequence

Figure 4. Byte Write Operation Sequence

01234567891011121314151617181920212223

6615 FHD F06.1

CS

SCK

SI

SO

HIGH IMPEDANCE

INSTRUCTION BYTE ADDRESS

DATA BYTE

76543210

76543210

01234567

6615 ILL F05.1

CS

SI

SCK

HIGH IMPEDANCE

SO

X25021

7

Figure 5. Page Write Operation Sequence

Figure 6. Write Status Register Operation Sequence

0123456789

CS

SCK

SI

SO

HIGH IMPEDANCE

INSTRUCTION

DATA BYTE

76543210

10 11 12 13 14 15

6615 ILL F08

24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

SCK

SI

CS

01234567891011121314151617181920212223

6615 FHD F07

SCK

SI

INSTRUCTION BYTE ADDRESS

DATA BYTE 1

76543210

CS

40 41 42 43 44 45 46 47

DATA BYTE 2

76543210

DATA BYTE 3

76543210

DATA BYTE 4

76543210

76543210

X25021

8

*COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
listed in the operational sections of this specification is not
implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS*

Temperature under Bias .................. –65°C to +135°C

Storage Temperature ....................... –65°C to +150°C

Voltage on any Pin with Respect to V

SS

.........

–1V to +7V

D.C. Output Current ............................................. 5mA

Lead Temperature

(Soldering, 10 seconds).............................. 300°C

CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V.

Symbol Test Max. Units Conditions

C

OUT

(2)

Output Capacitance (SO) 8 pF V

OUT

= 0V

C

IN

(2)

Input Capacitance (SCK, SI, CS, WP, HOLD)6 pF V

IN

= 0V

6615 PGM T09

RECOMMENDED OPERATING CONDITIONS

Temp Min. Max.

Commercial 0°C +70°C
Industrial –40°C +85°C

6615 PGM T05.1

Supply Voltage Limits

X25021 5V ±10%
X25021-3 3V to 5.5V
X25021-2.7 2.7 to 5.5V

6615 PGM T06

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Limits

Symbol Parameter Min. Max. Units Test Conditions

I

CC

VCC Supply Current (Active) 3 mA SCK = VCC x 0.1/VCC x 0.9 @ 1MHz,

SO = Open

I

SB

VCC Supply Current (Standby) 10 µA CS = V

CC, VIN

= VSS or VCC – 0.3V

I

LI

Input Leakage Current 10 µAVIN = VSS to V

CC

I

LO

Output Leakage Current 10 µAV

OUT

= VSS to V

CC

V

IL

(1)

Input LOW Voltage –0.5 V

CC

x 0.3 V

V

IH

(1)

Input HIGH Voltage V

CC

x 0.7 V

CC

+ 0.5 V

V

OL

Output LOW Voltage 0.4 V IOL = 2mA

V

OH

Output HIGH Voltage VCC – 0.8 V IOH = –1mA

6615 PGM T07.2

POWER-UP TIMING

Symbol Parameter Min. Max. Units

t

PUR

(2)

Power-up to Read Operation 1 ms

t

PUW

(2)

Power-up to Write Operation 5 ms

6615 PGM T08

Notes: (1) VIL min. and VIH max. are for reference only and are not tested.

(2) This parameter is periodically sampled and not 100% tested.

X25021

9

EQUIVALENT A.C. LOAD CIRCUIT AT 5V V

CC

A.C. TEST CONDITIONS

Input Pulse Levels VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times 10ns

Input and Output Timing Level VCC x 0.5

6615 PGM T10

6615 FHD F12

A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Data Input Timing

Symbol Parameter Min. Max. Units

f

SCK

Clock Frequency 0 1 MHz

t

CYC

Cycle Time 1000 ns

t

LEAD

CS Lead Time 500 ns

t

LAG

CS Lag Time 500 ns

t

WH

Clock HIGH Time 400 ns

t

WL

Clock LOW Time 400 ns

t

SU

Data Setup Time 100 ns

t

H

Data Hold Time 100 ns

t

RI

Data In Rise Time 2 µs

t

FI

Data In Fall Time 2 µs

t

HD

HOLD Setup Time 200 ns

t

CD

HOLD Hold Time 200 ns

t

CS

CS Deselect Time 500 ns

t

WC

(4)

Write Cycle Time 10 ms

6615 PGM T11.1

Data Output Timing

Symbol Parameter Min. Max. Units

f

SCK

Clock Frequency 0 1 MHz

t

DIS

Output Disable Time 500 ns

t

V

Output Valid from Clock LOW 400 ns

t

HO

Output Hold Time 0 ns

t

RO

(3)

Output Rise Time 300 ns

t

FO

(3)

Output Fall Time 300 ns

t

LZ

HOLD HIGH to Output in Low Z 100 ns

t

HZ

HOLD LOW to Output in High Z 100 ns

6615 PGM T12.1

Notes: (3) This parameter is periodically sampled and not 100% tested.

(4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal

nonvolatile write cycle.

5V

2.16KΩ

3.07KΩ

OUTPUT

100pF

X25021

10

Serial Output Timing

Serial Input Timing

SCK

CS

SO

SI

MSB OUT MSB–1 OUT LSB OUT

ADDR

LSB IN

t

CYC

t

V

t

HO

t

WL

t

WH

t

DIS

6615 FHD F09

t

LAG

SCK

CS

SI

SO

MSB IN

t

SU

t

RI

t

LAG

6615 FHD F10.1

t

LEAD

t

H

LSB IN

t

CS

t

FI

HIGH IMPEDANCE

X25021

11

Hold Timing

6615 FHD F11

SCK

CS

SI

SO

t

HD

t

LZ

HOLD

t

CD

t

HZ

t

CD

t

HD

SYMBOL TABLE

WAVEFORM

INPUTS

OUTPUTS

Must be
steady

Will be
steady

May change
from LOW
to HIGH

Will change
from LOW
to HIGH

May change
from HIGH
to LOW

Will change
from HIGH
to LOW

Don’t Care:
Changes
Allowed

Changing:
State Not
Known

N/A

Center Line
is High
Impedance

X25021

12

PACKAGING INFORMATION

3926 FHD F01

NOTE:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH

0.020 (0.51)

0.016 (0.41)

0.150 (3.81)

0.125 (3.18)

0.110 (2.79)

0.090 (2.29)

0.430 (10.92)

0.360 (9.14)

0.300

(7.62) REF.

PIN 1 INDEX

0.145 (3.68)

0.128 (3.25)

0.025 (0.64)

0.015 (0.38)

PIN 1

SEATING

PLANE

0.065 (1.65)

0.045 (1.14)

0.260 (6.60)

0.240 (6.10)

0.060 (1.52)

0.020 (0.51)

TYP. 0.010 (0.25)

0°

15°

8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P

HALF SHOULDER WIDTH ON

ALL END PINS OPTIONAL

0.015 (0.38)
MAX.

0.325 (8.25)

0.300 (7.62)

X25021

13

PACKAGING INFORMATION

0.150 (3.80)

0.158 (4.00)

0.228 (5.80)

0.244 (6.20)

0.014 (0.35)

0.019 (0.49)

PIN 1

PIN 1 INDEX

0.010 (0.25)

0.020 (0.50)

0.050 (1.27)

0.188 (4.78)

0.197 (5.00)

0.004 (0.19)

0.010 (0.25)

0.053 (1.35)

0.069 (1.75)

(4X) 7°

0.016 (0.410)

0.037 (0.937)

0.0075 (0.19)

0.010 (0.25)

0° – 8°

X 45°

3926 FHD F22.1

8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

0.250"

0.050" TYPICAL

0.050"
TYPICAL

0.030"

TYPICAL

8 PLACES

FOOTPRINT

X25021

14

X25021 P T -V

Device

ORDERING INFORMATION

VCC Limits

Blank = 5V ±10%
3 = 3V to 5.5V

2.7V = 2.7V to 5.5V

Temperature Range

Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C

Package

P = 8-Lead Plastic DIP
S = 8-Lead SOIC

Blank = 8-Lead SOIC
P = 8-Lead Plastic DIP

Blank = 5V ±10%, 0°C to +70°C
I = 5V ±10%, –40°C to +85°C
D = 3V to 5.5V, 0°C to +70°C
E = 3V to 5.5V, –40°C to +85°C
F = 2.7V to 5.5V, 0°C to +70°C
G = 2.7V to 5.5V, –40°C to + 85°C

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are
implied.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and
additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and back-up features to prevent such an occurence.

Xicor's products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.

X25021 X

X

Part Mark Convention