Datasheet X24C00MI, X24C00SM Datasheet (XICOR)

X24C00

1

128 Bit X24C00 16 x 8 Bit

Serial E

2

PROM

© Xicor, Inc. 1991, 1995, 1996 Patents Pending Characteristics subject to change without notice
3836-1.5 6/10/96 T2/C1/D0 NS

DESCRIPTION

The X24C00 is a CMOS 128 bit serial E2PROM, inter­nally organized as 16 x 8. The X24C00 features a serial
interface and software protocol allowing operation on a
simple two wire bus.

Xicor E2PROMs are designed and tested for applica­tions requiring extended endurance. Inherent data re­tention is greater than 100 years.

The X24C00 is fabricated with Xicor’s Advanced CMOS
Floating Gate technology.

FEATURES

• 2.7V to 5.5V Power Supply

• 128 Bit Serial E

2

PROM

• Low Power CMOS

—Active Current Less Than 3mA
—Standby Current Less Than 50µA

• Internally Organized 16 x 8

• 2 Wire Serial Interface

—Bidirectional Data Transfer Protocol

• Byte Mode Write

• Self Timed Write Cycle

—Typical Write Cycle Time of 5ms

• Push/Pull Output

• High Reliability

—Endurance: 100,000 Cycles
—Data Retention: 100 Years

• Available Packages

—8-Lead MSOP
—8-Lead PDIP
—8-Lead SOIC

FUNCTIONAL DIAGRAM

CONTROL

LOGIC

INPUT/
OUTPUT
BUFFER

SCL

SDA

COMMAND/ADDRESS

REGISTER

SHIFT REGISTER

MEMORY ARRA Y

3836 FHD F01

PIN CONFIGURATION

APPLICATION NOTES

AVAILABLE

AN4 • AN12 • AN22 • AN26 • AN32

V

CC

NC
SCL
SDA

3836 FHD F02.1

NC
NC

NC

V

SS

1
2
3
4

8
7
6
5

X24C00

MSOP/DIP/SOIC

2

X24C00

PIN DESCRIPTIONS
Serial Clock (SCL)

The SCL input is used to clock all data into and out of the
device.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into and
out of the device. It is a push/pull output and does not
require the use of a pull-up resistor.

PIN NAMES

Symbol Description

NC No Connect
V

SS

Ground

V

CC

Supply Voltage
SDA Serial Data
SCL Serial Clock

3836 PGM T01

DEVICE OPERATION

The X24C00 supports a bidirectional bus oriented pro­tocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as
the receiver. The device controlling the transfer is a
master and the device being controlled is the slave. The
master will always initiate data transfers and provide the
clock for both transmit and receive operations. There­fore, the X24C00 will be considered a slave in all
applications.

Clock and Data Conventions

Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are re­served for indicating start and stop conditions. Refer to
Figures 1 and 2.

Start Condition

All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X24C00 continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met.

A start may be issued to terminate the input of a control
word or the input of data to be written. This will reset the
device and leave it ready to begin a new read or write
command. Because of the push/pull output, a start
cannot be generated while the part is outputting data.
Starts are also inhibited while a write is in progress.

Stop Condition

The stop condition is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is used to reset
the device during a command or data input sequence
and will leave the device in the standby mode. As with
starts, stops are inhibited when outputting data and
while a write is in progress.

Write Operation

The byte write operation is initiated with a start condition.
The start condition is followed by an eight bit control byte
which consists of a two bit write command (0,1), four
address bits, and two “don’t care” bits (Figure 3).

X24C00

3

Figure 1. Data Validity

SCL

SDA

DATA STABLE DATA

CHANGE

3836 FHD F03

Figure 2. Definition of Start and Stop Conditions

SCL

SDA

START CONDITION STOP CONDITION

3836 FHD F04

Figure 3. Control Byte

START

C1

C2 A3 A2 A1 A0 XX XX

3836 FHD F05

4

X24C00

Read Operation

The byte read operation is initiated with a start condition.
The start condition is followed by an eight-bit control byte
which consists of a two-bit read command (1,0), four
address bits, and two “don’t care” bits. After receipt of
the control byte the X24C00 will enter the read mode and
transfer data into the shift register from the array. This
data is shifted out of the device on the next eight SCL
clocks. At the end of the read, all counters are reset and
the X24C00 will enter the standby mode. As with a write,
the read operation can be interrupted by a start or stop
condition while the command or address is being clocked
in. While clocking data out, starts or stops cannot be
generated.

During the second don’t care clock cycle, starts and
stops are ignored. The master must free the bus prior to
the end of this clock cycle to allow the X24C00 to begin
outputting data (Figures 5 and 6).

After receipt of the control byte, the X24C00 will enter
the write mode and await the data to be written. This data
is shifted into the device on the next eight SCL clocks.
Once eight clocks have been received, the data in the
shift register will be written into the memory array. While
the write is in progress the X24C00 will not respond to
any inputs. At any time prior to clocking in the last data
bit, a stop command or a new start command will
terminate the operation. If a start command is given, the
X24C00 will reset all counters and will prepare to clock
in the next control byte. If a stop command is given, the
X24C00 will reset all counters and await the next start
command.

At the end of the write the X24C00 will automatically
reset all counters and enter the standby mode.
(Figure 4).

Figure 4. Write Sequence

3836 FHD F06

START

0

1 A3 A2 A1 A0 XX XX D7 D6 D5 D4 D3 D2 D1 D0

Figure 5. Read Sequence

START

1

0 A3 A2 A1 A0 XX XX D7 D6 D5 D4 D3 D2 D1 D0

3836 FHD F07

6781

SDA IN

SCK

SDA OUT

A0 XX XX

D7 D6

3836 FHD F08

WAVEFORM

INPUTS

OUTPUTS

Must be
steady

Will be
steady

May change
from LOW
to HIGH

Will change
from LOW
to HIGH

May change
from HIGH
to LOW

Will change
from HIGH
to LOW

Don’t Care:
Changes
Allowed

Changing:
State Not
Known

N/A

Center Line
is High
Impedance

SYMBOL TABLE

Figure 6. Read Cycle Timing

X24C00

5

*COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS*

Temperature under Bias

X24C00...................................... –65°C to +135°C

Storage Temperature ....................... –65°C to +150°C

Voltage on any Pin with

Respect to V

SS

............................................ –1V to +7V

D.C. Output Current ............................................. 5mA

Lead Temperature

(Soldering, 10 seconds).............................. 300°C

RECOMMENDED OPERATING CONDITIONS

Temperature Min. Max.

Commercial 0°C +70°C
Industrial –40°C +85°C
Military –55°C +125°C

3836 PGM T02.1

D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)

Limits

Symbol Parameter Min. Max. Units Test Conditions

l

CC1

VCC Supply Current Read 1 mA SCL = VCC x 0.1/VCC x 0.9

I

CC2

VCC Supply Current Write 3 Levels @ 1MHz, SDA = Open

I

SB1

V

CC

Standby Current 100 µA SCL = SDA = V

CC

VCC = 5V ±10%

I

SB2

VCC Standby Current 50 µA SCL = SDA = V

CC

VCC = 2.7V

I

LI

Input Leakage Current 10 µAV

IN

= VSS to V

CC

I

LO

Output Leakage Current 10 µAV

OUT

= VSS to V

CC

V

lL

(1)

Input LOW Voltage –1 VCC x 0.3 V

V

IH

(1)

Input HIGH Voltage VCC x 0.7 VCC + 0.5 V

V

OL

Output LOW Voltage 0.4 V IOL = 2.1mA

V

OH

Output HIGH Voltage VCC – 0.8 V IOH = 1mA

3841 PGM T04.3

CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V

Symbol Parameter Max. Units Test Conditions

C

I/O

(2)

Input/Output Capacitance (SDA) 8 pF V

I/O

= 0V

C

IN

(2)

Input Capacitance (SCL) 6 pF V

IN

= 0V

3836 PGM T05.1

Notes: (1) VIL min. and VIH max. are for reference only and are not tested.

(2) This parameter is periodically sampled and not 100% tested.

Supply Voltage Limits

X24C00 5V ±10%
X24C00-3 3V to 5.5V
X24C00-2.7 2.7V to 5.5V

3836 PGM T03.1

6

X24C00

Symbol Parameter Min. Max. Units

f

SCL

SCL Clock Frequency 0 1 MHz

t

AA

SCL LOW to SDA Data Out Valid 350 ns

t

BUF

Time the Bus Must Be Free Before a 500 ns
New Transmission Can Start

t

HD:STA

Start Condition Hold Time 250 ns

t

LOW

Clock LOW Period 500 ns

t

HIGH

Clock HIGH Period 500 ns

t

SU:STA

Start Condition Setup Time 250 ns

t

HD:DAT

Data In Hold Time 0 µs

t

SU:DAT

Data in Setup Time 250 ns

t

R

SDA and SCL Rise Time 1 µs

t

F

SDA and SCL Fall Time 300 ns

t

SU:STO

Stop Condition Setup Time 250 ns

t

DH

Data Out Hold Time 50 ns

3836 PGM T07.1

A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Read & Write Cycle Limits

POWER-UP TIMING

Symbol Parameter Max. Units

t

PUR

(3)

Power-up to Read Operation 2 ms

t

PUW

(3)

Power-up to Write Operation 5 ms

3836 PGM T08

A.C. CONDITIONS OF TEST

Input Pulse Levels VCC x 0.1 to VCC x 0.9
Input Rise and

Fall Times 10ns
Input and Output

Timing Levels VCC x 0.5

3836 PGM T06.1

EQUIVALENT A.C. LOAD CIRCUIT

Note: (3) t

PUR

and t

PUW

are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters

are periodically sampled and not 100% tested.

3836 FHD F09.2

5V

2.16KΩ

100pF

OUTPUT

3.07KΩ

X24C00

7

Bus Timing

t

SU:STA

t

HD:STAtHD:DAT

t

SU:DAT

t

LOW

t

SU:STO

t

R

t

BUF

SCL

SDA IN

SDA OUT

t

DH

t

AA

t

F

t

HIGH

3836 FHD F10

WRITE CYCLE LIMITS

Symbol Parameter Min. Max. Units

t

WR

(4)

Write Cycle Time 5 ms

3836 PGM T09

Write Cycle Timing

3836 ILL F11.1

SDA

t

WR

SCL

D0

START
CONDTION

X24C00
ADDRESS

Note: (4) The write cycle time is the time from the initiation of a write sequence to the end of the internal erase/program cycle. During the

write cycle, the X24C00 bus interface circuits are disabled, SDA is high impedance, and the device does not respond to start
conditions.

8

X24C00

PACKAGING INFORMATION

0.118 ± 0.002
(3.00 ± 0.05)

0.040 ± 0.002
(1.02 ± 0.05)

0.150 (3.81)
REF.

0.193 (4.90)
REF.

0.030 (0.76)

0.036 (0.91)

0.032 (0.81)

0.007 (0.18)

0.005 (0.13)

0.008 (0.20)

0.004 (0.10)

0.0216 (0.55)

7° TYP

R 0.014 (0.36)

0.118 ± 0.002
(3.00 ± 0.05)

0.012 + 0.006 / -0.002
(0.30 + 0.15 / -0.05)

0.0256 (0.65) TYP

8-LEAD MINIATURE SMALL OUTLINE GULL WING PACKAGE TYPE M

NOTE:

1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)

3926 ILL F49

X24C00

9

3926 FHD F01

NOTE:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH

0.020 (0.51)

0.016 (0.41)

0.150 (3.81)

0.125 (3.18)

0.110 (2.79)

0.090 (2.29)

0.430 (10.92)

0.360 (9.14)

0.300

(7.62) REF.

PIN 1 INDEX

0.145 (3.68)

0.128 (3.25)

0.025 (0.64)

0.015 (0.38)

PIN 1

SEATING

PLANE

0.065 (1.65)

0.045 (1.14)

0.260 (6.60)

0.240 (6.10)

0.060 (1.52)

0.020 (0.51)

TYP. 0.010 (0.25)

0°

15°

8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P

HALF SHOULDER WIDTH ON

ALL END PINS OPTIONAL

0.015 (0.38)
MAX.

0.325 (8.25)

0.300 (7.62)

PACKAGING INFORMATION

10

X24C00

PACKAGING INFORMATION

0.150 (3.80)

0.158 (4.00)

0.228 (5.80)

0.244 (6.20)

0.014 (0.35)

0.019 (0.49)

PIN 1

PIN 1 INDEX

0.010 (0.25)

0.020 (0.50)

0.050 (1.27)

0.188 (4.78)

0.197 (5.00)

0.004 (0.19)

0.010 (0.25)

0.053 (1.35)

0.069 (1.75)

(4X) 7°

0.016 (0.410)

0.037 (0.937)

0.0075 (0.19)

0.010 (0.25)

0° – 8°

X 45°

3926 FHD F22.1

8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

0.250"

0.050" TYPICAL

0.050"
TYPICAL

0.030"

TYPICAL

8 PLACES

FOOTPRINT

X24C00

11

Blank = 8-Lead SOIC
P = 8-Lead Plastic DIP

Blank = 4.5V to 5.5V, 0°C to +70°C
I = 4.5V to 5.5V, –40°C to +85°C
M = 4.5V to 5.5V, –55°C to +85°C
D = 3V to 5.5V, 0°C to +70°C
E = 3V to 5.5V, –40°C to +85°C
F = 2.7V to 5.5V, 0°C to +70°C
G = 2.7V to 5.5V, –40°C to +85°C

ORDERING INFORMATION

Part Mark Convention

Device

X24C00 X X -X

VCC Range

Blank = 5V ±10%
3 = 3V to 5.5V

2.7 = 2.7V to 5.5V

Temperature Range

Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C

Package

M = 8-Lead MSOP
P = 8-Lead Plastic DIP
S = 8-Lead SOIC

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes
no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to
discontinue production and change specifications and prices at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.

US. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976;
4,980,859; 5,012,132; 5,003,197; 5,023,694. Foreign patents and additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence.

Xicor’s products are not authorized for use as critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure
of the life support device or system, or to affect its satety or effectiveness.

X24C00 X

X