Datasheet X24641S8I-2,5, X24641S8I-1,8, X24641S8I, X24641S8-2,5, X24641S8-1,8 Datasheet (XICOR)
...Page 1
400 KHz 2-Wire Serial E
2
PROM
64K
8K x 8 Bit
Xicor, 1995, 1996 Patents Pending Characteristics subject to change without notice
7026 3/27/97 T0/C0/D0 SH
1
X24641
FUNCTIONAL DIAGRAM
FEATURES
•
1.8V to 3.6V, 2.5V to 5.5V and 4.5V to 5.5V
Power Supply Operation
•
Low Power CMOS
—Active Read Current Less Than 1mA
—Active Write Current Less Than 3mA
—Standby Current Less Than 1 µ A
•
400KHz Fast Mode 2-Wire Serial Interface
—Down to 1.8V
—Schmitt Trigger Input Noise Suppression
—Output Slope Control for Ground Bounce
Noise Elimination
•
Internally Organized 8K x 8
•
32 Byte Page Write Mode
—Minimizes T otal Write Time Per Byte
•
Hardware Write Protect
•
Bidirectional Data Transfer Protocol
•
Self-Timed Write Cycle
—Typical Write Cycle Time of 5ms
•
High Reliability
—Endurance: 1,000,000 Cycles
—Data Retention: 100 Years
•
8-Lead SOIC
DESCRIPTION
The X24641 is a CMOS Serial E
2
PROM Memory,
internally organized 8K x 8. The device features a
serial interface and software protocol allowing operation on a simple two wire bus. The bus operates at
400KHz all the way down to 1.8V.
Three device select inputs (S
0
–S
2
) allow up to eight
devices to share a common two wire bus .
Hardware Write Protection is provided through a Write
Protect (WP) input pin on the X24641. When the WP
pin is HIGH, the upper quadrant of the Serial E
2
PROM
array is protected against any nonvolatile write
attempts.
Xicor Serial E
2
PROM Memories are designed and
tested for applications requiring extended endurance.
Inherent data retention is greater than 100 years.
SERIAL E2PROM DATA
AND ADDRESS (SDA)
SCL
S2
S1
S0
WP
COMMAND
DECODE
AND
CONTROL
LOGIC
DEVICE
SELECT
LOGIC
WRITE
PROTECT
LOGIC
PAGE
DECODE
LOGIC
DATA REGISTER
Y DECODE LOGIC
E
2
PROM
WRITE VOLTAGE
CONTROL
7026 FM 01
ARRAY
8K x 8
Page 2
X24641
2
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Pullup resistor selection graph at the end of this data
sheet.
Device Select (S
0
, S
1
, S
2
)
The device select inputs (S
0
, S
1
, S
2
) are used to set
the first three bits of the 8-bit slave address. This
allows up to eight devices to share a common bus.
These inputs can be static or actively driven. If used
statically they must be tied to V
SS
or V
CC
as appropriate. If actively driven, they must be driven with
CMOS levels .
Write Protect (WP)
The Write Protect input controls the Hardware Write
Protect feature. When held LOW, Hardware Write
Protection is disabled and the device can be written
normally. When this input is held HIGH, Write Protection is enabled, and nonvolatile writes are disabled to
the upper quadrant of the E
2
PROM array.
PIN NAMES
7026 FRM T01
PIN CONFIGURATION
Symbol Description
S
0
, S
1
, S
2
Device Select Inputs
SDA Serial Data
SCL Serial Clock
WP Write Protect
V
SS
Ground
V
CC
Supply Voltage
V
CC
WP
SCL
SDA
S
0
S
1
S
2
VSS
1
2
3
4
8
7
6
5
X24641
8-LEAD SOIC
7026 FM 02
Page 3
X24641
3
DEVICE OPERATION
The device supports a bidirectional, bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter, and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers, and provide the clock for both transmit and
receive operations. Therefore, the device will be
considered a slave in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 1 and 2.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met.
SCL
SDA
DATA STABLE DATA
CHANGE
7026 FM 03
SCL
SDA
START BIT STOP BIT
7026 FM 04
Figure 1. Data Validity
Figure 2. Definition of Start and Stop
Page 4
X24641
4
Figure 3. Acknowledge Response From Receiver
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the device into the standby power mode after a
read sequence. A stop condition can only be issued
after the transmitting device has released the bus .
Acknowledge
Acknowledge is a software con v ention used to indicate
successful data transfer. The transmitting device,
either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Ref er to Figure 3.
The device will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a Write Operation have been
selected, the device will respond with an acknowledge
after the receipt of each subsequent byte.
In the read mode the device will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. If an acknowledge is not
detected, the device will terminate further data transmissions. The master must then issue a stop condition
to return the device to the standby power mode and
place the device into a known state.
SCL FROM
MASTER
DATA OUTPUT
FROM
TRANSMITTER
1
8 9
DATA
OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
7026 FM 05
Page 5
X24641
5
Figure 4. Device Addressing
1
S1S0R/W
DEVICE
SELECT
0 1 0 S
2
DEVICE TYPE
IDENTIFIER
SLAVE ADDRESS BYTE
D7 D2 D1D6 D5 D4 D3
DATA BYTE
A2 A1 A0
A5
LOW ORDER ADDRESS
A4 A3
ADDRESS BYTE 0
0 A10 A9 A80
HIGH ORDER ADDRESS
A11
ADDRESS BYTE 1
0
A7 A6
D0
7026 FM 06
A12
DEVICE ADDRESSING
Following a start condition, the master must output the
address of the slave it is accessing. The first four bits
of the Slave Address Byte are the de vice type identifier
bits. These must equal “1010”. The next 3 bits are the
device select bits S
0
, S
1
, and S
2
. This allows up to 8
devices to share a single bus. These bits are
compared to the S
0
, S
1
, and S
2
device select input
pins. The last bit of the Slave Address Byte defines the
operation to be performed. When the R/W bit is a one,
then a Read Operation is selected. When it is zero
then a Write Operation is selected. Refer to figure 4.
After loading the Slave Address Byte from the SDA
bus, the device compares the device type bits with the
value “1010” and the device select bits with the status
of the device select input pins. If the compare is not
successful, no acknowledge is output during the ninth
clock cycle and the device returns to the standby mode.
The byte address is either supplied by the master or
obtained from an internal counter, depending on the
operation. When required, the master must supply the
two Address Bytes as shown in figure 4.
The internal organization of the E
2
PROM array is 256
pages by 32 bytes per page. The page address is
partially contained in the Address Byte 1 and par tially in
bits 7 through 5 of the Address Byte 0. The specific byte
address is contained in bits 4 through 0 of the Address
Byte 0. Ref er to figure 4.
Page 6
X24641
6
Figure 5. Page Write Sequence
WRITE OPERATIONS
Byte Write
For a Byte Write Operation, the device requires the
Slave Address Byte, the Word Address Byte 1, and
the Word Address Byte 0, which gives the master
access to any one of the bytes in the array. Upon
receipt of the Word Address Byte 0, the device
responds with an acknowledge, and waits for the first
eight bits of data. After receiving the 8 bits of the data
byte, the device again responds with an acknowledge. The master then terminates the transfer by
generating a stop condition, at which time the device
begins the internal write cycle to the nonvolatile
memory. While the internal write cycle is in progress
the device inputs are disabled and the device will not
respond to any requests from the master. The SDA
pin is at high impedance. See figure 4.
Page Write Operation
The device executes a thirty-two byte Page Write
Operation. For a Page Write Operation, the device
requires the Slave Address Byte, Address Byte 1, and
Address Byte 0. Address Byte 0 must contain the first
byte of the page to be written. Upon receipt of Address
Byte 0, the device responds with an ackno wledge, and
waits for the first eight bits of data. After receiving the 8
bits of the first data byte, the device again responds
with an acknowledge. The device will respond with an
acknowledge after the receipt of each of 31 more
bytes. Each time the byte address is internally incremented by one, while page address remains constant.
When the counter reaches the end of the page, the
master terminates the data loading by issuing a stop
condition, which causes the device to begin the
nonvolatile write cycle. All inputs are disabled until
completion of the nonvolatile write cycle. The SDA pin
is at high impedance. Refer to figure 5 for the address,
acknowledge, and data transf er sequence .
S
T
A
R
T
SLAVE
ADDRESS
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
7012 ILL F08.1
DATA
(1)
SIGNALS
FROM THE
MASTER
SDA BUS
SIGNALS
FROM THE
SLAVE
DATA
(32)
ADDRESS
BYTE 1
ADDRESS
BYTE 0
1 0 1 0 0
S P
SIGNALS
FROMTHE
MASTER
SDA BUS
SIGNALS
FROMTHE
SLAVE
S
T
A
R
T
SLAVE
ADDRESS
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
WORDADDRESS
BYTE 1
DATA
1 0 1 0 0
WORDADDRESS
BYTE 0
S P
7026 FM 07
SIGNALS
FROMTHE
MASTER
SDA BUS
SIGNALS
FROMTHE
SLAVE
S
T
A
R
T
SLAVE
ADDRESS
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
WORDADDRESS
BYTE 1
DATA
1 0 1 0 0
WORDADDRESS
BYTE 0
S P
7026 FM 07
Figure 4. Byte Write Sequence
Page 7
X24641
7
Acknowledge Polling
The maximum write cycle time can be significantly
reduced using Acknowledge Polling. To initiate
Acknowledge Polling, the master issues a star t condition followed by the Slave Address Byte for a write or
read operation. If the device is still busy with the
nonvolatile write cycle, then no ACK will be returned. If
the device has completed the nonvolatile write operation, an ACK will be returned and the host can then
proceed with the read or write operation. Refer to
figure 6.
BYTE LOAD COMPLETED
BY ISSUING STOP.
ENTER ACK POLLING
ISSUE
START
ISSUE SLAVE
ADDRESS BYTE
(READ OR PROGRAM)
ACK
RETURNED?
NONVOLATILE
WRITE
CYCLE COMPLETE.
CONTINUE
SEQUENCE?
CONTINUE NORMAL
READ ORPROGRAM
COMMAND SEQUENCE
PROCEED
ISSUE STOP
NO
YES
YES
ISSUE STOP
NO
7026 FM 09
READ OPERATIONS
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads,
Random Reads, and Sequential Reads.
Current Address Read
Internally, the device contains an address counter that
maintains the address of the last byte read or written,
incremented by one. After a read operation from the
last address in the array, the counter will “roll over” to
the first address in the array. After a write operation to
the last address in a given page, the counter will “roll
over” to the first address of the same page.
Upon receipt of the Slave Address Byte with the R/W
bit set to one, the device issues an acknowledge and
then transmits the byte at the current address. The
master terminates the read operation when it does not
respond with an acknowledge during the ninth clock
and then issues a stop condition. Refer to figure 7 for
the address, acknowledge, and data transfer
sequence.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
FROM THE
S
T
A
R
T
SLAVE
ADDRESS
S
T
O
P
A
C
K
DATA
SIGNALS
FROM THE
MASTER
SDA BUS
SIGNALS
SLAVE
1S P0 1 0 1
7026 FM 10
Figure 6. Acknowledge Polling Sequence
Figure 7. Current Address Read Sequence
Page 8
X24641
8
Random Read
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W
bit set to one, the
master must first perform a “Dummy” write operation.
The master issues the start condition and the Slave
Address Byte with the R/W bit low, receives an
acknowledge, then issues Address Byte 1, receives
another acknowledge, then issues Address Byte 0
containing the address of the byte to be read. After the
device acknowledges receipt of Address Byte 0, the
master issues another start condition and the Slave
Address Byte with the R/W
bit set to one. This is
followed b y an ac kno wledge and then eight bits of data
from the device. The master terminates the read operation by not responding with an acknowledge and then
issuing a stop condition. Refer to figure 8 for the
address, acknowledge, and data tr ansf er sequence.
The device will perform a similar operation called “Set
Current Address” if a stop is issued instead of the
second start shown in figure 9. The device will go into
standby mode after the stop and all bus activity will be
ignored until a start is detected. The effect of this operation is that the new address is loaded into the
address counter, b ut no data is output by the de vice .
The next Current Address Read operation will read
from the newly loaded address.
Sequential Read
Sequential reads can be initiated as either a current
address read or random read. The first byte is transmitted as with the other modes; however, the master
now responds with an acknowledge, indicating it
requires additional data. The device continues to
output data for each acknowledge received. The
master terminates the read operation by not
responding with an acknowledge and then issuing a
stop condition.
The data output is sequential, with the data from address
n followed by the data from address n + 1. The address
counter for read operations increments through all byte
addresses, allowing the entire memory contents to be
read during one operation. At the end of the address
space the counter “rolls over” to address 0000h and the
device continues to output data for each acknowledge
received. Refer to figure 9 for the acknowledge and data
transfer sequence.
SLAVE
ADDRESS
S
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
DATA
(1)
DATA
(2)
SIGNALS
FROM THE
MASTER
SDA BUS
SIGNALS
FROM THE
SLAVE
DATA
(n–1)
DATA
(n)
1 P
7026 FM 12
SIGNALS
FROMTHE
MASTER
SDA BUS
SIGNALS
FROMTHE
SLAVE
S
T
A
R
T
SLAVE
ADDRESS
S
T
O
P
A
C
K
A
C
K
A
C
K
ADDRESS
BYTE 1
SLAVE
ADDRESS
0
ADDRESS
BYTE 0
S
T
A
R
T
1
DATA
A
C
K
S PS1 0 1 0
7026 FM 11
Figure 8. Random Read Sequence
Figure 9. Sequential Read Sequence
Page 9
X24641
9
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias
X24641.......................................–65 ° C to +135 ° C
Storage Temperature........................–65 ° C to +150 ° C
Voltage on any Pin with
Respect to V
SS
....................................–1V to +7V
D.C. Output Current..............................................5mA
Lead Temperature
(Soldering, 10 seconds) ..............................300 ° C
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause per manent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
D.C. OPERATING CHARACTERISTICS
7026 FRM T06.1
CAPACITANCE T
A
= +25 ° C, f = 1MHz, V
CC
= 5V
7026 FRM T07
Notes: (1) Must perform a stop command prior to measurement.
(2) V
IL
min. and V
IH
max. are f or ref erence only and are not 100% tested.
(3) This parameter is periodically sampled and not 100% tested.
Limits
Symbol Parameter Min. Max. Units Test Conditions
I
CC1
V
CC
Supply Current (Read) 1 mA SCL = VCC X 0.1/VCC X 0.9 Levels
@ 400KHz, SDA = Open, All Other
Inputs =
V
SS
or VCC – 0.3V
I
CC2
VCC Supply Current
(Write)
3 mA
I
SB1
(1)
VCC Standby Current 3 µA SCL = SDA = VCC – 0.3V,
All Other Inputs =
V
SS
or VCC – 0.3V,
V
CC
= 5V ± 10%
I
SB2
(1)
VCC Standby Current 1 µA SCL = SDA = VCC – 0.1V,
All Other Inputs =
V
SS
or VCC – 0.1V,
V
CC
= 1.8V
I
LI
Input Leakage Current 10 µA VIN = VSS to V
CC
I
LO
Output Leakage Current 10 µA V
OUT
= VSS to V
CC
V
lL
(2)
Input LOW Voltage –0.5 VCC x 0.3 V
V
IH
(2)
Input HIGH Voltage VCC x 0.7 VCC + 0.5 V
V
OL
Output LOW Voltage 0.4 V IOL = 3mA
V
hys
(3)
Hysteresis of Schmitt
Trigger Inputs
V
CC
x 0.05 V
Symbol Parameter Max. Units Test Conditions
C
I/O
(3)
Input/Output Capacitance (SDA) 8 pF V
I/O
= 0V
C
IN
(3)
Input Capacitance (S0, S1, S2, SCL,WP) 6 pF VIN = 0V
RECOMMENDED OPERATING CONDITIONS
7026 FRM T04
Temperature Min. Max.
Commercial 0°C +70°C
Industrial –40°C +85°C
7026 FRM T05
Supply Voltage Limits
X24641 4.5V to 5.5V
X24641–2.5 2.5V to 5.5V
X24641–1.8 1.8V to 3.6V
Page 10
X24641
10
A.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Read & Program Cycle Limits
7026 FRM T09
POWER-UP TIMING
(4)
7026 FRM T10
Notes: (4) t
PUR
and t
PUW
are the delays required from the time VCC is stable until the specified operation can be initiated. These par ameters
are periodically sampled and not 100% tested.
(5) Cb = total capacitance of one bus line in pF
(6) tAA = 1.1µs Max below VCC = 2.5V.
Symbol Parameter Min. Max. Units
f
SCL
SCL Clock Frequency 0 400 KHz
T
I
Noise Suppression Time
Constant at SCL, SDA Inputs
50 ns
t
AA
(6)
SCL LOW to SDA Data Out Valid 0.1 0.9 µs
t
BUF
Time the Bus Must Be Free Before a
New Transmission Can Start
1.2 µs
t
HD:STA
Start Condition Hold Time 0.6 µs
t
LOW
Clock LOW Period 1.2 µs
t
HIGH
Clock HIGH Period 0.6 µs
t
SU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
0.6 µs
t
HD:DAT
Data In Hold Time 0 µs
t
SU:DAT
Data In Setup Time 100 ns
t
R
SDA and SCL Rise Time
20+0.1XC
b
(5)
300 ns
t
F
SDA and SCL Fall Time
20+0.1XC
b
(5)
300 ns
t
SU:STO
Stop Condition Setup Time 0.6 µs
t
DH
Data Out Hold Time 50 ns
t
OF
Output Fall Time 20 + 0.1C
b
(5)
250 ns
Symbol Parameter Max. Units
t
PUR
Power-up to Read Operation 1 ms
t
PUW
Power-up to Write Operation 5 ms
A.C. CONDITIONS OF TEST
7026 FRM T08
Input Pulse Levels VCC x 0.1 to VCC x 0.9
Input Rise and
Fall Times 10ns
Input and Output
Timing Levels
V
CC
X 0.5
EQUIVALENT A.C. LOAD CIRCUIT
5V
1.53KΩ
100pF
OUTPUT
7026 FM 13
Page 11
X24641
11
SYMBOL TABLE
WAVEFORM INPUTS OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
7026 FM 17
The program cycle time is the time from a valid stop condition of a program sequence to the end of the inter nal
erase/program cycle. During the program cycle, the X24641 bus interface circuits are disabled, SDA is allowed to
remain HIGH, and the device does not respond to its slav e address.
Bus Timing
t
SU:STA
t
HD:STAtHD:DAT
t
SU:DAT
t
LOW
t
SU:STO
t
R
t
BUF
SCL
SDA IN
SDA OUT
t
DH
t
AA
t
F
t
HIGH
7026 FM 14
Program Cycle Limits
7026 FRM T11
Symbol Parameter Min. Typ.
(7)
Max. Units
T
WR
(8)
Program Cycle Time 5 10 ms
SCL
SDA 8th BIT
WORD n
ACK
t
WR
STOP
CONDITION
START
CONDITION
7026 FM 15
Guidelines for Calculating Typical Values of
Bus Pull-Up Resistors
120
100
80
40
60
20
20 40 60 80
100 120
0
0
RESISTANCE (KΩ)
BUS CAPACITANCE (pF)
MIN.
RESISTANCE
MAX.
RESISTANCE
R
MAX
=
C
BUS
t
R
R
MIN
=
I
OL MIN
V
CC MAX
=1.8KΩ
7026 FM 16
Bus Timing
Notes: (7) Typical values are f or TA = 25°C and nominal supply voltage (5V).
(8) tWR is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the nonvolatile write operation.
Page 12
X24641
12
PACKAGING INFORMATION
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
0.014 (0.35)
0.019 (0.49)
PIN 1
PIN 1 INDEX
0.010 (0.25)
0.020 (0.50)
0.050 (1.27)
0.188 (4.78)
0.197 (5.00)
0.004 (0.19)
0.010 (0.25)
0.053 (1.35)
0.069 (1.75)
(4X) 7°
0.016 (0.410)
0.037 (0.937)
0.0075 (0.19)
0.010 (0.25)
0° – 8°
X 45°
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
NOTE:ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
0.250"
0.050" TYPICAL
0.050"
TYPICAL
0.030"
TYPICAL
8 PLACESFOOTPRINT
7026 FM 19
Page 13
X24641
13
ORDERING INFORMATION
Part Mark Convention
Device
X24641 X X -X
X24641 X
X
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc.
makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the
described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the
right to discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967;
4,883, 976. Foreign patents and additional patents pending.
LIFE RELA TED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prev ent such an occurence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain
life, and whose failure to perform, when properly used in accordance with instr uctions for use provided in the labeling, can be reasonably
expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably e xpected to cause the
failure of the life support device or system, or to affect its saf ety or eff ectiv eness .
VCC Range
Blank = 5V ±10%
2.5 = 2.5V to 5.5V
Temperature Range
Blank = 0°C to +70°C
I = –40°C to +85°C
Package
X24641
Blank = 8-Lead SOIC
Blank = 4.5V to 5.5V, 0°C to +70°C
I = 4.5V to 5.5V, –40°C to +85°C
AE = 2.5V to 5.5V, 0°C to +70°C
AF = 2.5V to 5.5V, –40°C to +85°C
S8= 8-Lead SOIC
1.8 = 1.8V to 3.6V
AG = 1.8V to 3.6V, 0°C to +70°C
AH = 1.8V to 3.6V, –40°C to +85°C
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