Datasheet X24026X, X24026W-2,7, X24026W, X24026H-2,7, X24026H Datasheet (XICOR)



Xicor, Inc. 1994, 1995, 1996 Patents Pending

7020-1.2 2/24/97 T1/C0/D2 SH

1

Characteristics subject to change without notice

2K

X24026

256 x 8 Bit

Serial E2PROM

FEATURES

• 2.7V to 5.5V Power Supply

• Low Power CMOS
—Active Current Less Than 1mA
—Standby Current Less Than 50 µ A

• Internally Organized 256 x 8

• Self Timed Write Cycle
—Typical Write Cycle Time of 5 ms

• 2 Wire Serial Interface
—Bidirectional Data Transfer Protocol

• Four Byte Page Write Operation
—Minimizes T otal Write Time Per Byte

• High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
—ESD Protection > 2KV

DESCRIPTION

The X24026 is a CMOS 2048 bit serial E

2

PROM, inter­nally organized 256 x 8. The X24026 features a serial
interface and software protocol allowing operation on a
simple two wire bus.

Xicor E

2

PROMs are designed and tested for applications
requiring extended endurance. Inherent data retention is
greater than 100 years. Available in DICE for m with ISO
7816 compatible pinout.

ISO 7816 Compatible

FUNCTIONAL DIAGRAM

START

STOP

LOGIC

CONTROL

LOGIC

SLAVE ADDRESS

REGISTER

+COMPARATOR

H.V. GENERATION

TIMING

& CONTROL

WORD
ADDRESS
COUNTER

XDEC

YDEC

D

OUT

ACK

E PROM

2

64 X 32

DATA REGISTER

START CYCLE

V

CC

R/W

PIN

V

SS

SDA

D

OUT

LOAD INC

CK

8

7020 FRM 01

SCL

X24026

2

PIN DESCRIPTIONS
Serial Clock (SCL)

The SCL input is used to clock all data into and out of the
device.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into and
out of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open
collector outputs.

An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the
Guidelines for Calculating Typical Values of Bus Pull-Up
Resistors graph.

DIE CONFIGURATION

PIN DESCRIPTIONS

7020 FRM T01

Symbol Description

SDA Serial Data

SCL Serial Clock

V

SS

Ground

V

CC

+5V

V

CC

V

SS

SDA

SCL
SDA

X24026 Die Revision A

.055 x .079

7020 FRM 02

X24026

3

DEVICE OPERATION

The X24026 supports a bidirectional bus oriented proto­col. The protocol defines any de vice that sends data onto
the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is a master
and the device being controlled is the slave. The master
will always initiate data transf ers and pro vide the clock f or
both transmit and receive operations. Therefore, the
X24026 will be considered a slave in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during SCL
LOW. SD A state changes during SCL HIGH are reserved
for indicating start and stop conditions. Ref er to Figures 1
and 2.

Start Condition

All commands are preceded by the start condition, which
is a HIGH to LOW transition of SDA when SCL is HIGH.
The X24026 continuously monitors the SDA and SCL
lines for the start condition and will not respond to any
command until this condition has been met.

Figure 1. Data Validity

SCL

SDA

DATA STABLE DATA

CHANGE

7020 FRM 03

X24026

4

Stop Condition

All communications must be terminated by a stop condi­tion, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used by the
X24026 to place the device in the standby power mode
after a read sequence. A stop condition can only be
issued after the transmitting device has released the bus .

Acknowledge

Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. Dur ing the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. Ref er to Figure 3.

The X24026 will respond with an acknowledge after rec­ognition of a start condition and its slave address. If both
the device and a write operation hav e been selected, the
X24026 will respond with an acknowledge after the
receipt of each subsequent eight bit word.

In the read mode the X24026 will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the X24026 will
continue to transmit data. If an acknowledge is not
detected, the X24026 will terminate further data trans­missions. The master must then issue a stop condition to
return the X24026 to the standby power mode and place
the device into a known state.

Figure 2. Definition of Start and Stop

Figure 3. Acknowledge Response from Receiver

SCL

SDA

START BIT STOP BIT

7020 FRM 04

7020 FRM 05

SCL FROM

MASTER

DATA

OUTPUT

FROM

TRANSMITTER

1

8 9

DATA

OUTPUT

FROM

RECEIVER

START ACKNOWLEDGE

X24026

5

DEVICE ADDRESSING

Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave are the device type identifier (see
Figure 4). For the X24026 this is fix ed as 1010[B].

Figure 4. Slave Address

The next three significant bits are reserved address bits.
The last bit of the slave address defines the operation to

be performed. When set to one a read operation is
selected, when set to zero a write operations is selected.

Following the start condition, the X24026 monitors the
SDA bus comparing the slave address being transmitted
with its slave address. Upon a correct compare the
X24026 outputs an acknowledge on the SDA line.
Depending on the state of the R/W

bit, the X24026 will

execute a read or write operation.

WRITE OPERATIONS
Byte Write

For a write operation, the X24026 requires a second
address field. This address field is the word address,
comprised of eight bits, providing access to any one of
the 256 words of memory. Upon receipt of the word
address the X24026 responds with an acknowledge, and
awaits the next eight bits of data, again responding with
an acknowledge. The master then terminates the transfer
by generating a stop condition, at which time the X24026
begins the internal write cycle to the nonvolatile memory.
While the internal write cycle is in progress the X24026
inputs are disabled, and the device will not respond to
any requests from the master. Refer to Figure 5 for the
address, acknowledge and data transf er sequence.

Figure 5. Byte Write

Figure 6. Page Write

1

7020 FRM 06

01 0 0 0 0 R/W

DEVICE TYPE

IDENTIFIER

RESERVE
ADDRESS

BITS

BUS ACTIVITY:
MASTER

SDA LINE

X24026

S

T
A
R

T

SLAVE

ADDRESS

S

S

T
O
P

P

A
C
K

A
C
K

A
C
K

WORD

ADDRESS DATA

7020 FRM 07

BUS ACTIVITY:

BUS ACTIVITY:
MASTER

SDA LINE

X24026

S

T
A
R

T

SLAVE

ADDRESS

S

S

T
O
P

P

A
C
K

A
C
K

A
C
K

A
C
K

A
C
K

WORD

ADDRESS (n) DATA n DATA n+1 DATA n+3

NOTE:In this example n = xxxx 000 (B); x = 1 or 0

7020 FRM 08

BUS ACTIVITY:

X24026

6

Page Write

The X24026 is capable of a four byte page write opera­tion. It is initiated in the same manner as the byte wr ite
operation, but instead of terminating the write cycle after
the first data word is transferred, the master can transmit
up to three more words. After the receipt of each word,
the X24026 will respond with an acknowledge.

After the receipt of each word, the two low order address
bits are internally incremented by one. The high order six
bits of the address remain constant. If the master should
transmit more than four words prior to generating the
stop condition, the address counter will “roll ov er” and the
previously written data will be overwritten. As with the
byte write operation, all inputs are disabled until comple­tion of the internal write cycle. Refer to Figure 6 for the
address, acknowledge and data transf er sequence.

Acknowledge Polling

The disabling of the inputs, during the internal write oper­ation, can be used to take advantage of the typical 5 ms
write cycle time. Once the stop condition is issued to indi­cate the end of the host’s write operation the X24026 ini­tiates the internal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition fol­lowed by the slave address for a write operation. If the
X24026 is still busy with the write operation no ACK will
be returned. If the X24026 has completed the write oper­ation an ACK will be returned and the master can then
proceed with the next read or write operation.

READ OPERATIONS

Read operations are initiated in the same manner as
write operations with the exception that the R/W

bit of the
slave address is set to a one. There are three basic read
operations: current address read, random read and
sequential read.

It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read opera­tion, the master must either issue a stop condition during
the ninth cycle or hold SDA HIGH during the ninth clock
cycle and then issue a stop condition.

Flow 1. ACK Polling Sequence

7020 FRM 09

WRITE OPERATION

COMPLETED

ENTER ACK POLLING

ISSUE

START

ISSUE SLAVE_

ADDRESS AND R/W = 0

ACK

RETURNED?

NEXT

OPERATION

A WRITE?

ISSUE BYTE

ADDRESS

PROCEED

ISSUE STOP

NO

YES

YES

PROCEED

ISSUE STOP

NO

X24026

7

Current Address Read

Internally the X24026 contains an address counter that
maintains the address of the last word accessed, incre­mented by one. Therefore, if the last access (either a
read or write) was to address n, the next read operation
would access data from address n + 1. Upon receipt of
the slave address with the R/W

bit set to one, the X24026
issues an acknowledge and transmits the eight bit word
during the next eight clock cycles. The master terminates
this transmission by issuing a stop condition, omitting the
ninth clock cycle acknowledge. Refer to Figure 7 for the
sequence of address, acknowledge and data transf er .

Random Read

Random read operations allow the master to access any
memory location in a random manner. Prior to issuing
the slave address with the R/W bit set to one, the master
must first perform a “dummy” write operation. The master
issues the start condition, and the slave address followed
by the word address it is to read. After the word address
acknowledge, the master immediately reissues the start
condition and the slave address with the R/W bit set to
one. This will be followed by an acknowledge from the
X24026 and then by the eight bit word. The master termi­nates this transmission by issuing a stop condition, omit­ting the ninth clock cycle acknowledge. Refer to Figure 8
for the address, acknowledge and data transfer
sequence.

Figure 7. Current Address Read

Figure 8. Random Read

7020 FRM 10

S

T
A
R

T
S

S

T
O
P

P

A
C
K

BUS ACTIVITY:
MASTER

SDA LINE

X24026

BUS ACTIVITY:

SLAVE

ADDRESS DATA

7020 FRM 11

S

T
A
R

T
S

S

T
O
P

P

A
C
K

A
C
K

A
C
K

WORD

ADDRESS n

SLAVE

ADDRESS DATA n

S

T
A
R

T
S

BUS ACTIVITY:
MASTER

SDA LINE

X24026

BUS ACTIVITY:

SLAVE

ADDRESS

X24026

8

Sequential Read

Sequential Read can be initiated as either a current
address read or random access read. The first word is
transmitted as with the other modes, howe ver, the master
now responds with an acknowledge, indicating it requires
additional data. The X24026 continues to output data for
each acknowledge received. The master terminates this
transmission by issuing a stop condition, omitting the
ninth clock cycle acknowledge .

The data output is sequential, with the data from address
n followed by the data from n + 1. The address counter
for read operations increments all address bits, allowing
the entire memory contents to be serially read during one
operation. At the end of the address space (address

255), the counter “rolls over” to address 0 and the
X24026 continues to output data for each acknowledge
received. Refer to Figure 9 for the address, acknowledge
and data transfer sequence.

Figure 9. Sequential Read

7020 FRM 12

A
C
K

A
C
K

S
T
O
P

P

DATA n

A

C

K

DATA n+1

A
C
K

BUS ACTIVITY:
MASTER

SDA LINE

X24026

BUS ACTIVITY:

SLAVE

ADDRESS

DATA n+2 DATA n+x

X24026

9

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias...................–65 ° C to +135 ° C

Storage Temperature........................–65 ° C to +150 ° C

Voltage on any Pin with

Respect to VSS.............................–1.0V to +7.0V

D.C. Output Current.............................................5 mA

Lead Temperature (Soldering, 10 Seconds)......300 ° C

*COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods ma y affect de vice reliabil­ity .

RECOMMENDED OPERATING CONDITIONS

7020 FRM T09

7020 FRM T10

Temperature Min. Max.

Commercial 0 ° C 70 ° C

Supply Voltage Limits

X24026 4.5V to 5.5V

X24026-2.7 2.7V to 5.5V

D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified).

7020 FRM T02

CAPACITANCE T

A

= 25 ° C, f = 1 MHz, V

CC

= 5V

7020 FRM T04

Notes: (1) Must perform a stop command prior to measurement.

(2) V

IL

min. and V

IH

max. are for reference only and are not tested.

(3) This parameter is periodically sampled and not 100% tested.

Symbol Parameter

Limits

Units Test ConditionsMin. Max.

l

CC1

Power Supply Current (read) 1 mA SCL = V

CC

x 0.1/V

CC

x 0.9 Levels

@ 100 KHz, SDA = Open

l

CC2

Power Supply Current (write) 2

I

SB

(1)

Standby Current 50

µ

A SCL = SDA = V

CC

– 0.3V,

V

CC

= 5V ± 10%

I

SB

(2)

Standby Current 30

µ

A SCL = SDA = V

CC

– 0.3V, V

CC

= 3V

I

LI

Input Leakage Current 10

µ

A V

IN

= GND to V

CC

I

LO

Output Leakage Current 10

µ

A V

OUT

= GND to V

CC

V

lL

(2)

Input Low Voltage –1.0 V

CC

x 0.3 V

V

IH

(2)

Input High Voltage V

CC

x 0.7 V

CC

+ 0.5 V

V

OL

Output Low Voltage 0.4 V I

OL

= 3 mA

Symbol Parameter Max. Units Test Conditions

C

I/O

(3)

Input/Output Capacitance (SDA) 8 pF

V

I/O

= 0V

C

IN

(3)

Input Capacitance (SCL) 6 pF

V

IN

= 0V

X24026

10

A.C. CONDITIONS OF TEST

7020 PGM T05

EQUIVALENT A.C. LOAD CIRCUIT

Input Pulse Levels

V

CC

x 0.1 to VCC x 0.9

Input Rise and Fall
Times

10 ns

Input and Output Timing
Levels

V

CC

x 0.5

7020 FRM 13

1533Ω

OUTPUT

100pF

5.0V

A.C. CHARACTERISTICS (Over recommended operating conditions)
DATA INPUT TIMING

7020 FRM T06

Bus Timing

POWER-UP TIMING

7020 FRM T07

Notes: (4) t

PUR

and t

PUW

are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters

are periodically sampled and not 100% tested.

Symbol Parameter Min. Max. Units

f

SCL

SCL Clock Frequency 0 100 KHz

T

I

Noise Suppression Time
Constant at SCL, SDA Inputs

100 ns

t

AA

SCL Low to SDA Data Out Valid 0.3 3.5 µs

t

BUF

Time the Bus Must Be Free Before a
New Transmission Can Start

4.7 µs

t

HD:STA

Start Condition Hold Time 4.0 µs

t

LOW

Clock Low Period 4.7 µs

t

HIGH

Clock High Period 4.0 µs

t

SU:STA

Start Condition Setup Time 4.7 µs

t

HD:DAT

Data In Hold Time 0 µs

t

SU:DAT

Data In Setup Time 250 ns

t

R

SDA and SCL Rise Time 1 µs

t

F

SDA and SCL Fall Time 300 ns

t

SU:STO

Stop Condition Setup Time 4.7 µs

t

DH

Data Out Hold Time 300 ns

Symbol Parameter Max. Units

t

PUR

(4)

Power-up to Read Operation 1 ms

t

PUW

(4)

Power-up to Write Operation 5

ms

7020 FRM 14

t

SU:STA

t

HD:STA

t

HD:DAT

t

SU:DAT

t

LOW

t

SU:STO

t

R

t

BUF

SCL

SDA IN

SDA OUT

t

DH

t

AA

t

F

t

HIGH

X24026

11

WRITE CYCLE LIMITS

7020 FRM T08

The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/program
cycle. Dur ing the write cycle, the X24026 bus interface circuits are disabled, SDA is allowed to remain high, and the
device does not respond to its slav e address.

Write Cycle Timing

Notes: (5) Typical values are for TA = 25°C and nominal supply voltage (5V)

(6) tWR is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the device

requires to perform the internal write operation.

Symbol Parameter Min. Typ.

(5)

Max. Units

t

WR

(6)

Write Cycle Time 5 10 ms

7020 FRM 15

SCL

SDA 8th BIT

WORD n

ACK

t

WR

STOP

CONDITION

START

CONDITION

X24026

ADDRESS

Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors

SYMBOL TABLE

7020 FRM 16

120
100

80

40

60

20

20 40 60 80 100 120

0

0

RESISTANCE (KΩ)

BUS CAPACITANCE (pF)

MIN.
RESISTANCE

MAX.
RESISTANCE

R

MAX

=

C

BUS

t

R

R

MIN

=

I

OL MIN

V

CC MAX

=1.8KΩ

WAVEFORM INPUTS OUTPUTS

Must be
steady

Will be
steady

May change
from Low to
High

Will change
from Low to
High

May change
from High to
Low

Will change
from High to
Low

Don’t Care:
Changes
Allowed

Changing:
State Not
Known

N/A Center Line

is High
Impedance

X24026

12

8 PAD CHIP ON BOARD SMART CARD MODULE TYPE X

V

CC

V

SS

SDA

SCL
SDA

SmartCard Module generic

X24026

7020 FRM 17

V

CC

V

SS

NC

NC

NC

NC

SCL SDA

X24026

13

3.369 ± 0.002

(85.57 ± 0.05)

2.125 ± 0.002

(53.98 ± 0.05)

0.593 ± 0.002

(15.06 ± 0.05)

3° MAX.

DRAFT ANGLE

(ALL AROUND)

NOTES:

1.ALL DIMENSIONS ARE IN INCHES AND (MILLIMETERS).

2.SPECIFIED DIMS ARE MEASURED AT BOTTOM OF CAVITY.

3.MATERIAL: WHITE PVC MOLDED PLASTIC WITH ANTI-STATIC ADDITIVE.

4.SURFACE FINISH SUITABLE FOR OFFSET PRINTING.

0.430 ± 0.002

(10.92 ± 0.05)

0.475 ± 0.010

(12.07 ± 0.25)

0.478 ± 0.002
(12.14 ± 0.05)

R.0.125

(3.18) (4x)

0.31 ± 0.0005

(.079 ± 0.0127)

SCALE:5x

A

A

R. 0.030 (0.76) (4x)

MOLD GATE DETAIL

SECTION A-A

X24026 SMART CARD TYPE Y

7020 FRM 18

VCC
NC

SCL

NC

VSS
NC

SD

A

NC

X24026

14

0.465 ± 0.002
(11.81 ± 0.05)

A

SECTION A-A

A

R. 0.039 (1.00) (4X)

0.285 (7.24) MAX.

0.420 ± 0.002
(10.67 ± 0.05)

0.210 ± 0.002
(5.33 ± 0.05)

0.105 ± 0.002
(2.67 ± 0.05)

TYP.

(8x)

(8x)

0.105 ± 0.002
(2.67 ± 0.05)

0.008 ± 0.001
(0.20 ± 0.03)

0.233 ± 0.002
(5.92 ± 0.05)

0.174 ± 0.002
(4.42 ± 0.05)

0.146 ± 0.002
(3.71 ± 0.05)

DIE

0.0235 (0.60) MAX.

0.015 (0.38) MAX.

0.008 (0.20) MAX.

GLOB SIZE

FR4 TAPE

SEE DETAIL SHEET 3 COPPER, NICKEL PLATED, GOLD FLASH

R.0.013 (0.33) (8x)

0.270 (6.86) MAX.

SEE NOTE 7 SHT 2.

0.069 (1.75) MIN EPOXY
FREE AREA (TYP

.)

0.088 (2.24) MIN EPOXY
FREE AREA (TYP.)

8 PAD CHIP ON BOARD SMART CARD MODULE TYPE X

NOTE:

1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)

7020 FRM 19

X24026

15

ORDERING INFORMATION
X24026: 256 x 8 CMOS Serial E2PROM

Device

X24026 X X

Temperature Range

Blank = Commercial = 0°C to +70°C

Package

Y = ISO, SmartCard

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc.
makes no warranty, express, statutory, implied, or by description regarding the information set for th herein or regarding the freedom of the
described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for an y purpose. Xicor, Inc. reserves the
right to discontinue production and change specifications and prices at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967;
4,883, 976. Foreign patents and additional patents pending.

LIFE RELA TED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prev ent such an occurence.

Xicor's products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain
life, and whose failure to perfor m, when properly used in accordance with instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its saf ety or eff ectiv eness .

H = DICE (Waffle Packs)

–X

VCC Range

2.7 = 2.7V to 5.5V

W = Wafer form
X = COB SmartCard Module

Blank = 4.5V to 5.5V