Datasheet X20C17PM-55, X20C17PM-45, X20C17PM-35, X20C17PI-55, X20C17PI-45 Datasheet (XICOR)

APPLICATION NOTE

AVAILABLE

X20C17

AN56

16K X20C17 2K x 8 Bit

High Speed AUTOSTORE™ NOVRAM

FEATURES

• 24-Pin Standard SRAM DIP Pinout

• Fast Access Time: 35ns, 45ns, 55ns

• High Reliability

—Endurance: 1,000,000 Nonvolatile Store

Operations

—Retention: 100 Years Minimum

• AUTOSTORE™ NOVRAM

—Automatically Stores SRAM Data Into the

E2PROM Array When VCC Low Threshold is
Detected

—E2PROM Data Automatically Recalled Into

RAM Upon Power-up

• Low Power CMOS

—Standby: 250µA

• Infinite E

and Write Cycles

PIN CONFIGURATION

2

PROM Array Recall, and RAM Read

DESCRIPTION

The Xicor X20C17 is a 2K x 8 NOVRAM featuring a high­speed static RAM overlaid bit-for-bit with a nonvolatile
electrically erasable PROM (E2PROM) and the
AUTOSTORE feature which automatically saves the
RAM contents to E2PROM at power-down. The X20C17
is fabricated with advanced CMOS floating gate technol­ogy to achieve high speed with low power and wide
power-supply margin. The X20C17 features a compat­ible JEDEC approved byte-wide memory pinout for
industry standard SRAMs.

The NOVRAM design allows data to be easily trans­ferred from RAM to E
RAM (recall). The store operation is completed in 2.5ms
or less. An automatic array recall operation reloads the
contents of the E2PROM into RAM upon power-up.

Xicor NOVRAMS are designed for unlimited write
operations to RAM, either from the host or recalls from

2

PROM, and a minimum 1,000,000 store operations to

E
the E2PROM. Data retention is specified to be greater
than 100 years.

2

PROM (store) and E2PROM to

PLASTIC

A
A
A
A
A
A
A

A
I/O
I/O
I/O

V

SS

AUTOSTORE™ NOVRAM is a trademark of Xicor, Inc.
©Xicor, Inc. 1992, 1995 Patents Pending Characteristics subject to change without notice

2015-2.5 8/1/97 T1/C0/D0 SH

1

7

2

6

3

5

4

4

5

3

6

2
1
0
0
1
2

7
8
9
10
11
12

X20C17

24
23
22
21
20
19
18
17
16
15
14
13

1

V

CC

A

8

A

9

WE
OE
A

10

CE
I/O

7

I/O

6

I/O

5

I/O

4

I/O

3

2015 ILL F02.1

X20C17

PIN DESCRIPTIONS

Addresses (A

0–A10

)

The Address inputs select an 8-bit memory location
during a read or write operation.

Chip Enable (CE)

The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consumption
is reduced.

Output Enable (OE)

The Output Enable input controls the data output buffers
and is used to initiate read and recall operations. Output
Enable LOW disables a store operation regardless of
the state of CE, WE.

Data In/Data Out (I/O

–I/O7)

0

Data is written to or read from the X20C17 through the
I/O pins. The I/O pins are placed in the high impedance
state when either CE or OE is HIGH.

Write Enable (WE)

The Write Enable input controls the writing of data to the
static RAM.

PIN NAMES

Symbol Description

A0–A

10

I/O0–I/O

7

Address Inputs
Data Input/Output

WE Write Enable
CE Chip Enable
OE Output Enable

V

CC

V

SS

+5V
Ground

2015 PGM T01

FUNCTIONAL DIAGRAM

A3–A

8

CE
OE

WE

A0–A

2

A9–A

10

CONTROL

LOGIC

ROW

SELECT

VCC SENSE

EEPROM ARRAY

HIGH SPEED

2K x 8
SRAM

ARRAY

COLUMN

SELECT

&

I/OS

I/O0–I/O

7

RECALL

STORE

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2

X20C17

DEVICE OPERATION

The CE, OE, and WE inputs control the X20C17 opera-
tion. The X20C17 byte-wide NOVRAM uses a
2-line control architecture to eliminate bus contention in
a system environment. The I/O bus will be in a high
impedance state when either OE or CE is HIGH.

RAM Operations

RAM read and write operations are performed as they
would be with any static RAM. A read operation requires
CE and OE to be LOW. A write operation requires CE
and WE to be LOW. There is no limit to the number of
read or write operations performed to the RAM portion
of the X20C17.

Memory Transfer Operations

There are two memory transfer operations: a recall

2

operation whereby the data stored in the E

PROM array
is transferred to the RAM array; and a store operation
which causes the entire contents of the RAM array to be
stored in the E2PROM array.

Recall operations are performed automatically upon
power-up.

SYMBOL TABLE

The following symbol table provides a key to under­standing the conventions used in the device timing
diagrams. The diagrams should be used in conjunction
with the device timing specifications to determine actual
device operation and performance, as well as device
suitability for user’s application.

WAVEFORM

INPUTS

Must be
steady

May change
from LOW
to HIGH

May change
from HIGH
to LOW

Don’t Care:
Changes
Allowed

N/A

OUTPUTS

Will be
steady

Will change
from LOW
to HIGH

Will change
from HIGH
to LOW

Changing:
State Not
Known

Center Line
is High
Impedance

Store operations are performed automatically upon
power-down. The store operation take a maximum of

2.5ms.

Write Protection

The X20C17 supports two methods of protecting the
nonvolatile data.

—If after power-up no RAM write operations have

occured, no AUTOSTORE operation can be initiated.

Sense – All functions are inhibited when VCC is

—V

CC

≤ 3V typical.

3

X20C17

ABSOLUTE MAXIMUM RATINGS*

Temperature under Bias .................. –65°C to +135°C

Storage Temperature ....................... –65°C to +150°C

Voltage on any Pin with

Respect to V

.......................................

SS

–1V to +7V

D.C. Output Current ........................................... 10mA

Lead Temperature (Soldering, 10 seconds)...... 300°C

*COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any conditions other than those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

Temperature Min. Max.

Commercial 0°C +70°C
Industrial –40°C +85°C

Supply Voltage Limits

X20C17 4.5V to 5.25V

2015 PGM T03.1

Military –55°C +125°C

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D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)

Limits

Symbol Parameter Min. Max. Units Test Conditions

l

CC1

VCC Current (Active) 100 mA WE = VIH, CE = OE = V

IL

Address Inputs = 0.4V/2.4V Levels
@ f = 20MHz, All I/Os = Open

(2)

I

CC2

VCC Current During 2.5 mA All I/Os = Open
AUTOSTORE

I

SB1

VCC Standby Current 10 mA All Inputs = VIH, All I/Os = Open
(TTL Input)

I

SB2

VCC Standby Current 250 µA All Inputs = V

CC

– 0.3V

(CMOS Input) All I/Os = Open
I
I
V
V
V
V

LI
LO

IL
IH
OL
OH

(1)

(1)

Input Leakage Current 10 µAV

Output Leakage Current 10 µAV

= VSS to V

IN

= VSS to VCC, CE = V

OUT

Input LOW Voltage –1 0.8 V

Input HIGH Voltage 2 V

+ 1 V

CC

Output LOW Voltage 0.4 V IOL = 4mA

Output HIGH Voltage 2.4 V IOH = –4mA

CC

IH

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POWER-UP TIMING

Symbol Parameter Max. Units

(2)

t

PUR

t

PUW

(2)

Power-Up to RAM Operation 100 µs
Power-Up to Nonvolatile Operation 5 ms

CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V.

Symbol Test Max. Units Conditions

(2)

C

I/O

(2)

C

IN

Notes: (1) VIL min. and VIH max. are for reference only and are not tested.

(2) This parameter is periodically sampled and not 100% tested.

Input/Output Capacitance 10 pF V
Input Capacitance 6 pF VIN = 0V

4

2015 PGM T05

= 0V

I/O

2015 PGM T06.2

X20C17

ENDURANCE AND DATA RETENTION

Parameter Min. Units

Endurance 100,000 Data Changes Per Bit
Store Cycles 1,000,000 Store Cycles
Data Retention 100 Years

MODE SELECTION

CE WE OE Mode I/O Power

H X X Not Selected Output High Z Standby

L H L Read RAM Output Data Active
L L H Write “1” RAM Input Data High Active
L L H Write “0” RAM Input Data Low Active
L L L Not Allowed Output High Z Active
L H H No Operation Output High Z Active

2015 PGM T07.1

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EQUIVALENT A.C. LOAD CIRCUIT A.C. CONDITIONS OF TEST

Input Pulse Levels 0V to 3V

5V

Input Rise and
Fall Times 5ns

893Ω

Input and Output
Timing Levels 1.5V

OUTPUT

347Ω

30pF

2015 FHD F04

2015 PGM T08.1

5

X20C17

A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified)
Read Cycle Limits

X20C17-35

°C to +85°C X20C17-45 X20C17-55

-40

Symbol Parameter Min. Max. Min. Max. Min. Max. Units

t

RC

t

CE

t

AA

t

OE

(3)

t

LZ

(3)

t

OLZ

(3)

t

HZ

(3)

t

OHZ

t

OH

Read Cycle

Read Cycle Time 35 45 55 ns
Chip Enable Access Time 35 45 55 ns
Address Access Time 35 45 55 ns
Output Enable Access Time 20 25 30 ns
Chip Enable to Output in Low Z 0 0 0 ns
Output Enable to Output in Low Z 0 0 0 ns
Chip Disable to Output in High Z 0 15 0 20 0 25 ns
Output Disable to Output in High Z 0 15 0 20 0 25 ns
Output Hold From Address Change 0 0 0 ns

2015 PGM T10

ADDRESS

CE

OE

WE

DATA I/O

Note: (3) tLZ min., tHZ, t

= 5pF, from the point when CE or OE return HIGH (whichever occurs first) to the time when the Outputs are no longer driven.

C

L

min., and t

OLZ

t

RC

t

CE

t

t

OE

OE

t

OLZ

t

LZ

DATA VALID

are periodically sampled and not 100% tested. tHZ max. and t

OHZ

t

t

OH

AA

t

HZ

DATA VALID

max. are measured, with

OHZ

t

OHZ

2015 FHD F05

6

X20C17

Write Cycle Limits

X20C17-35 X20C17-45 X20C17-55

Symbol Parameter Min. Max. Min. Max. Min. Max. Units

t

WC

t

CW

t

AS

t

WP

t

WR

t

DW

t

DH

t

OEH

t

OES

(4)

t

OZ

Write Cycle

Write Cycle Time 35 45 55 ns
Chip Enable to End of Write Input 30 35 40 ns
Address Setup Time 0 0 0 ns
Write Pulse Width 30 35 40 ns
Write Recovery Time 0 0 0 ns
Data Setup to End of Write 15 20 25 ns
Data Hold Time 3 3 3 ns

OE High Hold Time 0 0 0 ns
OE High Setup Time 0 0 0 ns

Output Enable to Output in High Z 15 20 25 ns

2015 PGM T11

t

WC

ADDRESS

OE

CE

t

AS

WE

t

OZ

DATA OUT

DATA IN

Note: (4) tOW, tOZ are periodically sampled and not 100% tested.

t

CW

t

WP

t

DW

DATA VALID

t

DH

t

WR

t

OEH

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7

X20C17

AUTOSTORE Feature

The AUTOSTORE feature automatically saves the con­tents of the X20C17’s static RAM to the on-board bit-for­bit shadow E

2

PROM at power-down. This circuitry in­sures that no data is lost during accidental power-downs
or general system crashes, and is ideal for microproces­sor caching systems, embedded software systems, and
general system back-up memory.

AUTOSTORE CYCLE Timing Diagram and

5
4
3
2

VOLTS (V)

1

t

ASTO

STORE TIME

V

CC

AUTOSTORE CYCLE IN PROGRESS

TIME (ms)

Suggested AUTOSTORE Implementation Circuit

The X20C17 automatically initiates a nonvolatile store
cycle whenever Vcc falls below the AUTOSTORE thresh­old voltage (V
AUTOSTORE Cycle End Voltage (V
tion of the store cycle (t

). VCC must remain above the

ASTH

). The detailed timing for this

ASTO

ASEND

feature is illustrated in the AUTOSTORE timing dia­gram, below. Once the AUTOSTORE cycle is initiated,
all other device functions are inhibited.

V

CC

V

ASTH

V

ASEND

X20C17

V

CC

22µF

) for the dura-

2015 ILL F30.4

2015 FHD F14

AUTOSTORE CYCLE LIMITS

X20C17

Symbol Parameter Min. Max. Units

(5)

t

ASTO

V

ASTH

V

ASEND

Note: (5) t

ASTO

(5)

and V

AUTOSTORE Cycle Time 2.5 ms
AUTOSTORE Threshold Voltage 4.0 4.3 V
AUTOSTORE Cycle End Voltage 3.5 V

are periodically sampled and not 100% tested.

ASEND

2015 PGM T15

8

X20C17

Normalized ICC by Temperature over the VCC Range and Frequency

1.4

1.2
VCC = 5.5V

1.0

0.8

0.6

(NORMALIZED)

0.4

CC

I

0.2

0.0

0 2.0

VCC = 5.0V
VCC = 4.5V

1.0 3.0

4.0 5.0 5.5 6.6 8.3 10.0 11.1 12.5 13.3 14.3 15.2 16.7 20.0 25.0 30.0
FREQUENCY (MHz)

2015 FHD F31.1

Normalized ICC by Temperature over Frequency

1.4

1.2

-55°C

1.0

0.8

0.6

(NORMALIZED)

0.4

CC

I

0.2

0.0
0 2.0

1.0 3.0

+25°C

+125°C

4.0 5.0 5.5 6.6 8.3 10.0 11.1 12.5 13.3 14.3 15.2 16.7 20.0 25.0 30.0
FREQUENCY (MHz)

2015 FHD F33.2

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X20C17

PACKAGING INFORMATION

PIN 1 INDEX

PIN 1

24-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P

1.265 (32.13)

1.230 (31.24)

1.100 (27.94)
REF.

0.557 (14.15)

0.530 (13.46)

0.080 (2.03)

0.065 (1.65)

SEATING

PLANE

0.150 (3.81)

0.125 (3.18)

0.110 (2.79)

0.090 (2.29)

0.065 (1.65)

0.040 (1.02)

0.625 (15.87)

0.600 (15.24)

TYP. 0.010 (0.25)

0°

15°

NOTE:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH

0.162 (4.11)

0.140 (3.56)

0.030 (0.76)

0.015 (0.38)

0.022 (0.56)

0.014 (0.36)

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3926 FHD F03

X20C17

ORDERING INFORMATION

X20C17 X X -X

Device

Access Time

–35 = 35ns
–45 = 45ns
–55 = 55ns

Temperature Range

Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C

Package

P = 24 Lead Plastic Dip

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes
no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to
discontinue production and change specifications and prices at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.

US. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967;
4,883,976. Foreign patents and additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence.

Xicor’s products are not authorized for use as critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure
of the life support device or system, or to affect its satety or effectiveness.

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