Datasheet X20C16JMB-45, X20C16JMB-35, X20C16JM-55, X20C16JM-45, X20C16JM-35 Datasheet (XICOR)

APPLICATION NOTE

AVAILABLE

X20C16

AN56

16K X20C16 2K x 8 Bit

High Speed AUTOSTORE™ NOVRAM

FEATURES

• Fast Access Time: 35ns, 45ns, 55ns

• High Reliability

—Endurance: 1,000,000 Nonvolatile Store

Operations

—Retention: 100 Years Minimum

• AUTOSTORE™ NOVRAM

—Automatically Stores RAM Data Into the

E2PROM Array When VCC Low Threshold is

Detected
—User Enabled Option
—Open Drain AUTOSTORE Status Output Pin

• Power-on Recall

—E2PROM Data Automatically Recalled Into

RAM Upon Power-up

• Software Data Protection

—Locks Out Inadvertent Store Operations

• Low Power CMOS

—Standby: 250µA

• Infinite E

and Write Cycles

PIN CONFIGURATION

2

PROM Array Recall, and RAM Read

DESCRIPTION

The Xicor X20C16 is a 2K x 8 NOVRAM featuring a high­speed static RAM overlaid bit-for-bit with a nonvolatile
electrically erasable PROM (E2PROM) and the
AUTOSTORE feature which automatically saves the
RAM contents to E2PROM at power-down. The X20C16
is fabricated with advanced CMOS floating gate technol­ogy to achieve high speed with low power and wide
power-supply margin. The X20C16 features a compat­ible JEDEC approved pinout for byte-wide memories,
for industry standard RAMs, ROMs, EPROMs, and
E2PROMs.

The NOVRAM design allows data to be easily trans­ferred from RAM to E2PROM (store) and E2PROM to
RAM (recall). The store operation is completed in 5ms or
less and the recall operation is completed in 10µs or
less. An automatic array recall operation reloads the
contents of the E2PROM into RAM upon power-up.

Xicor NOVRAMS are designed for unlimited write
operations to RAM, either from the host or recalls from
E2PROM, and a minimum 1,000,000 store operations to
the E2PROM. Data retention is specified to be greater
than 100 years.

PLASTIC

CERDIP

X20C16

28

V

27

WE

26

AS

25

A

24

A

23

NC

22

OE

21

A

20

CE

19

I/O

18

I/O

17

I/O

16

I/O

15

I/O

3826 FHD F02

3826 FHD F15.1

CC

8
9

10

SOIC

X20C16

28

A

27

CE

26

I/O

25

I/O

24

I/O

23

I/O

22

I/O

21

V

20

I/O

19

I/O

18

I/O

17

A

16

A

15

A

1

NC

2

OE

3

A

9

7
6
5
4

V

3

A

AS

WE

CC
NE

NC

A
A
A
A
A

4

8

5
6
7
8
9
10

7

11

6

12

5

13

4

14

3

1

NE

2

NC

3

A

7

4

A

6

5

A

5

6

A

4

7

A

3

8

A

2

9

A

1

10

A

0

11

I/O

0

12

I/O

1

13

I/O

2

14

V

SS

AUTOSTORE™ NOVRAM is a trademark of Xicor, Inc.
©Xicor, Inc. 1991, 1995, 1996 Patents Pending Characteristics subject to change without notice

3826-2.9 7/31/97 T4/C0/D0 SH

10

SS

0
1
2

A

CE

10

31

32

7
6
5
4
3

OE

2
1
0

1

TSOP

VSSV

I/O

I/O1I/O

I/O3I/O4I/O5I/O6I/O

7

30

SS

25

26

27

28

29

N/C

A2A1A

0

0

2

17

18

19

20

21

22

23

24

LCC

PLCC

7

A

NCNENC

X20C16

16

15

14

13

12

10

11

987654321

NE

VCCVCCWE

AS

NC

A8A9NC

3826 ILL F17.2

A3A4A5A6A7NC

NC

I/O

3826 FHD F03

4 3 2 1 32 31 30

A

5

6

6

A

5

7

A

4

8

A

3

9

A

2

10

A

1

11

A

0

12
13

0

14 15 16 17 18 19 20

I/O1I/O

(TOP VIEW)

2

X20C16

SS

NC

V

VCCWE

AS

29
28
27
26
25
24
23
22
21

I/O3I/O4I/O

5

A
A
NC
NC
OE
A
CE
I/O
I/O

8
9

10

7
6

X20C16

PIN DESCRIPTIONS

Addresses (A0–A10)

The Address inputs select an 8-bit memory location
during a read or write operation.

Chip Enable (CE)

The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consumption
is reduced.

Output Enable (OE)

The Output Enable input controls the data output buffers
and is used to initiate read and recall operations. Output
Enable LOW disables a store operation regardless of
the state of CE, WE, or NE.

Data In/Data Out (I/O0–I/O7)

Data is written to or read from the X20C16 through the
I/O pins. The I/O pins are placed in the high impedance
state when either CE or OE is HIGH or when NE is LOW.

Write Enable (WE)

The Write Enable input controls the writing of data to the
static RAM.

FUNCTIONAL DIAGRAM

Nonvolatile Enable (NE)

The Nonvolatile Enable input controls the recall function
to the E2PROM array.

AUTOSTORE Output (AS)
AS is an open drain output which, when asserted indi-

cates VCC has fallen below the AUTOSTORE threshold
(V

). AS may be wire-ORed with multiple open drain

ASTH

outputs and used as an interrupt input to a microcontroller.

PIN NAMES

Symbol Description

A0–A

10

I/O0–I/O

7

Address Inputs
Data Input/Output

WE Write Enable
CE Chip Enable
OE Output Enable
NE Nonvolatile Enable
AS AUTOSTORE Output

V

CC

V

SS

+5V
Ground

NC No Connect

3826 PGM T01

A3–A

A0–A

A9–A

CE
OE

WE

NE

10

AS

8

CONTROL

LOGIC

2

ROW

SELECT

VCC SENSE

EEPROM ARRAY

HIGH SPEED

2K x 8
SRAM

ARRAY

COLUMN

SELECT

&

I/OS

I/O0–I/O

7

RECALL

STORE

3826 FHD F01

2

X20C16

DEVICE OPERATION

The CE, OE, WE, and NE inputs control the X20C16
operation. The X20C16 byte-wide NOVRAM uses a
2-line control architecture to eliminate bus contention in
a system environment. The I/O bus will be in a high
impedance state when either OE or CE is HIGH, or
when NE is LOW.

RAM Operations

RAM read and write operations are performed as they
would be with any static RAM. A read operation requires
CE and OE to be LOW with WE and NE HIGH. A write
operation requires CE and WE to be LOW with NE
HIGH. There is no limit to the number of read or write
operations performed to the RAM portion of the X20C16.

Memory Transfer Operations

There are two memory transfer operations: a recall
operation whereby the data stored in the E2PROM array
is transferred to the RAM array; and a store operation
which causes the entire contents of the RAM array to be
stored in the E2PROM array.

Recall operations are performed automatically upon
power-up and under host system control when NE, OE
and CE are LOW and WE is HIGH. The recall operation
takes a maximum of 5µs.

SDP (Software Data Protection)

There are two methods of initiating a store operation.
The first is the software store command. This command
takes the place of the hardware store employed on the
X20C04. This command is issued by entering into the
special command mode: NE, CE, and WE strobe LOW
while at the same time a specific address and data
combination is sent to the device. This is a three step
operation: the first address/data combination is 555[H]/
AA[H]; the second combination is 2AA[H]/55[H]; and the
final command combination is 555[H]/33[H]. This se­quence of pseudo write operations will immediately
initiate a store operation. Refer to the software com­mand timing diagrams for details on set and hold times
for the various signals.

The second method of storing data is with the
AUTOSTORE command. When enabled, data is auto-

matically stored from the RAM into the E2PROM array
whenever VCC falls below the preset Autostore thresh­old. This feature is enabled by performing the first two
steps for the software store with the command combina­tion being 555[H]/CC[H].

The AUTOSTORE feature is disabled by issuing the
three step command sequence with the command com­bination being 555[H]/CD[H]. The AUTOSTORE feature
will also be reset if VCC falls below the power-up reset
threshold (approximately 3.5V) and is then raised back
into the operation range.

Write Protection

The X20C16 supports two methods of protecting the
nonvolatile data.

—If after power-up the AUTOSTORE feature is not

enabled, no AUTOSTORE can occur.

—VCC Sense – All functions are inhibited when VCC is

≤ 3.0V typical.

SYMBOL TABLE

The following symbol table provides a key to under­standing the conventions used in the device timing
diagrams. The diagrams should be used in conjunction
with the device timing specifications to determine actual
device operation and performance, as well as device
suitability for user’s application.

WAVEFORM

INPUTS

Must be
steady

May change
from LOW
to HIGH

May change
from HIGH
to LOW

Don’t Care:
Changes
Allowed

N/A

OUTPUTS

Will be
steady

Will change
from LOW
to HIGH

Will change
from HIGH
to LOW

Changing:
State Not
Known

Center Line
is High
Impedance

3

X20C16

ABSOLUTE MAXIMUM RATINGS*

Temperature under Bias .................. –65°C to +135°C

Storage Temperature ....................... –65°C to +150°C

Voltage on any Pin with

Respect to V

.......................................

SS

–1V to +7V

D.C. Output Current ........................................... 10mA

Lead Temperature (Soldering, 10 seconds)...... 300°C

RECOMMENDED OPERATING CONDITIONS

*COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any conditions other than those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

Temperature Min. Max.

Commercial 0°C +70°C
Industrial –40°C +85°C
Military –55°C +125°C

3826 PGM T02.1

Supply Voltage Limits

X20C16 5V ±10%

3826 PGM T03.1

D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)

Limits

Symbol Parameter Min. Max. Units Test Conditions

l

CC1

VCC Current (Active) 100 mA NE = WE = VIH, CE = OE = V

IL

Address Inputs = 0.4V/2.4V Levels
@ f = 20MHz All I/Os = Open

I

CC2

I

CC3

VCC Current During Store 5 mA All Inputs = V

(2)

VCC Current During 2.5 mA All I/Os = Open

IH

AUTOSTORE

I

SB1

VCC Standby Current 10 mA CE = V

All Other Inputs = V

IH,

IH

(TTL Input) All I/Os = Open

I

SB2

VCC Standby Current 250 µA All Inputs = V

CC

– 0.3V

(CMOS Input) All I/Os = Open

I

LI

I

LO

V

IL

V

IH

V

OL

V

OLAS

V

OH

(1)

(1)

Input Leakage Current 10 µAV
Output Leakage Current 10 µAV

= VSS to V

IN

= VSS to VCC, CE = V

OUT

Input LOW Voltage –1 0.8 V
Input HIGH Voltage 2 V

+ 0.5 V

CC

Output LOW Voltage 0.4 V IOL = 4mA
AUTOSTORE Output 0.4 V I

OLAS

= 1mA

Output HIGH Voltage 2.4 V IOH = –4mA

CC

IH

3826 PGM T04.3

POWER-UP TIMING

Symbol Parameter Max. Units

(2)

t

PUR

t

PUW

(2)

Power-Up to RAM Operation 100 µs
Power-Up to Nonvolatile Operation 5 ms

CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V.

Symbol Test Max. Units Conditions

(2)

C

I/O

(2)

C

IN

Notes: (1) VIL min. and VIH max. are for reference only and are not tested.

(2) This parameter is periodically sampled and not 100% tested.

Input/Output Capacitance 10 pF V
Input Capacitance 6 pF VIN = 0V

4

3826 PGM T05

= 0V

I/O

3826 PGM T06.1

X20C16

ENDURANCE AND DATA RETENTION

Parameter Min. Units

Endurance 100,000 Data Changes Per Bit
Store Cycles 1,000,000 Store Cycles
Data Retention 100 Years

MODE SELECTION

CE WE NE OE Mode I/O Power

H X X X Not Selected Output High Z Standby

L H H L Read RAM Output Data Active
L L H H Write “1” RAM Input Data High Active
L L H H Write “0” RAM Input Data Low Active
L H L L Array Recall Output High Z Active
L L L H Software Command Input Data Active
L H H H Output Disabled Output High Z Active
L L L L Not Allowed Output High Z Active
L H L H No Operation Output High Z Active

3826 PGM T07.1

3826 PGM T09

EQUIVALENT A.C. LOAD CIRCUIT A.C. CONDITIONS OF TEST

Input Pulse Levels 0V to 3V

5V

Input Rise and
Fall Times 5ns

735Ω

Input and Output
Timing Levels 1.5V

OUTPUT

318Ω

30pF

3826 FHD F04

3826 PGM T08.1

5

X20C16

A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified)
Read Cycle Limits

X20C16-35

–40 to +85°C X20C16-45 X20C16-55

Symbol Parameter Min. Max. Min. Max. Min. Max. Units

t

RC

t

CE

t

AA

t

OE

(3)

t

LZ

(3)

t

OLZ

(3)

t

HZ

(3)

t

OHZ

t

OH

Read Cycle

ADDRESS

CE

Read Cycle Time 35 45 55 ns
Chip Enable Access Time 35 45 55 ns
Address Access Time 35 45 55 ns
Output Enable Access Time 20 25 30 ns
Chip Enable to Output in Low Z 0 0 0 ns
Output Enable to Output in Low Z 0 0 0 ns
Chip Disable to Output in High Z 0 15 0 20 0 25 ns
Output Disable to Output in High Z 0 15 0 20 0 25 ns
Output Hold From Address Change 0 0 0 ns

3826 PGM T10

t

RC

t

CE

t

t

OE

OE

OE

WE

DATA I/O

Note: (3) tLZ min., tHZ, t

CL = 5pF, from the point when CE or OE return HIGH (whichever occurs first) to the time when the outptus are no longer driven.

min., and t

OLZ

t

OLZ

t

LZ

DATA VALID

are periodically sampled and not 100% tested. tHZ max. and t

OHZ

6

t

OH

t

AA

t

HZ

DATA VALID

max. are measured, with

OHZ

t

OHZ

3826 FHD F05

X20C16

Write Cycle Limits

X20C16-35 X20C16-45 X20C16-55

Symbol Parameter Min. Max. Min. Max. Min. Max. Units

t

WC

t

CW

t

AS

t

WP

t

WR

t

DW

t

DH

(4)

t

WZ

(4)

t

OW

(4)

t

OZ

WE Controlled Write Cycle

Write Cycle Time 35 45 55 ns
Chip Enable to End of Write Input 30 35 40 ns
Address Setup Time 0 0 0 ns
Write Pulse Width 30 35 40 ns
Write Recovery Time 0 0 0 ns
Data Setup to End of Write 15 20 25 ns
Data Hold Time 3 3 3 ns
Write Enable to Output in High Z 15 20 25 ns
Output Active from End of Write 5 5 5 ns
Output Enable to Output in High Z 15 20 25 ns

3826 PGM T11

ADDRESS

OE

CE

WE

DATA OUT

DATA IN

t

AS

t

OZ

t

t

CW

WC

t

WP

t

DW

DATA VALID

t

DH

t

WR

t

OW

3826 FHD F06

Note: (4) tWZ, tOW, tOZ are periodically sampled and not 100% tested.

7

X20C16

CE Controlled Write Cycle

ADDRESS

t

WC

OE

CE

WE

DATA OUT

DATA IN

V

IH

t

CW

t

AS

t

WZ

t

WP

t

DW

DATA VALID

t

DH

t

WR

t

OW

3826 FHD F07.2

8

X20C16

ARRAY RECALL CYCLE LIMITS

X20C16-35 X20C16-45 X20C16-55

Symbol Parameter Min. Max. Min. Max. Min. Max. Units

t

RCC

(5)

t

RCP

t

RWE

Array Recall Cycle

ADDRESS

Array Recall Cycle Time 10 10 10 µs
Recall Pulse Width to 0.6 1000 40 1000 50 1000 ns

InitiateRecall
WE Setup Time to NE 000ns

3826 PGM T13

t

RCC

t

RCP

NE

OE

WE

CE

DATA I/O

Note: (5) The Recall Pulse Width (t

NE and CE.

t

RWE

) is a minimum time that NE, OE and CE must be LOW simultaneously to insure data integrity,

RCP

3826 FHD F10

9

X20C16

Software Command Timing Limits

X20C16-35 X20C16-45 X20C16-55

Symbol Parameter Min. Max. Min. Max. Min. Max. Units

t

STO

t

SP

t

SPH

t

WC

t

AS

t

AH

t

DS

t

DH

t

SOE

t

OEST

t

NHZ

t

NES

t

NEH

(6)

(7)

(7)

(7)

Store Cycle Time 5 5 5 ms
Store Pulse Width 30 40 50 ns
Store Pulse Hold Time 35 45 55 ns
Write Cycle Time 35 45 55 ns
Address Setup Time 0 0 0 ns
Address Hold time 0 0 0 ns
Data Setup Time 15 20 25 ns
Data Hold Time 3 3 3 ns
OE Disable to Store Function 20 20 20 ns
Output Enable from End of Store 10 10 10 ns
Nonvolatile Enable to Output in 15 20 25 ns

High Z

NE Setup Time 5 5 5 ns
NE Hold Time 5 5 5 ns

3826 PGM T12.2

CE Controlled Software Command Sequence

t

WC

ADDRESS

OE

CE

WE

NE

DATA OUT

DATA IN

t

SOE

t

AS

t

555 2AA

t

SP

t

NES

t

DS

t

NHZ

NEH

t

t

AH

DH

t

SPH

t

STO

555

t

OEST

55AA

CMD

Note: (6) The Store Pulse Width (tSP) is a minimum time that NE, WE and CE must be LOW simultaneously.

(7) t

SOE

, t

OEST

and t

are periodically sampled and not 100% tested.

NHZ

10

3826 FHD F08.2

X20C16

WE Controlled Software Command Sequence

ADDRESS

OE

CE

WE

NE

DATA OUT

DATA IN

t

SOE

t

AS

t

NES

t

WC
555 2AA

t

DS

t

SP

t

NHZ

t

NEH

t

t

AH

DH

t

SPH

t

STO

555

t

OEST

55AA

CMD

3826 FHD F09.2

11

X20C16

AUTOSTORE Feature

The AUTOSTORE feature automatically saves the con­tents of the X20C16’s static RAM to the on-board bit-for­bit shadow E2PROM at power-down. This circuitry in­sures that no data is lost during accidental power-downs
or general system crashes, and is ideal for microproces­sor caching systems, embedded software systems, and
general system back-up memory.

AUTOSTORE CYCLE Timing Diagrams

5
4
3
2

VOLTS (V)

1

t

ASTO

STORE TIME

V

ASTH

0V

V

AUTOSTORE CYCLE IN PROGRESS

TIME (ms)

V

CC

t

PUR

The AUTOSTORE instruction (EAS) to the SDP register
sets the AUTOSTORE enable latch, allowing the X20C16
to automatically perform a store operation whenever
VCC falls below the AUTOSTORE threshold (V
VCC must remain above the AUTOSTORE Cycle End
Voltage (V
(t

). The detailed timing for this feature is illustrated

ASTO

) for the duration of the store cycle

ASEND

in the AUTOSTORE timing diagram, below. Once the
AUTOSTORE cycle is initiated, all other device func­tions are inhibited.

CC

V

ASTH

V

ASEND

t

t

ASTO

PUR

ASTH

).

AS

3826 FHD F14

AUTOSTORE CYCLE LIMITS

X20C16

Symbol Parameter Min. Max. Units

t

ASTO

V

ASTH

V

ASEND

AUTOSTORE Cycle Time 2.5 ms
AUTOSTORE Threshold Voltage 4.0 4.3 V
AUTOSTORE Cycle End Voltage 3.5 V

3826 PGM T15

12

X20C16

SDP (Software Data Protection) Store State Diagram

NO STORE

NO STORE

RAM Write or Recall

NO STORE

POWER UP

DATA AA

ADDR 2AA,

DATA 55

STORE ON SS

ENABLE/RESET

AUTOSTORE

S0

ADDR 555,

DATA AAADDR 555,

S1

ADDR 555,

DATA AA

S2

WRITE: ADDR 555,
DATA=COMMAND

OR

Power

Down

RAS

POWER UP

Software

Store

Enabled

Software

Store &

AUTOSTORE

Enabled

EAS

SS

Power On
Recall

SS

EAS

Power Down

(AUTOSTORE)

3826 FHD F13.1

3826 FHD F12.1

SOFTWARE DATA PROTECTION COMMANDS

Command Data

EAS Enable AUTOSTORE CC[H]
RAS Reset AUTOSTORE CD[H]
SS Software Store 33[H]

3826 PGM T14.1

13

X20C16

NOTES

14

X20C16

PACKAGING INFORMATION

28-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D

PIN 1

1.490 (37.85)

1.435 (36.45)

1.30 (33.02)
REF.

0.610 (15.49)

0.500 (12.70)

0.100 (2.54)

0.035 (0.89)

SEATING

PLANE

0.200 (5.08)

0.125 (3.18)

0.110 (2.79)

0.090 (2.29)

TYP. 0.100 (2.54)

TYP. 0.010 (0.25)

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

0.070 (1.78)

0.030 (0.76)

TYP. 0.055 (1.40)

0.620 (15.75)

0.590 (14.99)

TYP. 0.614 (15.60)

0.225 (5.72)

0.140 (3.56)

0.060 (1.52)

0.015 (0.38)

0.026 (0.66)

0.014 (0.36)

TYP. 0.018 (0.46)

0°

15°

15

3926 FHD F08

X20C16

PACKAGING INFORMATION

PIN 1 INDEX

PIN 1

28-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P

1.460 (37.08)

1.400 (35.56)

1.300 (33.02)
REF.

0.550 (13.97)

0.510 (12.95)

0.085 (2.16)

0.040 (1.02)

SEATING

PLANE

0.150 (3.81)

0.125 (3.17)

0.110 (2.79)

0.090 (2.29)

0.020 (0.51)

0.016 (0.41)

TYP. 0.010 (0.25)

0.062 (1.57)

0.050 (1.27)

0.610 (15.49)

0.590 (14.99)

0°

15°

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

0.160 (4.06)

0.125 (3.17)

0.030 (0.76)

0.015 (0.38)

16

3926 FHD F04

X20C16

PACKAGING INFORMATION

32-PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE TYPE E

0.015 (0.38)

0.003 (0.08)

0.200 (5.08)
BSC

0.028 (0.71)

0.022 (0.56)
(32) PLCS.

0.150 (3.81) BSC

PIN 1

0.050 (1.27) BSC

0.458 (11.63)

0.442 (11.22)

0.458 (11.63)
––

0.300 (7.62)
BSC

0.020 (0.51) x 45° REF.

0.095 (2.41)

0.075 (1.91)

0.022 (0.56)

0.006 (0.15)

0.055 (1.39)

0.045 (1.14)

TYP. (4) PLCS.

0.040 (1.02) x 45° REF.
TYP. (3) PLCS.

0.120 (3.05)

0.060 (1.52)

0.088 (2.24)

0.050 (1.27)

0.560 (14.22)

0.540 (13.71)

0.400 (10.16)
BSC

132

NOTE:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. TOLERANCE: ±1% NTL ±0.005 (0.127)

PIN 1 INDEX CORDER

0.558 (14.17)
––

17

3926 FHD F14

X20C16

PACKAGING INFORMATION

32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J

0.420 (10.67)

0.495 (12.57)

0.485 (12.32)

TYP. 0.490 (12.45)

0.453 (11.51)

0.447 (11.35)

TYP. 0.450 (11.43)

0.300 (7.62)
REF.

0.050 (1.27) TYP.

0.021 (0.53)

0.013 (0.33)

TYP. 0.017 (0.43)0.045 (1.14) x 45°

SEATING PLANE

±0.004 LEAD

CO – PLANARITY

—

0.015 (0.38)

0.095 (2.41)

0.060 (1.52)

0.140 (3.56)

0.100 (2.45)

TYP. 0.136 (3.45)

0.048 (1.22)

0.042 (1.07)

PIN 1

0.595 (15.11)

0.585 (14.86)

TYP. 0.590 (14.99)

0.553 (14.05)

0.547 (13.89)

TYP. 0.550 (13.97)

0.400

REF.

(10.16)

3° TYP.

NOTES:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY

3926 FHD F13

18

X20C16

PACKAGING INFORMATION

28-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S

0.1040 (2.6416)

0.0940 (2.3876)

0.0192 (0.4877)

0.0138 (0.3505)

0.7080 (17.9832)

0.7020 (17.8308)

0.050 (1.270)
BSC

0.0160 (0.4064)

0.0100 (0.2540)

X 45°

0.2980 (7.5692)

0.2920 (7.4168)

0.0110 (0.2794)

0.0040 (0.1016)

0.4160 (10.5664)

0.3980 (10.1092)

BASE PLANE

SEATING PLANE

0° – 8°

0.0350 (0.8890)

0.0160 (0.4064)

0.0125 (0.3175)

0.0090 (0.2311)

NOTES:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES

3. BACK EJECTOR PIN MARKED “KOREA”

4. CONTROLLING DIMENSION: INCHES (MM)

3926 FHD F17

19

X20C16

PACKAGING INFORMATION

SEE NOTE 2

8.02 (0.315)

7.98 (0.314)

32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) TYPE T

SEE NOTE 2

12.50 (0.492)

12.30 (0.484)

PIN #1 IDENT.
O 0.76 (0.03)

0.50 (0.0197) BSC

0.26 (0.010)

0.14 (0.006)

1.18 (0.046)

1.02 (0.040)

FOOTPRINT

0.58 (0.023)

0.42 (0.017)

SOLDER PADS

14.15 (0.557)

13.83 (0.544)

14.80 ± 0.05

(0.583 ± 0.002)

0.30 ± 0.05

(0.012 ± 0.002)

TYPICAL

32 PLACES

0.17 (0.007)

0.03 (0.001)

1.30 ± 0.05

(0.051 ± 0.002)

0.17 (0.007)

0.03 (0.001)

SEATING
PLANE

15 EQ. SPC. 0.50 ± 0.04

0.0197 ± 0.016 = 7.50 ± 0.06
(0.295 ± 0.0024) OVERALL

TOL. NON-CUMULATIVE

0.50 ± 0.04

(0.0197 ± 0.0016)

NOTE:

1. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES IN PARENTHESES).

20

3926 ILL F38.1

X20C16

ORDERING INFORMATION

X20C16 X X -X

Device

Access Time

–35 = 35ns
–45 = 45ns
–55 = 55ns

Temperature Range

Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
MB = Mil. STD 883

Package

D = 28-Lead Cerdip
P = 28 Lead Plastic Dip
E = 32-Pad Ceramic LCC
J = 32-Lead PLCC
S = 28-Lead SOIC
T = 32-Lead TSOP

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes
no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to
discontinue production and change specifications and prices at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.

US. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967;
4,883,976. Foreign patents and additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence.

Xicor’s products are not authorized for use as critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure
of the life support device or system, or to affect its satety or effectiveness.

21