Datasheet X20C05PM-55, X20C05PM-45, X20C05PM-35, X20C05PI-55, X20C05J-55 Datasheet (XICOR)

APPLICATION NOTE

AVAILABLE

X20C05

AN56

4K X20C05 512 x 8

High Speed AUTOSTORE™ NOVRAM

FEATURES

• Fast Access Time: 35ns, 45ns, 55ns

• High Reliability

—Endurance: 1,000,000 Nonvolatile Store

Operations

—Retention: 100 Years Minimum

• Power-on Recall

—E2PROM Data Automatically Recalled Into

SRAM Upon Power-up

• AUTOSTORE™ NOVRAM

—User Enabled Option
—Automatically Stores SRAM Data Into the

E2PROM Array When VCC Low Threshold is
Detected

—Open Drain AUTOSTORE Status Output Pin

• Software Data Protection

—Locks Out Inadvertent Store Operations

• Low Power CMOS

—Standby: 250µA

• Infinite E

and Write Cycles

2

PROM Array Recall, and RAM Read

• Upward compatible with X20C16 (16K)

DESCRIPTION

The Xicor X20C05 is a 512 x 8 NOVRAM featuring a
high-speed static RAM overlaid bit-for-bit with a non­volatile electrically erasable PROM (E2PROM). The
X20C05 is fabricated with advanced CMOS floating
gate technology to achieve high speed with low power
and wide power-supply margin. The X20C05 features
the JEDEC approved pinout for byte-wide memories,
compatible with industry standard RAMs, ROMs,
EPROMs, and E2PROMs.

The NOVRAM design allows data to be easily trans­ferred from RAM to E2PROM (store) and E2PROM to
RAM (recall). The store operation is completed in 5ms or
less and the recall operation is completed in 5µs or less.

Xicor NOVRAMS are designed for unlimited write
operations to RAM, either from the host or recalls from
E2PROM, and a minimum 1,000,000 store operations to
the E2PROM. Data retention is specified to be greater
than 100 years.

PIN CONFIGURATION

PLASTIC

CERDIP

1

NE

2

NC

3
4

7

5

A

6

6

A

5

7

A

4

A

3

A

2

A

1

A

0

I/O

0

I/O

1

I/O

2

AUTOSTORE™ NOVRAM is a trademark of Xicor, Inc.
©Xicor, Inc. 1991 - 1997 Patents Pending Characteristics subject to change without notice

3827-2.7 7/31/97 T4/C0/D0 SH

8
9
10
11
12
13
14

X20C05

28

V

27

WE

26

AS

25

A

24

NC

23

NC

22

OE

21

NC

20

CE

19

I/O

18

I/O

17

I/O

16

I/O

15

I/O

3827 FHD F02

CC

8

4321323130

A

5

6

6

A

5

7

A

4

8

A

3

9

A

2

10

A

1

11

7
6
5
4
3

A

0

12

NC

I/O

1

13

0

14 15 16 17 18 19 20

7

A

NCNENC

(TOP VIEW)

2

I/O1I/O

LCC

PLCC

X20C05

SS

NC

V

VCCWE

AS

29
28
27
26
25
24
23
22
21

I/O3I/O4I/O

3827 FHD F03

A

8

NC
NC
NC
OE
NC
CE
I/O

7

I/O

6

5

X20C05

PIN DESCRIPTIONS

Addresses (A0–A8)

The Address inputs select an 8-bit memory location
during a read or write operation.

Chip Enable (CE)

The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consumption
is reduced.

Output Enable (OE)

The Output Enable input controls the data output buffers
and is used to initiate read and recall operations. Output
Enable LOW disables a store operation regardless of
the state of CE, WE, or NE.

Data In/Data Out (I/O0–I/O7)

Data is written to or read from the X20C05 through the
I/O pins. The I/O pins are placed in the high impedance
state when either CE or OE is HIGH or when NE is LOW.

Write Enable (WE)

The Write Enable input controls the writing of data to the
RAM.

FUNCTIONAL DIAGRAM

Nonvolatile Enable (NE)

The Nonvolatile Enable input controls the recall function
to the E2PROM array.

AUTOSTORE Output (AS)
AS is an open drain output which, when asserted indi-

cates VCC has fallen below the AUTOSTORE threshold
(V

). AS may be wire-ORed with multiple open drain

ASTH

outputs and used as an interrupt input to a microcontroller.

PIN NAMES

Symbol Description

A0–A

8

I/O0–I/O

7

Address Inputs
Data Input/Output

WE Write Enable
CE Chip Enable
OE Output Enable
NE Nonvolatile Enable
AS AUTOSTORE Output

V

CC

V

SS

+5V
Ground

NC No Connect

3827 PGM T01

A3–A

A0–A

A7–A

CE
OE

WE

NE

AS

6

CONTROL

LOGIC

2

8

ROW

SELECT

VCC SENSE

EEPROM ARRA Y

HIGH SPEED

512 x 8

SRAM

ARRAY

COLUMN

SELECT

&

I/OS

I/O0–I/O

7

RECALL

STORE

3827 FHD F01

2

X20C05

DEVICE OPERATION

The CE, OE, WE and NE inputs control the X20C05
operation. The X20C05 byte-wide NOVRAM uses a
2-line control architecture to eliminate bus contention in
a system environment. The I/O bus will be in a high
impedance state when either OE or CE is HIGH, or
when NE is LOW.

RAM Operations

RAM read and write operations are performed as they
would be with any static RAM. A read operation requires
CE and OE to be LOW with WE and NE HIGH. A write
operation requires CE and WE to be LOW with NE
HIGH. There is no limit to the number of read or write
operations performed to the RAM portion of the X20C05.

MEMORY TRANSFER OPERATIONS

There are two memory transfer operations: a recall
operation whereby the data stored in the E2PROM array
is transferred to the RAM array; and a store operation
which causes the entire contents of the RAM array to be
stored in the E2PROM array.

Recall operations are performed automatically upon
power-up and under host system control when NE, OE
and CE are LOW and WE is HIGH. The recall operation
takes a maximum of 5µs.

operation: the first address/data combination is
155[H]/AA[H]; the second combination is 0AA[H]/55[H];
and the final command combination is 155[H]/33[H].
This sequence of pseudo write operations will immedi­ately initiate a store operation. Refer to the software
command timing diagrams for details on set and hold
times for the various signals.

The second method of storing data is through the
AUTOSTORE command. When enabled, data is auto­matically stored from the RAM into the E2PROM array
whenever VCC falls below the preset AUTOSTORE
threshold. This feature is enabled by performing the first
two steps for the software store with the command
combination being 155[H]/CC[H].

The AUTOSTORE feature is disabled by issuing the
three step command sequence with the command com­bination being 155[H]/CD[H]. The AUTOSTORE feature
will also be reset if VCC falls below the power-up reset
threshold (approximately 3.5V) and is then raised back
into the operating range.

DATA PROTECTION

The X20C05 supports two methods of protecting the
nonvolatile data.

There are two methods of initiating a store operation.
The first is the software store command. This command
takes the place of the hardware store employed on the
X20C04. This command is issued by entering into the
special command mode: NE, CE, and WE strobe LOW
while at the same time a specific address and data
combination is sent to the device. This is a three step

—If after power-up the AUTOSTORE feature is not
enabled, no AUTOSTORE can occur.

—If after power-up no RAM write operations have oc­curred no store operation can be initiated. The software
store and AUTOSTORE commands will be ignored.

SYMBOL TABLE

WAVEFORM

INPUTS

Must be
steady

May change
from LOW
to HIGH

May change
from HIGH
to LOW

Don’t Care:
Changes
Allowed

N/A

OUTPUTS

Will be
steady

Will change
from LOW
to HIGH

Will change
from HIGH
to LOW

Changing:
State Not
Known

Center Line
is High
Impedance

3

X20C05

ABSOLUTE MAXIMUM RATINGS*

Temperature under Bias .................. –65°C to +135°C

Storage Temperature ....................... –65°C to +150°C

Voltage on any Pin with

Respect to V

.......................................

SS

–1V to +7V

D.C. Output Current ........................................... 10mA

Lead Temperature (Soldering, 10 seconds)...... 300°C

RECOMMENDED OPERATING CONDITIONS

*COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

Temperature Min. Max.

Commercial 0°C +70°C
Industrial –40°C +85°C
Military –55°C +125°C

3827 PGM T02.1

Supply Voltage Limits

X20C05 5V ±10%

3827 PGM T03.1

D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)

Limits

Symbol Parameter Min. Max. Units Test Conditions

l

CC1

VCC Current (Active) 100 mA NE = WE = VIH, CE = OE = V

IL

Address Inputs = 0.4V/2.4V Levels @
f = 20MHz. All I/Os = Open

I

CC2

I

CC3

VCC Current During Store 5 mA All Inputs = V

IH

VCC Current During 2.5 mA All I/Os = Open
AUTOSTORE

I

SB1

VCC Standby Current 10 mA CE = V

IH

(TTL Input) All Other Inputs = VIH, All I/Os = Open

I

SB2

VCC Standby Current 250 µA All Inputs = V

CC

– 0.3V

(CMOS Input) All I/Os = Open

I

LI

I

LO

V

IL

V

IH

V

OL

V

OLAS

V

OH

(1)

(1)

Input Leakage Current 10 µAVIN = VSS to V
Output Leakage Current 10 µAV

= VSS to VCC, CE = V

OUT

Input LOW Voltage –1 0.8 V
Input HIGH Voltage 2 V

+ 0.5 V

CC

Output LOW Voltage 0.4 V IOL = 4mA
AUTOSTORE Output 0.4 V I

OLAS

= 1mA

Output HIGH Voltage 2.4 V IOH = –4mA

CC

IH

3827 PGM T04.3

POWER-UP TIMING

Symbol Parameter Max. Units

(2)

t

PUR

t

PUW

(2)

Power-Up to RAM Operation 100 µs
Power-Up to Nonvolatile Operation 5 ms

CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V.

Symbol Test Max. Units Conditions

(2)

C

I/O

(2)

C

IN

Notes: (1) VIL min. and VIH max. are for reference only and are not tested.

(2) This parameter is periodically sampled and not 100% tested.

Input/Output Capacitance 10 pF V
Input Capacitance 6 pF VIN = 0V

4

3827 PGM T05

= 0V

I/O

3827 PGM T06.2

X20C05

ENDURANCE AND DATA RETENTION

Parameter Min. Units

Endurance 100,000 Data Changes Per Bit
Store Cycles 1,000,000 Store Cycles
Data Retention 100 Years

MODE SELECTION

CE WE NE OE Mode I/O Power

H X X X Not Selected Output High Z Standby

L H H L Read RAM Output Data Active
L L H H Write “1” RAM Input Data High Active
L L H H Write “0” RAM Input Data Low Active
L H L L Array Recall Output High Z Active
L L L H Software Command Input Data Active
L H H H Output Disabled Output High Z Active
L L L L Not Allowed Output High Z Active
L H L H No Operation Output High Z Active

EQUIVALENT A.C. LOAD CIRCUIT

A.C. CONDITIONS OF TEST

3827 PGM T07.1

3827 PGM T09

OUTPUT

5V

735Ω

318Ω

Input Pulse Levels 0V to 3V
Input Rise and

Fall Times 5ns
Input and Output

Timing Levels 1.5V

3827 PGM T08.2

30pF

3827 FHD F04

5

X20C05

A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified)
Read Cycle Limits

X20C05-35 X20C05-45 X20C05-55

Symbol Parameter Min. Max. Min. Max. Min. Max. Units

t

RC

t

CE

t

AA

t

OE

(3)

t

LZ

(3)

t

OLZ

(3)

t

HZ

(3)

t

OHZ

t

OH

Read Cycle

ADDRESS

CE

OE

Read Cycle Time 35 45 55 ns
Chip Enable Access Time 35 45 55 ns
Address Access Time 35 45 55 ns
Output Enable Access Time 20 25 30 ns
Chip Enable to Output in Low Z 0 0 0 ns
Output Enable to Output in Low Z 0 0 0 ns
Chip Disable to Output in High Z 15 20 25 ns
Output Disable to Output in High Z 15 20 25 ns
Output Hold From Address Change 0 0 0 ns

3827 PGM T10

t

RC

t

CE

t

t

OE

OE

V

IH

WE

DATA I/O

Note: (3) tLZ min., tHZ, t

from the point when CE or OE return HIGH (whichever occurs first) to the time when the outptus are no longer driven.

min., and t

OLZ

t

OLZ

t

LZ

DATA VALID

are periodically sampled and not 100% tested. tHZ and t

OHZ

6

t

OH

t

AA

t

HZ

DATA VALID

are measured, with CL = 5pF,

OHZ

t

OHZ

3827 FHD F05

X20C05

Write Cycle Limits

X20C05-25 X20C05-35 X20C05-45 X20C05-55

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Units

t

WC

t

CW

t

AS

t

WP

t

WR

t

DW

t

DH

(4)

t

WZ

(4)

t

OW

(4)

t

OZ

WE Controlled Write Cycle

Write Cycle Time 25 35 45 55 ns
Chip Enable to End of Write Input 25 30 35 40 ns
Address Setup Time 0 0 0 0 ns
Write Pulse Width 30 30 35 40 ns
Write Recovery Time 0 0 0 0 ns
Data Setup to End of Write 15 15 20 25 ns
Data Hold Time 0 0 3 3 ns
Write Enable to Output in High Z 15 20 25 ns
Output Active from End of Write 5 5 5 5 ns
Output Enable to Output in High Z 15 20 25 ns

3827 PGM T11

t

WC

ADDRESS

OE

CE

WE

DATA OUT

DATA IN

Note: (4) tWZ, t

OW

and t

t

AS

t

OZ

are periodically sampled and not 100% tested.

OZ

t

CW

t

WP

t

DW

DATA VALID

t

DH

t

WR

t

OW

3827 FHD F06

7

X20C05

CE Controlled Write Cycle

ADDRESS

t

WC

OE

CE

WE

DATA OUT

DATA IN

V

IH

t

CW

t

AS

t

WZ

t

WP

t

DW

DATA VALID

t

DH

t

WR

t

OW

3827 FHD F07.1

8

X20C05

Array Recall Cycle Limits

X20C05-35 X20C05-45 X20C05-55

Symbol Parameter Min. Max. Min. Max. Min. Max. Units

t

RCC

(5)

t

RCP

t

RWE

Array Recall Cycle

ADDRESS

Array Recall Cycle Time 5 5 5 µs
Recall Pulse Width to 30 1000 40 1000 50 1000 ns

Initiate Recall
WE Setup Time to NE 000ns

3827 PGM T13.1

t

RCC

t

RCP

NE

OE

WE

CE

DATA I/O

Note: (5) The Recall Pulse Width (t

NE and CE.

t

RWE

) is a minimum time that NE, OE and CE must be LOW simultaneously to insure data integrity,

RCP

3827 FHD F10

9

X20C05

Software Command Timing Limits

X20C05-35 X20C05-45 X20C05-55

Symbol Parameter Min. Max. Min. Max. Min. Max. Units

t

STO

t

SP

t

SPH

t

WC

t

AS

t

AH

t

DS

t

DH

t

SOE

t

OEST

t

NHZ

t

NES

t

NEH

(6)

(7)

(7)

(7)

Store Cycle Time 5 5 5 ms
Store Pulse Width 30 40 50 ns
Store Pulse Hold Time 35 45 55 ns
Write Cycle Time 35 45 55 ns
Address Setup Time 0 0 0 ns
Address Hold time 0 0 0 ns
Data Setup Time 15 20 25 ns
Data Hold Time 0 3 3 ns
OE Disable to Store Function 20 20 20 ns
Output Enable from End of Store 10 10 10 ns
Nonvolatile Enable to Output in 15 20 25 ns

High Z

NE Setup Time 5 5 5 ns
NE Hold Time 5 5 5 ns

3827 PGM T12.1

CE Controlled Software Command Sequence

t

WC

ADDRESS

OE

CE

WE

NE

DATA OUT

DATA IN

t

SOE

t

AS

t

155 0AA

t

SP

t

NES

t

DS

t

NHZ

NEH

t

t

AH

DH

t

SPH

t

STO

155

t

OEST

55AA

CMD

Notes: (6) The Store Pulse Width (tSP) is a minimum time that NE, WE and CE must be LOW simultaneously.

(7) t

SOE

, t

OEST

and t

are periodically sampled and not 100% tested.

NHZ

10

3827 FHD F08.2

X20C05

WE Controlled Software Command Sequence

ADDRESS

OE

CE

WE

NE

DATA OUT

DATA IN

t

SOE

t

AS

t

NES

t

WC
155 0AA

t

DS

t

SP

t

NHZ

t

NEH

t

t

AH

DH

t

SPH

t

STO

155

t

OEST

55AA

CMD

3827 FHD F09.2

11

X20C05

AUTOSTORE Feature

The AUTOSTORE feature automatically saves the con­tents of the X20C05’s RAM to the on-board bit-for-bit
shadow E2PROM at power-down. This circuitry insures
that no data is lost during accidental power-downs or
general system crashes, and is ideal for microprocessor
caching systems, embedded software systems, and
general system back-up memory.

The AUTOSTORE instruction (EAS) to the SDP register
sets the AUTOSTORE enable latch, allowing the X20C05

AUTOSTORE CYCLE Timing Diagrams

5
4
3
2

VOLTS (V)

1

t

ASTO

STORE TIME

V

ASTH

0V

AUTOSTORE CYCLE IN PROGRESS

TIME (ms)

V

CC

t

PUR

V

CC

t

to automatically perform a store operation whenever V
falls below the AUTOSTORE threshold (V
must remain above the AUTOSTORE Cycle End Volt­age (V

) for the duration of the store cycle (t

ASEND

The detailed timing for this feature is illustrated in the
AUTOSTORE timing diagram, below. Once the
AUTOSTORE cycle is initiated, all other device functions
are inhibited.

V

ASTH

V

ASEND

t

ASTO

PUR

ASTH

). V

ASTO

CC
CC

).

AS

3827 FHD F14

AUTOSTORE CYCLE LIMITS

X20C05

Symbol Parameter Min. Max. Units

t

ASTO

V

ASTH

V

ASEND

AUTOSTORE Cycle Time 2.5 ms
AUTOSTORE Threshold Voltage 4.0 4.3 V
AUTOSTORE Cycle End Voltage 3.5 V

12

3827 PGM T15

X20C05

SDP (Software Data Protection) Store State Diagram

POWER UP

POWER UP

NO STORE

NO STORE

RAM Write or Recall

NO STORE

S0

DATA AA

S1

ADDR 0AA,

DATA 55

S2

STORE ON SS

OR

ENABLE / RESET

AUTOSTORE

ADDR 155,

DATA AAADDR 155,

ADDR 155,

DATA AA

WRITE: ADDR 555,
DATA=COMMAND

3827 FHD F12.1

Power

Down

RAS

Software

Store

Enabled

Software

Store &

AUTOSTORE

Enabled

EAS

SS

Power On
Recall

SS

EAS

Power Down

(AUTOSTORE)

3827 FHD F13.1

SOFTWARE DATA PROTECTION COMMANDS

Command Data

EAS Enable AUTOSTORE CC[H]
RAS Reset AUTOSTORE CD[H]

SS Software Store 33[H]

3827 PGM T14.1

13

X20C05

NOTES

14

X20C05

PACKAGING INFORMATION

28-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D

PIN 1

1.490 (37.85)

1.435 (36.45)

1.30 (33.02)
REF.

0.610 (15.49)

0.500 (12.70)

0.100 (2.54)

0.035 (0.89)

SEATING

PLANE

0.200 (5.08)

0.125 (3.18)

0.110 (2.79)

0.090 (2.29)

TYP. 0.100 (2.54)

TYP. 0.010 (0.25)

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

0.070 (1.78)

0.030 (0.76)

TYP. 0.055 (1.40)

0.620 (15.75)

0.590 (14.99)

TYP. 0.614 (15.60)

0.225 (5.72)

0.140 (3.56)

0.060 (1.52)

0.015 (0.38)

0.026 (0.66)

0.014 (0.36)

TYP. 0.018 (0.46)

0°

15°

15

X20C05

PACKAGING INFORMATION

PIN 1 INDEX

28-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P

1.460 (37.08)

1.400 (35.56)

PIN 1

1.300 (33.02)
REF.

0.550 (13.97)

0.510 (12.95)

0.085 (2.16)

0.040 (1.02)

SEATING

PLANE

0.150 (3.81)

0.125 (3.17)

0.110 (2.79)

0.090 (2.29)

0.020 (0.51)

0.016 (0.41)

TYP. 0.010 (0.25)

0.062 (1.57)

0.050 (1.27)

0.610 (15.49)

0.590 (14.99)

0°

15°

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

0.160 (4.06)

0.125 (3.17)

0.030 (0.76)

0.015 (0.38)

16

X20C05

PACKAGING INFORMATION

32-PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE TYPE E

0.015 (0.38)

0.003 (0.08)

0.200 (5.08)
BSC

0.028 (0.71)

0.022 (0.56)
(32) PLCS.

0.150 (3.81) BSC

PIN 1

0.458 (11.63)

0.442 (11.22)

0.458 (11.63)
––

0.300 (7.62)
BSC

0.050 (1.27) BSC

0.020 (0.51) x 45° REF.

0.095 (2.41)

0.075 (1.91)

0.022 (0.56)

0.006 (0.15)

0.055 (1.39)

0.045 (1.14)

TYP. (4) PLCS.

0.040 (1.02) x 45° REF.
TYP. (3) PLCS.

0.120 (3.05)

0.060 (1.52)

0.088 (2.24)

0.050 (1.27)

0.560 (14.22)

0.540 (13.71)

0.400 (10.16)
BSC

132

NOTE:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. TOLERANCE: ±1% NTL ±0.005 (0.127)

PIN 1 INDEX CORDER

0.558 (14.17)
––

17

X20C05

PACKAGING INFORMATION

32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J

0.420 (10.67)

0.495 (12.57)

0.485 (12.32)

TYP. 0.490 (12.45)

0.453 (11.51)

0.447 (11.35)

TYP. 0.450 (11.43)

0.300 (7.62)
REF.

0.050 (1.27) TYP.

0.021 (0.53)

0.013 (0.33)

TYP. 0.017 (0.43)0.045 (1.14) x 45°

SEATING PLANE

±0.004 LEAD

CO – PLANARITY

—

0.015 (0.38)

0.095 (2.41)

0.060 (1.52)

0.140 (3.56)

0.100 (2.45)

TYP. 0.136 (3.45)

0.048 (1.22)

0.042 (1.07)

PIN 1

0.595 (15.11)

0.585 (14.86)

TYP. 0.590 (14.99)

0.553 (14.05)

0.547 (13.89)

TYP. 0.550 (13.97)

0.400

REF.

(10.16)

NOTES:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY

3° TYP.

18

X20C05

ORDERING INFORMATION

X20C05 X X -X

Device

Access Time

–35 = 35ns
–45 = 45ns
–55 = 55ns

Temperature Range

Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C

Package

D = 28-Lead Cerdip
P = 28 Lead Plastic DIP
E = 32-Pad Ceramic LCC
J = 32-Lead PLCC

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes
no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to
discontinue production and change specifications and prices at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.

US. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967;
4,883,976. Foreign patents and additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence.

Xicor’s products are not authorized for use as critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure
of the life support device or system, or to affect its satety or effectiveness.

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