Datasheet X1227V8I-4.5A, X1227V8I-2.7A, X1227V8I-2.7, X1227V8-4.5A, X1227V8-2.7A Datasheet (XICOR)
...Page 1
New Features
Repetitive Alarms &
Temperature Compensation
4K (512 x 8)
Real Time Clock/Calendar/CPU Supervisor with EEPROM
FEATURES
• Real Time Clock/Calendar
— Tracks time in Hours, Minutes, and Seconds
— Day of the Week, Day, Month, and Year
• 2 Polled Alarms (Non-volatile)
— Settable on the Second, Minute, Hour, Day of the
Week, Day, or Month
— Repeat Mode (periodic interrupts)
• Oscillator Compensation on chip
— Internal feedback resistor and compensation
capacitors
— 64 position Digitally Controlled Trim Capacitor
— 6 digital frequency adjustment settings to ±30ppm
• CPU Supervisor Functions
— Power On Reset, Low Voltage Sense
— Watchdog Timer (SW Selectable: 0.25s, 0.75s,
1.75s, off)
• Battery Switch or Super Cap Input
• 4K x 8 Bits of EEPROM
— 64-Byte Page Write Mode
— 8 modes of Block Lock™ Protection
— Single Byte Write Capability
• High Reliability
— Data Retention: 100 years
— Endurance: 100,000 cycles per byte
• 2-Wire™ Interface interoperable with I2C*
— 400kHz data transfer rate
• Low Power CMOS
— 1.25µA Operating Current (Typical)
• Small Package Options
— 8-Lead SOIC and 8-Lead TSSOP
X1227
APPLICATIONS
• Utility Meters
• HVAC Equipment
• Audio / Video Components
• Set Top Box / Television
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers / PDA
• POS Equipment
• Test Meters / Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial / Medical / Automotive
DESCRIPTION
The X1227 device is a Real Time Clock with clock/
calendar, two polled alarms with integrated 512x8
EEPROM, oscillator compensation, CPU Supervisor
(POR/LVS and WDT) and battery backup switch.
The oscillator uses an external, low-cost 32.768kHz
crystal. All compensation and trim components are
integrated on the chip. This eliminates several external
discrete components and a trim capacitor, saving
board area and component cost.
2-Wire
™
RTC
BLOCK DIAGRAM
Serial
X1
X2
Control
Decode
8
32.768kHz
SCL
SDA
*I2C is a Trademark of Philips.
REV 1.1.20 1/13/03
Interface
Decoder
RESET
Logic
Compensation
Oscillator
Control/
Registers
(EEPROM)
OSC
Watchdog
Timer
Frequency
Divider
Registers
(SRAM)
1Hz
Status
Low Voltage
Reset
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Timer
Calendar
Logic
Alarm
Time
Keeping
Registers
(SRAM)
Compare
Alarm Regs
(EEPROM)
Mask
4K
EEPROM
ARRAY
Characteristics subject to change without notice.
Battery
Switch
Circuitry
V
V
CC
BACK
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X1227
DESCRIPTION (continued)
The Real-Time Clock keeps track of time with separate
registers for Hours, Minutes, Seconds. The Calendar
has separate registers for Date, Month, Year and Dayof-week. The calendar is correct through 2099, with
automatic leap year correction.
The powerful Dual Alarms can be set to any Clock/
Calendar value for a match. For instance, every
minute, every Tuesday, or 5:23 AM on March 21. The
alarms can be polled in the Status Register. There is a
repeat mode for the alarms allowing a periodic
interrupt.
The X1227 device integrates CPU Supervisor functions and a Battery Switch. There is a Power-On Reset
(RESET output) with typically 250 ms delay from power
on. It will also assert RESET when Vcc goes below the
specified threshold. The V
threshold is user repro-
trip
grammable. There is a WatchDog Timer (WDT) with 3
selectable time-out periods (0.25s, 0.75s, 1.75s) and a
disabled setting. The watchdog activates the RESET
pin when it expires.
The device offers a backup power input pin. This
V
pin allows the device to be backed up by battery
BACK
or SuperCap. The entire X1227 device is fully
operational from 2.7 to 5.5 volts and the clock/calendar
portion of the X1227 device remains fully operational
down to 1.8 volts (Standby Mode).
The X1227 device provides 4K bits of EEPROM with 8
modes of BlockLock™ control. The BlockLock allows a
safe, secure memory for critical user and configuration
data, while allowing a large user storage area.
PIN DESCRIPTIONS
X1227
8-Pin SOIC
RESET
V
X1
X2
SS
1
2
3
4
V
8
CC
V
7
BACK
SCL
6
SDA
5
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device. The input buffer on this pin is always active
(not gated).
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It has an open drain output and may
be wire ORed with other open drain or open collector
outputs. The input buffer is always active (not gated).
An open drain output requires the use of a pull-up
resistor. The output circuitry controls the fall time of the
output signal with the use of a slope controlled pulldown. The circuit is designed for 400kHz 2-wire interface speeds.
V
BACK
This input provides a backup supply voltage to the
device. V
event the V
supplies power to the device in the
BACK
supply fails. This pin can be connected
CC
to a battery, a Supercap or tied to ground if not used.
RESET Output – RESET
This is a reset signal output. This signal notifies a host
processor that the watchdog time period has expired or
that the voltage has dropped below a fixed V
TRIP
threshold. It is an open drain active LOW output. Recommended value for the pullup resistor is 5K Ohms. If
unused, tie to ground.
X1, X2
The X1 and X2 pins are the input and output,
respectively, of an inverting amplifier. An external
32.768kHz quartz crystal is used with the X1227 to
supply a timebase for the real time clock. The
recommended crystal is a Citizen CFS206-32.768KDZF.
Internal compensation circuitry is included to form a
complete oscillator circuit. Care should be taken in the
placement of the crystal and the layout of the circuit.
Plenty of ground plane around the device and short
traces to X1 and X2 are highly recommended. See
Application section for more recommendations.
V
BACK
V
CC
X1
X2
NC = No internal connection
REV 1.1.20 1/13/03
X1227
8-Pin TSSOP
1
8
2
7
3
6
4
5
SCL
SDA
V
SS
RESET
Figure 1. Recommended Crystal connection
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X1
X2
Characteristics subject to change without notice.
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X1227
.
POWER CONTROL OPERATION
The power control circuit accepts a V
and a V
CC
BACK
input. The power control circuit powers the device from
V
when V
BACK
power the device from V
CC
< V
- 0.2V. It will switch back to
BACK
CC
when V
exceeds V
CC
BACK
Figure 2. Power Control
V
V
CC
BACK
Off
Voltage
On
In
REAL TIME CLOCK OPERATION
The Real Time Clock (RTC) uses an external
32.768kHz quartz crystal to maintain an accurate
internal representation of the second, minute, hour,
day, date, month, and year. The RTC has leap-year
correction. The clock also corrects for months having
fewer than 31 days and has a bit that controls 24 hour
or AM/PM format. When the X1227 powers up after
the loss of both V
CC
and V
, the clock will not
BACK
operate until at least one byte is written to the clock
register.
Reading the Real Time Clock
The RTC is read by initiating a Read command and
specifying the address corresponding to the register of
the Real Time Clock. The RTC Registers can then be
read in a Sequential Read Mode. Since the clock runs
continuously and a read takes a finite amount of time,
there is the possibility that the clock could change during
the course of a read operation. In this device, the time is
latched by the read command (falling edge of the clock
on the ACK bit prior to RTC data output) into a separate
latch to avoid time changes during the read operation.
The clock continues to run. Alarms occurring during a
read are unaffected by the read operation.
Writing to the Real Time Clock
The time and date may be set by writing to the RTC
registers. To avoid changing the current time by an
uncompleted write operation, the current time value is
loaded into a separate buffer at the falling edge of the
clock on the ACK bit before the RTC data input bytes,
the clock continues to run. The new serial input data
replaces the values in the buffer. This new RTC value
is loaded back into the RTC Register by a stop bit at
the end of a valid write sequence. An invalid write
operation aborts the time update procedure and the
contents of the buffer are discarded. After a valid write
operation the RTC will reflect the newly loaded data
beginning with the next “one second” clock cycle after
the stop bit is written. The RTC continues to update
the time while an RTC register write is in progress and
the RTC continues to run during any nonvolatile write
sequences. A single byte may be written to the RTC
without affecting the other bytes.
Accuracy of the Real Time Clock
The accuracy of the Real Time Clock depends on the
frequency of the quartz crystal that is used as the time
base for the RTC. Since the resonant frequency of a
crystal is temperature dependent, the RTC performance will also be dependent upon temperature. The
frequency deviation of the crystal is a fuction of the
turnover temperature of the crystal from the crystal’s
nominal frequency. For example, a >20ppm frequency
deviation translates into an accuracy of >1 minute per
month. These parameters are available from the
crystal manufacturer. Xicor’s RTC family provides onchip crystal compensation networks to adjust loadcapacitance to tune oscillator frequency from +116
ppm to –37 ppm when using a 12.5 pF load crystal.
For more detail information see the Application
section.
CLOCK/CONTROL REGISTERS (CCR)
The Control/Clock Registers are located in an area
separate from the EEPROM array and are only
accessible following a slave byte of “1101111x” and
reads or writes to addresses [0000h:003Fh]. The
clock/control memory map has memory addresses
from 0000h to 003Fh. The defined addresses are
described in the Table 1. Writing to and reading from
the undefined addresses are not recommended.
CCR access
The contents of the CCR can be modified by performing a byte or a page write operation directly to any
address in the CCR. Prior to writing to the CCR
(except the status register), however, the WEL and
RWEL bits must be set using a two step process (See
section “Writing to the Clock/Control Registers.”)
The CCR is divided into 5 sections. These are:
1. Alarm 0 (8 bytes; non-volatile)
2. Alarm 1 (8 bytes; non-volatile)
3. Control (4 bytes; non-volatile)
4. Real Time Clock (8 bytes; volatile)
5. Status (1 byte; volatile)
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Characteristics subject to change without notice.
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X1227
Each register is read and written through buffers. The
non-volatile portion (or the counter portion of the RTC) is
updated only if RWEL is set and only after a valid write
operation and stop bit. A sequential read or page write
operation provides access to the contents of only one
section of the CCR per operation. Access to another section requires a new operation. Continued reads or writes,
once reaching the end of a section, will wrap around to
change the time being read. A sequential read of the
CCR will not result in the output of data from the memory array. At the end of a read, the master supplies a
stop condition to end the operation and free the bus.
After a read of the CCR, the address remains at the
previous address +1 so the user can execute a current
address read of the CCR and continue reading the
next Register.
the start of the section. A read or write can begin at any
address in the CCR.
It is not necessary to set the RWEL bit prior to writing
the status register. Section 5 supports a single byte
read or write only. Continued reads or writes from this
section terminates the operation.
The state of the CCR can be read by performing a random read at any address in the CCR at any time. This
returns the contents of that register location. Additional registers are read by performing a sequential
read. The read instruction latches all Clock registers
into a buffer, so an update of the clock does not
ALARM REGISTERS
There are two alarm registers whose contents mimic the
contents of the RTC register, but add enable bits and
exclude the 24 hour time selection bit. The enable bits
specify which registers to use in the comparison between
the Alarm and Real Time Registers. For example:
– Setting the Enable Month bit (EMOn*) bit in combi-
nation with other enable bits and a specific alarm
time, the user can establish an alarm that triggers at
the same time once a year.
– *n = 0 for Alarm 0: N = 1 for Alarm 1
Table 1. Clock/Control Memory Map
Addr. Type
003F Status SR BAT AL1 AL0 0 0 RWEL WEL RTCF 01h
0037 RTC
0036 DW 0 0 0 0 0 DY2 DY1 DY0 0-6 00h
0035 YR Y23 Y22 Y21 Y20 Y13 Y12 Y11 Y10 0-99 00h
0034 MO 0 0 0 G20 G13 G12 G11 G10 1-12 00h
0033 DT 0 0 D21 D20 D13 D12 D11 D10 1-31 00h
0032 HR MIL 0 H21 H20 H13 H12 H11 H10 0-23 00h
0031 MN 0 M22 M21 M20 M13 M12 M11 M10 0-59 00h
0030 SC 0 S22 S21 S20 S13 S12 S11 S10 0-59 00h
0013 Control
0012 ATR 0 0 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 00h
0011 INT Unused
0010 BL BP2 BP1 BP0 WD1 WD0 0 0 0 00h
000F Alarm1
000E DWA1 EDW1 0 0 0 0 DY2 DY1 DY0 0-6 00h
000D YRA1 Unused - Default = RTC Year value (No EEPROM) - Future expansion
000C MOA1 EMO1 0 0 A1G20 A1G13 A1G12 A1G11 A1G10 1-12 00h
000B DTA1 EDT1 0 A1D21 A1D20 A1D13 A1D12 A1D11 A1D10 1-31 00h
000A HRA1 EHR1 0 A1H21 A1H20 A1H13 A1H12 A1H11 A1H10 0-23 00h
0009 MNA1 EMN1 A1M22 A1M21 A1M20 A1M13 A1M12 A1M11 A1M10 0-59 00h
0008 SCA1 ESC1 A1S22 A1S21 A1S20 A1S13 A1S12 A1S11 A1S10 0-59 00h
0007 Alarm0
0006 DWA0 EDW0 0 0 0 0 DY2 DY1 DY0 0-6 00h
0005 YRA0 Unused - Default = RTC Year value (No EEPROM) - Future expansion
0004 MOA0 EMO0 0 0 A0G20 A0G13 A0G12 A0G11 A0G10 1-12 00h
0003 DTA0 EDT0 0 A0D21 A0D20 A0D13 A0D12 A0D11 A0D10 1-31 00h
0002 HRA0 EHR0 0 A0H21 A0H20 A0H13 A0H12 A0H11 A0H10 0-23 00h
0001 MNA0 EMN0 A0M22 A0M21 A0M20 A0M13 A0M12 A0M11 A0M10 0-59 00h
0000 SCA0 ESC0 A0S22 A0S21 A0S20 A0S13 A0S12 A0S11 A0S10 0-59 00h
(SRAM)
(EEPROM)
(EEPROM)
(EEPROM)
Reg
Name
Y2K 0 0 Y2K21 Y2K20 Y2K13 0 0 Y2K10 19/20 20h
DTR 0 0 0 0 0 DTR2 DTR1 DTR0 00h
Y2K1 0 0 A1Y2K21 A1Y2K20 A1Y2K13 0 0 A1Y2K10 19/20 20h
Y2K0 0 0 A0Y2K21 A0Y2K20 A0Y2K13 0 0 A0Y2K10 19/20 20h
76543210 (optional)
Bit
Range
Default
REV 1.1.20 1/13/03
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Characteristics subject to change without notice.
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X1227
When there is a match, an alarm flag is set. The occurrence of an alarm can be determined by polling the
AL0 and AL1 bits or by enabling the IRQ output, using
it as hardware flag.
The alarm enable bits are located in the MSB of the
particular register. When all enable bits are set to ‘0’,
there are no alarms.
– The user can set the X1227 to alarm every Wednes-
day at 8:00 AM by setting the EDWn*, the EHRn*
and EMNn* enable bits to ‘1’ and setting the DWAn*,
HRAn* and MNAn* Alarm registers to 8:00 AM
Wednesday.
– A daily alarm for 9:30PM results when the EHRn*
and EMNn* enable bits are set to ‘1’ and the HRAn*
and MNAn* registers are set to 9:30 PM.
*n = 0 for Alarm 0: N = 1 for Alarm 1
REAL TIME CLOCK REGISTERS
Clock/Calendar Registers (SC, MN, HR, DT, MO,
YR)
These registers depict BCD representations of the
time. As such, SC (Seconds) and MN (Minutes) range
from 00 to 59, HR (Hour) is 1 to 12 with an AM or PM
indicator (H21 bit) or 0 to 23 (with MIL=1), DT (Date) is
1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99.
Date of the Week Register (DW)
This register provides a Day of the Week status and
uses three bits DY2 to DY0 to represent the seven
days of the week. The counter advances in the cycle
0-1-2-3-4-5-6-0-1-2-… The assignment of a numerical
value to a specific day of the week is arbitrary and may
be decided by the system software designer. The
default value is defined as ‘0’.
24 Hour Time
If the MIL bit of the HR register is 1, the RTC uses a
24-hour format. If the MIL bit is 0, the RTC uses a 12hour format and H21 bit functions as an AM/PM indicator with a ‘1’ representing PM. The clock defaults to
standard time with H21=0.
Leap Years
Leap years add the day February 29 and are defined
as those years that are divisible by 4. Years divisible by
100 are not leap years, unless they are also divisible
by 400. This means that the year 2000 is a leap year,
the year 2100 is not. The X1227 does not correct for
the leap year in the year 2100.
REV 1.1.20 1/13/03
www.xicor.com
STATUS REGISTER (SR)
The Status Register is located in the CCR Memory
Map at address 003Fh. This is a volatile register only
and is used to control the WEL and RWEL write
enable latches, read two power status and two alarm
bits. This register is separate from both the array and
the Clock/Control Registers (CCR).
Table 2. Status Register (SR)
Addr 7 6 5 4 3 2 1 0
003Fh BAT AL1 AL0 0 0 RWEL WEL RTCF
Default 0 0 0 0 0 0 0 1
BAT: Battery Supply—Volatile
This bit set to “1” indicates that the device is operating
from V
BACK
, not V
. It is a read-only bit and is set/
CC
reset by hardware (X1227 internally). Once the device
begins operating from V
, the device sets this bit to
CC
“0”.
AL1, AL0: Alarm bits—Volatile
These bits announce if either alarm 0 or alarm 1 match
the real time clock. If there is a match, the respective
bit is set to ‘1’. The falling edge of the last data bit in a
SR Read operation resets the flags. Note: Only the AL
bits that are set when an SR read starts will be reset.
An alarm bit that is set by an alarm occurring during an
SR read operation will remain set after the read operation is complete.
RWEL: Register Write Enable Latch—Volatile
This bit is a volatile latch that powers up in the LOW
(disabled) state. The RWEL bit must be set to “1” prior
to any writes to the Clock/Control Registers. Writes to
RWEL bit do not cause a nonvolatile write cycle, so the
device is ready for the next operation immediately after
the stop condition. A write to the CCR requires both
the RWEL and WEL bits to be set in a specific
sequence.
WEL: Write Enable Latch—Volatile
The WEL bit controls the access to the CCR and
memory array during a write operation. This bit is a
volatile latch that powers up in the LOW (disabled)
state. While the WEL bit is LOW, writes to the CCR or
any array address will be ignored (no acknowledge will
be issued after the Data Byte). The WEL bit is set by
writing a “1” to the WEL bit and zeroes to the other bits
of the Status Register. Once set, WEL remains set
until either reset to 0 (by writing a “0” to the WEL bit
and zeroes to the other bits of the Status Register) or
Characteristics subject to change without notice.
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X1227
until the part powers up again. Writes to WEL bit do
not cause a nonvolatile write cycle, so the device is
ready for the next operation immediately after the stop
condition.
RTCF: Real Time Clock Fail Bit—Volatile
This bit is set to a ‘1’ after a total power failure. This is
a read only bit that is set by hardware (X1227 internally) when the device powers up after having lost all
power to the device. The bit is set regardless of
whether V
CC
or V
is applied first. The loss of only
BACK
one of the supplies does not result in setting the RTCF
bit. The first valid write to the RTC after a complete
power failure (writing one byte is sufficient) resets the
RTCF bit to ‘0’.
Unused Bits:
This device does not use bits 3 or 4 in the SR, but
must have a zero in these bit positions. The Data Byte
output during a SR read will contain zeros in these bit
locations.
CONTROL REGISTERS
The Control Bits and Registers, described under this
section, are nonvolatile.
Block Protect Bits—BP2, BP1, BP0
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to a
protected block of memory is ignored. The block protect
bits will prevent write operations to one of eight segments
of the array. The partitions are described in Table 3 .
Table 3. Block Protect Bits
Protected Addresses
BP2
BP1
BP0
X1227 Array Lock
0 0 0 None (Default) None
180
100
000
000
000
000
000
– 1FF
h
– 1FF
h
– 1FF
h
– 03F
h
– 07F
h
– 0FF
h
– 1FF
h
h
h
h
h
h
h
h
Upper 1/4
Upper 1/2
Full Array
First Page
First 2 pgs
First 4 pgs
First 8 pgs
001
010
011
100
101
110
111
Watchdog Timer Control Bits—WD1, WD0
The bits WD1 and WD0 control the period of the
Watchdog Timer. See Table 4 for options.
Table 4. Watchdog Timer Time-Out Options
WD1 WD0
Watchdog Time-Out Period
0 0 1.75 seconds (Factory Default)
0 1 750 milliseconds
1 0 250 milliseconds
1 1 Disabled
ON-CHIP OSCILLATOR COMPENSATION
Digital Trimming Register (DTR) — DTR2, DTR1
and DTR0 (Non-Volatile)
The digital trimming Bits DTR2, DTR1 and DTR0
adjust the number of counts per second and average
the ppm error to achieve better accuracy.
DTR2 is a sign bit. DTR2=0 means frequency
compensation is > 0. DTR2=1 means frequency
compensation is < 0.
DTR1 and DTR0 are scale bits. DTR1 gives 10 ppm
adjustment and DTR0 gives 20 ppm adjustment.
A range from -30ppm to +30ppm can be represented
by using three bits above.
Table 5. Digital Trimming Registers
DTR Register
Estimated frequency
PPMDTR2 DTR1 DTR0
0 0 0 0 (Default)
0 1 0 +10
0 0 1 +20
0 1 1 +30
100 0
1 1 0 -10
1 0 1 -20
1 1 1 -30
REV 1.1.20 1/13/03
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Characteristics subject to change without notice.
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X1227
Analog Trimming Register (ATR) (Non-volatile)
Six analog trimming Bits from ATR5 to ATR0 are provided to adjust the on-chip loading capacitance range.
The on-chip load capacitance ranges from 3.25pF to
18.75pF. Each bit has a different weight for capacitance adjustment. Using a Citizen CFS-206 crystal
with different ATR bit combinations provides an estimated ppm range from +116ppm to -37ppm to the
nominal frequency compensation. The combination of
digital and analog trimming can give up to +146ppm
adjustment.
The on-chip capacitance can be calculated as follows:
C
= [(ATR value, decimal) x 0.25pF] + 11.0pF
AT R
Note that the ATR values are in two’s complement,
with ATR(000000) = 11.0pF, so the entire range runs
from 3.25pF to 18.75pF in 0.25pF steps.
The values calculated above are typical, and total load
capacitance seen by the crystal will include approximately 2pF of package and board capacitance in addition to the ATR value.
See Application section and Xicor’s Application Note
AN154 for more information.
– Write one to 8 bytes to the Clock/Control Registers
with the desired clock, alarm, or control data. This
sequence starts with a start bit, requires a slave byte
of “11011110” and an address within the CCR and is
terminated by a stop bit. A write to the CCR changes
EEPROM values so these initiate a nonvolatile write
cycle and will take up to 10ms to complete. Writes to
undefined areas have no effect. The RWEL bit is
reset by the completion of a nonvolatile write cycle,
so the sequence must be repeated to again initiate
another change to the CCR contents. If the
sequence is not completed for any reason (by sending an incorrect number of bits or sending a start
instead of a stop, for example) the RWEL bit is not
reset and the device remains in an active mode.
– Writing all zeros to the status register resets both the
WEL and RWEL bits.
– A read operation occurring between any of the
previous operations will not interrupt the register
write operation.
WRITING TO THE CLOCK/CONTROL REGISTERS
Changing any of the nonvolatile bits of the clock/control register requires the following steps:
– Write a 02h to the Status Register to set the Write
Enable Latch (WEL). This is a volatile operation,
so there is no delay after the write. (Operation
preceeded by a start and ended with a stop).
– Write a 06h to the Status Register to set both the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop).
REV 1.1.20 1/13/03
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Characteristics subject to change without notice.
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X1227
POWER ON RESET
Application of power to the X1227 activates a Power
On Reset Circuit that pulls the RESET pin active. This
signal provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power up.
When VCC exceeds the device V
threshold value
TRIP
for typically 250ms the circuit releases RESET, allowing the system to begin operation. Recommended slew
rate is between 0.2V/ms and 50V/ms.
WATCHDOG TIMER OPERATION
The watchdog timer is selectable. By writing a value to
WD1 and WD0, the watchdog timer can be set to 3 different time out periods or off. When the Watchdog
timer is set to off, the watchdog circuit is configured for
low power operation.
Watchdog Timer Restart
The Watchdog Timer is started by a falling edge of
SDA when the SCL line is high and followed by a stop
bit. The start signal restarts the watchdog timer
counter, resetting the period of the counter back to the
maximum. If another start fails to be detected prior to
the watchdog timer expiration, then the RESET pin
becomes active. In the event that the start signal
occurs during a reset time out period, the start will
have no effect. When using a single START to refresh
watchdog timer, a STOP bit should be followed to reset
the device back to stand-by mode.
LOW VOLTAGE RESET OPERATION
When a power failure occurs, and the voltage to the
part drops below a fixed v
voltage, a reset pulse is
TRIP
issued to the host microcontroller. The circuitry monitors the VCC line with a voltage comparator which
senses a preset threshold voltage. Power up and
power down waveforms are shown in Figure 4. The
Low Voltage Reset circuit is to be designed so the
RESET signal is valid down to 1.0V.
When the low voltage reset signal is active, the operation
of any in progress nonvolatile write cycle is unaffected,
allowing a nonvolatile write to continue as long as possible (down to the power on reset voltage). The low voltage
reset signal, when active, terminates in progress communications to the device and prevents new commands, to
reduce the likelihood of data corruption.
Figure 3. Watchdog Restart/Time Out
t
RSP
t
RSP<tWDO
SCL
SDA
RESET
REV 1.1.20 1/13/03
Start
Note: All inputs are ignored during the active reset period (t
Stop
t
RSP>tWDO
Start
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t
RSP>tWDO
t
RST
).
RST
Characteristics subject to change without notice. 8 of 28
t
RST
Page 9
X1227
Figure 4. Power On Reset and Low Voltage Reset
V
TRIP
V
CC
t
PURST
t
R
RESET
t
RPD
t
PURST
t
F
V
RVALID
VCC THRESHOLD RESET PROCEDURE
[OPTIONAL]
The X1227 is shipped with a standard VCC threshold
(V
) voltage. This value will not change over normal
TRIP
operating and storage conditions. However, in applications where the standard V
higher precision is needed in the V
is not exactly right, or if
TRIP
value, the
TRIP
X1227 threshold may be adjusted. The procedure is
described below, and uses the application of a nonvolatile write control signal.
Figure 5. Set V
RESET
V
CC
SCL
SDA
Level Sequence (V
TRIP
01234567
AEh 00h
= desired V
CC
VP = 15V
01234567 01234567 01234567
Setting the V
TRIP
Voltage
It is necessary to reset the trip point before setting the
new value.
To set the new V
voltage, apply the desired V
TRIP
threshold voltage to the VCC pin and tie the RESET pin
to the programming voltage VP. Then write data 00h to
address 01h. The stop bit following a valid write operation initiates the V
programming sequence. Bring
TRIP
RESET to VCC to complete the operation. Note: this
operation may take up to 10 milliseconds to complete
and also writes 00h to address 01h of the EEPROM
array.
value)
TRIP
01h
00h
TRIP
V
CC
Note: BP0, BP1, BP2 must be disabled.
Resetting the V
This procedure is used to set the V
voltage level. For example, if the current V
and the new V
be reset. When V
Voltage
TRIP
must be 4.0V, then the V
TRIP
is reset, the new V
TRIP
to a “native”
TRIP
TRIP
TRIP
is 4.4V
must
TRIP
is something less than 1.7V. This procedure must be used to
set the voltage to a lower value.
To reset the new V
voltage, apply more than 5.5V
TRIP
to the VCC pin and tie the RESET pin to the
programming voltage VP. Then write 00h to address
03h. The stop bit of a valid write operation initiates the
V
programming sequence. Bring RESET to VCC to
TRIP
complete the operation. Note: this operation takes up
REV 1.1.20 1/13/03
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to 10 milliseconds to complete and also writes 00h to
address 03h of the EEPROM array.
For best accuracy in setting V
, it is advised that the
TRIP
following sequence be used.
1.Program V
2.Measure resulting V
TRIP
as above.
TRIP
by measuring the VCC
value where a RESET occurs. Calculate Delta =
(Desired – Measured) V
3.Perform a V
program using the following formula
TRIP
TRIP
value.
to set the voltage of the RESET pin:
V
= (Desired Value – Delta) + 0.025V
RESET
Characteristics subject to change without notice. 9 of 28
Page 10
X1227
Figure 6. Reset V
RESET
V
CC
SCL
SDA
Note: BP0, BP1, BP2 must be disabled.
Level Sequence
TRIP
01234567
AEh
VP = 15V
01234567
00h
SERIAL COMMUNICATION
Interface Conventions
The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this family
operate as slaves in all applications.
Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 7.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met. See
Figure 8.
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the device into the Standby power mode after a
read sequence. A stop condition can only be issued
after the transmitting device has released the bus. See
Figure 8.
V
CC
01234567 01234567
03h
00h
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle, the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. Refer to Figure 9.
The device will respond with an acknowledge after recognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave
Address Byte. If a write operation is selected, the
device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for:
– The Slave Address Byte when the Device Identifier
and/or Select bits are incorrect
– All Data Bytes of a write when the WEL in the Write
Protect Register is LOW
– The 2nd Data Byte of a Status Register Write Opera-
tion (only 1 data byte is allowed)
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
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Characteristics subject to change without notice. 10 of 28
Page 11
X1227
Figure 7. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable Data Change Data Stable
Figure 8. Valid Start and Stop Conditions
SCL
SDA
Start Stop
Figure 9. Acknowledge Response From Receiver
SCL from
Master
Data Output
from Transmitter
Data Output
from Receiver
Start Acknowledge
DEVICE ADDRESSING
Following a start condition, the master must output a
Slave Address Byte. The first four bits of the Slave
Address Byte specify access to either the EEPROM
array or to the CCR. Slave bits ‘1010’ access the
EEPROM array. Slave bits ‘1101’ access the CCR.
When shipped from the factory, EEPROM array is
UNDEFINED, and should be programmed by the customer to a known state.
Bit 3 through Bit 1 of the slave byte specify the device
select bits. These are set to ‘111’.
The last bit of the Slave Address Byte defines the operation to be performed. When this R/W
bit is a one, then
a read operation is selected. A zero selects a write
operation. Refer to Figure 10.
After loading the entire Slave Address Byte from the
SDA bus, the X1227 compares the device identifier
81 9
and device select bits with ‘1010111’ or ‘1101111’.
Upon a correct compare, the device outputs an
acknowledge on the SDA line.
Following the Slave Byte is a two byte word address.
The word address is either supplied by the master
device or obtained from an internal counter. On power
up the internal address counter is set to address 0h, so
a current address read of the EEPROM array starts at
address 0. When required, as part of a random read,
the master must supply the 2 Word Address Bytes as
shown in Figure 10.
In a random read operation, the slave byte in the
“dummy write” portion must match the slave byte in the
“read” section. That is if the random read is from the
array the slave byte must be 1010111x in both
instances. Similarly, for a random read of the Clock/
Control Registers, the slave byte must be 1101111x in
both places.
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Characteristics subject to change without notice. 11 of 28
Page 12
X1227
Figure 10. Slave Address, Word Address, and Data Bytes (64 Byte pages)
Device Identifier
Array
CCR
1
1
D7 D6 D5 D2D4 D3 D1 D0
0
1
00 000A80
A6 A5
1
0
0
0
1
1
Write Operations
Byte Write
For a write operation, the device requires the Slave
Address Byte and the Word Address Bytes. This gives
the master access to any one of the words in the array
or CCR. (Note: Prior to writing to the CCR, the master
must write a 02h, then 06h to the status register in two
preceding operations to enable the write operation.
See “Writing to the Clock/Control Registers.” Upon
1
1
R/W
Slave Address Byte
Byte 0
Word Address 1
Byte 1
Word Address 0
A0A7 A2A4 A3 A1
Byte 2
Data Byte
Byte 3
receipt of each address byte, the X1227 responds with
an acknowledge. After receiving both address bytes
the X1227 awaits the eight bits of data. After receiving
the 8 data bits, the X1227 again responds with an
acknowledge. The master then terminates the transfer
by generating a stop condition. The X1227 then begins
an internal write cycle of the data to the nonvolatile
memory. During the internal write cycle, the device
inputs are disabled, so the device will not respond to
any requests from the master. The SDA output is at high
impedance. See Figure 11.
Figure 11. Byte Write Sequence
S
Signals from
the Master
SDA Bus
Signals From
The Slave
t
a
r
t
Slave
Address
0
1111
A
C
K
Word
Address 1
0000000
Address 0
A
C
K
Word
A
C
K
Figure 12. Writing 30 bytes to a 64-byte memory page starting at address 40.
7 Bytes
REV 1.1.20 1/13/03
Address
= 6
Address Pointer
Ends Here
Addr = 7
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Address
40
Characteristics subject to change without notice. 12 of 28
Data
23 Bytes
S
t
o
p
A
C
K
Address
63
Page 13
X1227
A write to a protected block of memory is ignored, but
will still receive an acknowledge. At the end of the write
command, the X1227 will not initiate an internal write
cycle, and will continue to ACK commands.
Page Write
The X1227 has a page write operation. It is initiated in
the same manner as the byte write operation; but
instead of terminating the write cycle after the first data
byte is transferred, the master can transmit up to 63
more bytes to the memory array and up to 7 more
bytes to the clock/control registers. (Note: Prior to writing to the CCR, the master must write a 02h, then 06h
to the status register in two preceding operations to
enable the write operation. See “Writing to the Clock/
Control Registers.”
After the receipt of each byte, the X1227 responds with
an acknowledge, and the address is internally incremented by one. When the counter reaches the end of
the page, it “rolls over” and goes back to the first
address on the same page. This means that the master can write 64 bytes to a memory array page or 8
bytes to a CCR section starting at any location on that
page. For example, if the master begins writing at loca-
tion 40 of the memory and loads 30 bytes, then the first
23 bytes are written to addresses 45 through 63, and
the last 7 bytes are written to columns 0 through 6.
Afterwards, the address counter would point to location
7 on the page that was just written. If the master supplies more than the maximum bytes in a page, then the
previously loaded data is over written by the new data,
one byte at a time. Refer to Figure 12.
The master terminates the Data Byte loading by issuing a stop condition, which causes the X1227 to begin
the nonvolatile write cycle. As with the byte write operation, all inputs are disabled until completion of the
internal write cycle. Refer to Figure 13 for the address,
acknowledge, and data transfer sequence.
Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte and it’s associated ACK signal. If a stop is issued
in the middle of a data byte, or before 1 full data byte +
ACK is sent, then the X1227 resets itself without performing the write. The contents of the array are not
affected.
Figure 13. Page Write Sequence
S
Signals from
the Master
SDA Bus
Signals from
the Slave
t
a
Slave
r
Address
t
0
1111
0000000
A
C
K
Word
Address 1
A
C
K
Word
Address 0
1 ≤ n ≤ 64 for EEPROM array
1 ≤ n ≤ 8 for CCR
Data
(1)
A
C
K
Data
(n)
S
t
o
p
A
C
K
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Characteristics subject to change without notice. 13 of 28
Page 14
X1227
Acknowledge Polling
Disabling of the inputs during nonvolatile write cycles
can be used to take advantage of the typical 5mS write
cycle time. Once the stop condition is issued to indicate the end of the master’s byte load operation, the
X1227 initiates the internal nonvolatile write cycle.
Acknowledge polling can begin immediately. To do this,
the master issues a start condition followed by the
Memory Array Slave Address Byte for a write or read
operation (AEh or AFh). If the X1227 is still busy with
the nonvolatile write cycle then no ACK will be
returned. When the X1227 has completed the write
operation, an ACK is returned and the host can proceed with the read or write operation. Refer to the flow
chart in Figure 15. Note: Do not use the CCR slave
byte (DEh or DFh) for acknowledge polling.
Read Operations
There are three basic read operations: Current
Address Read, Random Read, and Sequential Read.
Current Address Read
Internally the X1227 contains an address counter that
maintains the address of the last word read incremented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power up, the sixteen bit
address is initialized to 0h. In this way, a current
address read immediately after the power on reset can
download the entire contents of memory starting at the
first location.Upon receipt of the Slave Address Byte
with the R/W bit set to one, the X1227 issues an
acknowledge, then transmits eight data bits. The master terminates the read operation by not responding
with an acknowledge during the ninth clock and issuing
a stop condition. Refer to Figure 14 for the address,
acknowledge, and data transfer sequence.
Figure 15. Acknowledge Polling Sequence
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue START
Issue Memory Array Slave
Address Byte AFh (Read)
or AEh (Write)
ACK
returned?
YES
nonvolatile write
Cycle complete. Continue
command sequence?
YES
Continue normal
Read or Write
command
sequence
PROCEED
Issue STOP
NO
NO
Issue STOP
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
Figure 14. Current Address Read Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
REV 1.1.20 1/13/03
S
t
Slave
a
Address
r
t
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S
t
o
p
11111
A
C
Data
K
Characteristics subject to change without notice. 14 of 28
Page 15
X1227
Random Read
Random read operations allows the master to access
any location in the X1227. Prior to issuing the Slave
Address Byte with the R/W bit set to zero, the master
must first perform a “dummy” write operation.
The master issues the start condition and the slave
address byte, receives an acknowledge, then issues
the word address bytes. After acknowledging receipt of
each word address byte, the master immediately
issues another start condition and the slave address
byte with the R/W bit set to one. This is followed by an
acknowledge from the device and then by the eight bit
data word. The master terminates the read operation
by not responding with an acknowledge and then issuing a stop condition. Refer to Figure 16 for the address,
acknowledge, and data transfer sequence.
In a similar operation called “Set Current Address,” the
device sets the address if a stop is issued instead of
the second start shown in Figure 16. The X1227 then
goes into standby mode after the stop and all bus
activity will be ignored until a start is detected. This
operation loads the new address into the address
counter. The next Current Address Read operation will
read from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first data
byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indicating it requires additional data. The device continues
to output data for each acknowledge received. The master terminates the read operation by not responding with
an acknowledge and then issuing a stop condition.
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments
through all page and column addresses, allowing the
entire memory contents to be serially read during one
operation. At the end of the address space the counter
“rolls over” to the start of the address space and the
X1227 continues to output data for each acknowledge
received. Refer to Figure 17 for the acknowledge and
data transfer sequence.
Figure 16. Random Address Read Sequence
S
Signals from
the Master
SDA Bus
Signals from
the Slave
t
a
r
t
Slave
Address
0
1111
A
C
K
0000000
Figure 17. Sequential Read Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
Slave
Address
1
A
C
K
Data
(1)
Word
Address 1
S
Word
Address 0
A
C
K
A
C
K
Data
(2)
t
Slave
a
r
Address
t
1
1111
A
C
K
A
C
K
Data
(n-1)
(n is any integer greater than 1)
A
C
K
A
C
K
Data
Data
(n)
S
t
o
p
S
t
o
p
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Characteristics subject to change without notice. 15 of 28
Page 16
X1227
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ................... -65°C to +135°C
Storage Temperature......................... -65°C to +150°C
Voltage on VCC, V
BACK
pin
(respect to ground)...............................-0.5V to 7.0V
Voltage on SCL, SDA, X1 and X2
pin (respect to ground) ............... -0.5V to 7.0V or 0.5V
above VCC or V
(whichever is higher)
BACK
DC Output Current .............................................. 5 mA
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Lead Temperature (Soldering, 10 sec) ...............300°C
DC OPERATING CHARACTERISTICS (Temperature = -40°C to +85°C, unless otherwise stated.)
Symbol Parameter Conditions Min Typ Max Unit Notes
V
V
V
V
CC
BACK
CB
BC
Main Power Supply 2.7 5.5 V
Backup Power Supply 1.8 5.5 V
Switch to Backup Supply V
Switch to Main Supply V
-0.2 V
BACK
BACK
BACK
V
BACK
-0.1 V
+0.2 V
OPERATING CHARACTERISTICS
Symbol Parameter Conditions Min Typ Max Unit Notes
= 2.7V 400 µA
I
CC1
I
CC2
I
CC3
I
BACK
I
LI
I
LO
V
V
V
HYS
V
OL1
IH
Read Active Supply
Current
Program Supply Current
(nonvolatile)
Main Timekeeping
Current
Timekeeping Current –
(Low Voltage Sense
and Watchdog Timer
disabled
Input Leakage Current 10 µA 10
Output Leakage Current 10 µA 10
IL
Input LOW Voltage -0.5
Input HIGH Voltage
Schmitt Trigger Input
Hysteresis
Output LOW Voltage for
SDA and RESET
V
CC
= 5.0V 800 µA
V
CC
= 2.7V 2.5 mA
V
CC
= 5.0V 3.0 mA
V
CC
= 2.7V 10 µA
V
CC
= 5.0V 20 µA
V
CC
= 1.8V 1.25 µA
V
BACK
V
= 3.3V 1.5 µA
BACK
x 0.2 or
V
CC
V
BACK
V
CC
V
BACK
related level
V
CC
x 0.7 or
V
CC
V
BACK
.05 x V
.05 x V
x 0.7
or
CC
BACK
VCC = 2.7V 0.4
= 5.5V 0.4
V
CC
x 0.2
+ 0.5 or
+ 0.5
1, 5, 7, 14
2, 5, 7, 14
3, 7, 8, 14, 15
3, 6, 9, 14, 15
“See Perfor-
mance Data”
V13
V13
V13
V11
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Characteristics subject to change without notice. 16 of 28
Page 17
X1227
Notes: (1) The device enters the Active state after any start, and remains active: for 9 clock cycles if the Device Select Bits in the Slave
Address Byte are incorrect or until 200nS after a stop ending a read or write operation.
(2) The device enters the Program state 200nS after a stop ending a write operation and continues for tWC.
(3) The device goes into the Timekeeping state 200nS after any stop, except those that initiate a nonvolatile write cycle; tWC after a
stop that initiates a nonvolatile write cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in
the Slave Address Byte.
(4) For reference only and not tested.
(5) VIL = VCC x 0.1, VIH = VCC x 0.9, f
(6) VCC = 0V
(7) V
(8) V
(9) V
(10) V
(11) IOL = 3.0mA at 5.5V, 1.5mA at 2.7V
(12) IOH = -1.0mA at 5.5V, -0.4mA at 2.7V
(13) Threshold voltages based on the higher of Vcc or Vback.
(14) Using recommended crystal and oscillator network applied to X1 and X2 (25°C).
(15) Typical values are for TA = 25°C
= 0V
BACK
= V
SDA
SCL=VCC
SDA =VSCL=VBACK
= GND or VCC, V
SDA
, Others = GND or V
, Others = GND or V
= GND or VCC, V
SCL
Capacitance TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol Parameter Max. Units Test Conditions
(1)
C
OUT
(1)
C
IN
Notes: (1) This parameter is not 100% tested.
(2) The input capacitance between x1 and x2 pins can be varied between 5pF and 19.75pF by using analog trimming registers
Output Capacitance (SDA, RESET)10pFV
Input Capacitance (SCL) 10 pF VIN = 0V
= 400KHz
SCL
CC
BACK
RESET
= GND or V
CC
OUT
= 0V
AC CHARACTERISTICS
AC Test Conditions
Input Pulse Levels V
x 0.1 to VCC x 0.9
CC
Input Rise and Fall Times 10ns
Input and Output Timing
Levels
x 0.5
V
CC
Output Load Standard Output Load
Figure 18. Standard Output Load for testing the device with VCC = 5.0V
Equivalent AC Output Load Circuit for VCC = 5V
5.0V
1533Ω
SDA
100pF
For VOL= 0.4V
and I
= 3 mA
OL
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Characteristics subject to change without notice. 17 of 28
Page 18
X1227
AC Specifications (TA = -40°C to +85°C, VCC = +2.7V to +5.5V, unless otherwise specified.)
Symbol Parameter
f
SCL
t
IN
t
AA
t
BUF
t
LOW
t
HIGH
t
SU:STA
t
HD:STA
t
SU:DAT
t
HD:DAT
t
SU:STO
t
DH
t
R
t
F
SCL Clock Frequency 400 kHz
Pulse width Suppression Time at inputs 50
SCL LOW to SDA Data Out Valid 0.1 0.9 µs
Time the bus must be free before a new transmission can start 1.3 µs
Clock LOW Time 1.3 µs
Clock HIGH Time 0.6 µs
Start Condition Setup Time 0.6 µs
Start Condition Hold Time 0.6 µs
Data In Setup Time 100 ns
Data In Hold Time 0 µs
Stop Condition Setup Time 0.6 µs
Data Output Hold Time 50 ns
SDA and SCL Rise Time 20 +.1Cb
SDA and SCL Fall Time 20 +.1Cb
Cb Capacitive load for each bus line 400 pF
Notes: (1) This parameter is not 100% tested.
(2) Cb = total capacitance of one bus line in pF.
Min. Max. Units
(1)
(2)
(2)
300 ns
300 ns
ns
TIMING DIAGRAMS
Bus Timing
SCL
t
SU:STA
SDA IN
SDA
OUT
t
HD:STA
t
F
t
SU:DAT
t
HIGH
t
LOW
t
HD:DAT
t
R
t
SU:STO
t
t
DH
AA
t
BUF
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Characteristics subject to change without notice. 18 of 28
Page 19
X1227
Write Cycle Timing
SCL
SDA
8th Bit of Last Byte ACK
Stop
Condition
t
WC
Start
Condition
Power Up Timing
Symbol Parameter Min. Typ.
(1)
t
PUR
(1)
t
PUW
Notes: (1) Delays are measured from the time VCC is stable until the specified operation can be initiated. These parameters are not 100%
tested. VCC slew rate should be between 0.2mV/µsec and 50mV/µsec.
(2) Typical values are for TA = 25°C and VCC = 5.0V
Time from Power Up to Read 1 ms
Time from Power Up to Write 5 ms
(2)
Max. Units
Nonvolatile Write Cycle Timing
Symbol Parameter Min. Typ.
(1)
t
WC
Note: (1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.
It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Write Cycle Time 5 10 ms
(1)
Max. Units
WATCHDOG TIMER/LOW VOLTAGE RESET OPERATING CHARACTERISTICS
Watchdog/Low Voltage Reset Parameters (See Figures 3 and 4)
Symbols Parameters Min. Typ. Max. Unit
Programmed Reset Trip Voltage
V
PTRIP
t
RPD
t
PURST
t
t
t
WDO
t
RST
t
RSP
V
RVALID
X1227-4.5A
X1227
X1227-2.7A
X1227-2.7
VCC Detect to RESET LOW 500 ns
Power Up Reset Time-out Delay
F
R
VCC Fall Time 10 µs
VCC Rise Time 10 µs
Watchdog Timer Period (Crystal=32.768kHz):
WD1=0, WD0=0
WD1=0, WD0=1
WD1=1, WD0=0
Watchdog Reset Time-out Delay (Crystal=32.768kHz) 225 250 275 ms
2-Wire interface 1 µs
Reset Valid V
CC
4.50
4.25
2.75
2.55
4.63
4.38
2.85
2.65
4.75
4.50
2.95
2.75
100 250 400 ms
1.7
725
225
1.75
750
250
1.8
775
275
ms
ms
1.0 V
V
s
REV 1.1.20 1/13/03
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Characteristics subject to change without notice. 19 of 28
Page 20
X1227
V
Programming Timing Diagram
TRIP
V
CC
(V
)
TRIP
V
TRIP
RESET
V
CC
SCL
SDA
V
Programming Parameters
TRIP
t
VPS
0123456 7
VP = 15V
01234567 0123456 7 01234567
AEh 03h/01h
t
TSU
t
VPH
00h00h
t
THD
t
VPO
t
RP
Parameter Description Min. Max. Units
t
VPS
t
VPH
t
TSU
t
THD
t
VPO
t
RP
V
P
V
TRAN
V
tv
programming parameters are not 100% Tested.
V
TRIP
V
Program Enable Voltage Setup time 1 µs
TRIP
V
Program Enable Voltage Hold time 1 µs
TRIP
V
Setup time 1 µs
TRIP
V
Hold (stable) time 10 ms
TRIP
V
Program Enable Voltage Off time
TRIP
(Between successive adjustments)
V
Program Recovery Period
TRIP
(Between successive adjustments)
0µs
10 ms
Programming Voltage 14 16 V
V
Programmed Voltage Range 1.7 5.0 V
TRIP
V
Program variation after programming
TRIP
(Programmed at 25°C)
-25 +25 mV
V
CC
REV 1.1.20 1/13/03
www.xicor.com
Characteristics subject to change without notice. 20 of 28
Page 21
X1227
APPLICATION SECTION
CRYSTAL OSCILLATOR AND TEMPERATURE
COMPENSATION
Xicor has now integrated the oscillator compensation
circuity on-chip, to eliminate the need for external components and adjust for crystal drift over temperature
and enable very high accuracy time keeping (<5ppm
drift.
The Xicor RTC family uses an oscillator circuit with onchip crystal compensation network, including adjustable load-capacitance. The only external component
required is the crystal. The compensation network is
optimized for operation with certain crystal parameters
which are common in many of the surface mount or
tuning-fork crystals available today. Table 6 summarizes these parameters.
Table 7 contains some crystal manufacturers and part
numbers that meet the requirements for the Xicor RTC
products.
The turnover temperature in Table 6 describes the
temperature where the apex of the of the drift vs. temperature curve occurs. This curve is parabolic with the
drift increasing as (T-T0)2. For an Epson MC-405
device, for example, the turnover temperature is typi-
cally 25 deg C, and a peak drift of >110ppm occurs at
the temperature extremes of –40 and +85 deg C. It is
possible to address this variable drift by adjusting the
load capacitance of the crystal, which will result in predictable change to the crystal frequency. The Xicor
RTC family allows this adjustment over temperature
since the devices include on-chip load capacitor trimming. This control is handled by the Analog Trimming
Register, or ATR, which has 6 bits of control. The load
capacitance range covered by the ATR circuit is
approximately 3.25pF to 18.75pF, in 0.25pf increments. Note that actual capacitance would also
include about 2pF of package related capacitance. Incircuit tests with commercially available crystals demonstrate that this range of capacitance allows frequency control from +116ppm to –37ppm, using a
12.5pF load crystal.
In addition to the analog compensation afforded by the
adjustable load capacitance, a digital compensation
feature is available for the Xicor RTC family. There are
three bits known as the Digital Trimming Register or
DTR, and they operate by adding or skipping pulses in
the clock signal. The range provided is ±30ppm in
increments of 10ppm. The default setting is 0ppm. The
DTR control can be used for coarse adjustments of
frequency drift over temperature or for crystal initial
accuracy correction.
Table 6. Crystal Parameters Required for Xicor RTC’s
Parameter Min Typ Max Units Notes
Frequency 32.768 kHz
Freq. Tolerance ±100 ppm Down to 20ppm if desired
Turnover Temperature 20 25 30 °C
Operating Temperature Range -40 85 °C
Parallel Load Capacitance 12.5 pF
Equivalent Series Resistance 50 kΩ For best oscillator performance
Typically the value used for most
crystals
Table 7. Crystal Manufacturers
Manufacturer Part Number Temp Range +25°C Freq Toler.
Citizen CM201, CM202, CM200S -40 to +85°C ±20ppm
Epson MC-405, MC-406 -40 to +85°C ±20ppm
Raltron RSM-200S-A or B -40 to +85°C ±20ppm
SaRonix 32S12A or B -40 to +85°C ±20ppm
Ecliptek ECPSM29T-32.768K -10 to +60°C ±20ppm
ECS ECX-306/ECX-306I -10 to +60°C ±20ppm
Fox FSM-327 -40 to +85°C ±20ppm
REV 1.1.20 1/13/03
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Characteristics subject to change without notice. 21 of 28
Page 22
X1227
A final application for the ATR control is in-circuit calibration for high accuracy applications, along with a
temperature sensor chip. Once the RTC circuit is powered up with battery backup, the frequency drift is measured. The ATR control is then adjusted to a setting
which minimizes drift. Once adjusted at a particular
temperature, it is possible to adjust at other discrete
temperatures for minimal overall drift, and store the
resulting settings in the EEPROM. Extremely low overall temperature drift is possible with this method. The
Xicor evaluation board contains the circuitry necessary
to implement this control.
For more detailed operation see Xicor’s application
note AN154 on Xicor’s website at www.xicor.com.
Layout Considerations
The crystal input at X1 has a very high impedance and
will pick up high frequency signals from other circuits
on the board. Since the X2 pin is tied to the other side
of the crystal, it is also a sensitive node. These signals
can couple into the oscillator circuit and produce double clocking or mis-clocking, seriously affecting the
accuracy of the RTC. Care needs to be taken in layout
of the RTC circuit to avoid noise pickup. Below in Figure 15 is a suggested layout for the X1226 or X1227
devices.
Figure 15. Suggested Layout for Xicor RTC in SO-8
The X1 and X2 connections to the crystal are to be
kept as short as possible. A thick ground trace around
the crystal is advised to minimize noise intrusion, but
ground near the X1 and X2 pins should be avoided as
it will add to the load capacitance at those pins. Keep in
mind these guidelines for other PCB layers in the vicinity of the RTC device. A small decoupling capacitor at
the Vcc pin of the chip is mandatory, with a solid connection to ground.
For other RTC products, the same rules stated above
should be observed, but adjusted slightly since the
packages and pinouts are slightly different.
Assembly
Most electronic circuits do not have to deal with
assembly issues, but with the RTC devices assembly
includes insertion or soldering of a live battery into an
unpowered circuit. If a socket is soldered to the board,
and a battery is inserted in final assembly, then there
are no issues with operation of the RTC. If the battery
is soldered to the board directly, then the RTC device
Vback pin will see some transient upset from either soldering tools or intermittent battery connections which
can stop the circuit from oscillating. Once the battery is
soldered to the board, the only way to assure the circuit
will start up is to momentarily (very short period of
time!) short the Vback pin to ground and the circuit will
begin to oscillate.
REV 1.1.20 1/13/03
Oscillator Measurements
When a proper crystal is selected and the layout guidelines above are observed, the oscillator should start up
in most circuits in less than one second. Some circuits
may take slightly longer, but startup should definitely
occur in less than 5 seconds. When testing RTC circuits, the most common impulse is to apply a scope
probe to the circuit at the X2 pin (oscillator output) and
observe the waveform. DO NOT DO THIS! Although in
some cases you may see a useable waveform, due to
the parasitics (usually 10pF to ground) applied with the
scope probe, there will be no useful information in that
waveform other than the fact that the circuit is oscillating. The X2 output is sensitive to capacitive impedance
so the voltage levels and the frequency will be affected
www.xicor.com
Characteristics subject to change without notice. 22 of 28
Page 23
X1227
by the parasitic elements in the scope probe. Applying
a scope probe can possibly cause a faulty oscillator to
start up, hiding other issues (although in the Xicor
RTC’s, the internal circuitry assures startup when
using the proper crystal and layout). The best way to
analyze the RTC circuit is to power it up and read the
real time clock as time advances.
Backup Battery Operation
Many types of batteries can be used with the Xicor
RTC products. 3.0V or 3.6V Lithium batteries are
appropriate, and sizes are available that can power a
Xicor RTC device for up to 10 years. Another option is
to use a supercapacitor for applications where Vcc may
disappear intermittently for short periods of time.
Depending on the value of supercapacitor used,
backup time can last from a few days to two weeks
(with >1F). A simple silicon or Schottky barrier diode
can be used in series with Vcc to charge the supercapacitor, which is connected to the Vback pin. Do not
use the diode to charge a battery (especially lithium
batteries!).
Figure 16. Supercapacitor charging circuit
2.7-5.5V
V
CC
V
back
Supercapacitor
V
SS
Since the battery switchover occurs at Vcc=Vback-
0.1V (see Figure 16), the battery voltage must always
be lower than the Vcc voltage during normal operation
or the battery will be drained. A second consideration
is the trip point setting for the system RESET- function,
known as Vtrip. Vtrip is set at the factory at levels for
systems with either Vcc = 5V or 3.3V operation, with
the following standard options:
V
= 4.63V ± 3%
TRIP
V
= 4.38V ± 3%
TRIP
V
= 2.85V ± 3%
TRIP
V
= 2.65V ± 3%
TRIP
The summary of conditions for backup battery operation is given in Table 8:
Table 8. Battery Backup Operation
1. Example Application, Vcc=5V, Vback=3.0V
Condition Vcc Vback Vtrip Iback Reset Notes
a. Normal Operation 5.00 3.00 4.38 <<1µA H
b. Vcc on with no battery 5.00 0 4.38 0 H
c. Backup Mode 0–1.8 1.8-3.0 4.38 <2µA L
2. Example Application, Vcc=3.3V,Vback=3.0V
Condition Vcc Vback Vtrip Iback Reset
a. Normal Operation 3.30 3.00 2.65 <<1µA H
b. Vcc on with no battery 3.30 0 2.65 0 H
c. Backup Mode 0–1.8 1.8–3.0* 2.65 <2µA* L
d. UNWANTED - Vcc ON, Vback
powering
*since Vback>2.65V is higher than Vtrip, the battery is powering the entire device
2.65 - 3.30 > Vcc 2.65 up to 3mA H
Timekeeping
only
Timekeeping
only
Internal
Vcc=Vback
REV 1.1.20 1/13/03
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Characteristics subject to change without notice. 23 of 28
Page 24
X1227
Referring to Figure 16, Vtrip applies to the “Internal
Vcc” node which powers the entire device. This means
that if Vcc is powered down and the battery voltage at
Vback is higher than the Vtrip voltage, then the entire
chip will be running from the battery. If Vback falls to
lower than Vtrip, then the chip shuts down and all outputs are disabled except for the oscillator and timekeeping circuitry. The fact that the chip can be powered
from Vback is not necessarily an issue since standby
current for the RTC devices is <2µA for this mode
(called “main timekeeping current” in the data sheet).
Only when the serial interface is active is there an
increase in supply current, and with Vcc powered
down, the serial interface will most likely be inactive.
One way to prevent operation in battery backup mode
above the Vtrip level is to add a diode drop (silicon
diode preferred) to the battery to insure it is below
Vtrip. This will also provide reverse leakage protection
which may be needed to get safety agency approval.
One mode that should always be avoided is the operation of the RTC device with Vback greater than both
Vcc and Vtrip (Condition 2d in Table 8). This will cause
the battery to drain quickly as serial bus communication and non-volatile writes will require higher supplier
current.
PERFORMANCE DATA
Performance
I
BACK
I
BACK
1.4
1.2
1.0
0.8
(µA)
0.6
BACK
I
0.4
0.2
0
Multi-Lot Process Variation Data
-40 25 60 85
Temperature °C
vs. Temperature
3.3V
1.8V
REV 1.1.20 1/13/03
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Characteristics subject to change without notice. 24 of 28
Page 25
X1227
PACKAGING INFORMATION
8-Lead Plastic, SOIC, Package Code S8
Pin 1 Index
(4X) 7°
0.050 (1.27)
0.010 (0.25)
0.020 (0.50)
Pin 1
X 45°
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
0.150 (3.80)
0.158 (4.00)
0.004 (0.19)
0.010 (0.25)
0.228 (5.80)
0.244 (6.20)
0.053 (1.35)
0.069 (1.75)
0.050"Typical
0° - 8°
REV 1.1.20 1/13/03
0.0075 (0.19)
0.010 (0.25)
0.016 (0.410)
0.037 (0.937)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
www.xicor.com
0.250"
Characteristics subject to change without notice. 25 of 28
0.030"
Typical
8 PlacesFOOTPRINT
0.050"
Typical
Page 26
X1227
PACKAGING INFORMATION
8-Lead Plastic, TSSOP, Package Code V8
.025 (.65) BSC
0° – 8°
.019 (.50)
.029 (.75)
Detail A (20X)
.114 (2.9)
.122 (3.1)
.0075 (.19)
.0118 (.30)
.010 (.25)
.169 (4.3)
.177 (4.5)
.002 (.05)
.006 (.15)
Gage Plane
Seating Plane
.252 (6.4) BSC
.047 (1.20)
(4.16)
(7.72)
See Detail “A”
REV 1.1.20 1/13/03
(1.78)
.031 (.80)
.041 (1.05)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
www.xicor.com
(0.42)
All Measurements Are Typical
Characteristics subject to change without notice. 26 of 28
(0.65)
Page 27
X1227
ORDERING INFORMATION
VCC Range V
TRIP
Package Operating Temperature Range Part Number
2.7 – 5.5V 4.63V ± 112mV 8L SOIC 0–70°C X1227S8-4.5A
-40–85°C X1227S8I-4.5A
2.7 – 5.5V 4.63V ± 112mV 8L TSSOP 0–70°C X1227V8-4.5A
-40–85°C X1227V8I-4.5A
2.7 – 5.5V 4.38V ± 112mV 8L SOIC 0–70°C X1227S8
-40–85°C X1227S8I
2.7 – 5.5V 4.38V ± 112mV 8L TSSOP 0–70°C X1227V8
-40–85°C X1227V8I
2.7 – 5.5V 2.85V ± 100mV 8L SOIC 0–70°C X1227S8-2.7A
-40–85°C X1227S8I-2.7A
2.7 – 5.5V 2.85V ± 100mV 8L TSSOP 0–70°C X1227V8-2.7A
-40–85°C X1227V8I-2.7A
2.7 – 5.5V 2.65V ± 100mV 8L SOIC 0–70°C X1227S8-2.7
-40–85°C X1227S8I-2.7
2.7 – 5.5V 2.65V ± 100mV 8L TSSOP 0–70°C X1227V8-2.7
-40–85°C X1227V8I-2.7
Note: For appropriate volume, any V
value from 2.6 to 4.7V may be ordered via Xicor’s Customer Specification Program (CSPEC).
TRIP
REV 1.1.20 1/13/03
www.xicor.com
Characteristics subject to change without notice. 27 of 28
Page 28
X1227
PART MARK INFORMATION
8-Lead TSSOP
YWW
XXXXX
1227AL = 4.5 to 5.5V, 0 to +70°C, V
1227AM = 4.5 to 5.5V, -40 to +85°C, V
1227 = 4.5 to 5.5V, 0 to +70°C, V
1227I = 4.5 to 5.5V, -40 to +85°C, V
TRIP
TRIP
1227AN = 2.7 to 5.5V, 0 to +70°C, V
1227AP = 2.7 to 5.5V, -40 to +85°C, V
1227F = 2.7 to 5.5V, 0 to +70°C, V
TRIP
1227G = 2.7 to 5.5V, -40 to +85°C, V
8-Lead SOIC
X1227 X
Blank = 8-Lead SOIC
XX
AL = 4.5 to 5.5V, 0 to +70°C, V
AM = 4.5 to 5.5V, -40 to +85°C, V
Blank = 4.5 to 5.5V, 0 to +70°C, V
I = 4.5 to 5.5V, -40 to +85°C, V
AN = 2.7 to 5.5V, 0 to +70°C, V
AP = 2.7 to 5.5V, -40 to +85°C, V
F = 2.7 to 5.5V, 0 to +70°C, V
G = 2.7 to 5.5V, -40 to +85°C, V
= 4.63V ± 112mV
TRIP
TRIP
TRIP
= 4.38V ± 112mV
TRIP
= 2.85V ± 100mV
TRIP
TRIP
= 2.65V ± 100mV
TRIP
TRIP
= 4.63V ± 112mV
TRIP
= 4.63V ± 112mV
TRIP
= 4.38V ± 112mV
= 4.38V ± 112mV
= 2.85V ± 100mV
TRIP
= 2.85V ± 100mV
TRIP
= 2.65V ± 100mV
= 2.65V ± 100mV
TRIP
= 4.63V ± 112mV
= 4.38V ± 112mV
= 2.85V ± 100mV
= 2.65V ± 100mV
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
COPYRIGHTS AND TRADEMARKS
2
Xicor, Inc., the Xicor logo, E
2
KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are
E
used for identification purposes only, and are trademarks or registered trademarks of their respective holders.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
REV 1.1.20 1/13/03
POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM,
www.xicor.com
Characteristics subject to change without notice. 28 of 28
©Xicor, Inc. 2003 Patents Pending
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