Datasheet WS512K16-25FLIA, WS512K16-25FLI, WS512K16-25FLCA, WS512K16-25FLC, WS512K16-25DLMA Datasheet (White Electronic Designs)

White Microelectronics • Phoenix, AZ • [phone]

3

SRAM MONOLITHICS

1

512Kx16 SRAM MODULE

ADVANCED*

FEATURES

■ Access Times 17, 20, 25, 35ns

■ MIL-STD-883 Compliant Devices Available

■ Packaging

•44 pin Ceramic SOJ (Package 102)

•44 lead Ceramic Flatpack (Package 209)

■ Organized as two banks of 256Kx16

■ Data Byte Control:

Lower Byte (LB) = I/O

1-8

Upper Byte (UB) = I/O9-16

■ Data I/O Compatible with 3.3V devices

■ 2V Minimum Data Retention for battery back up operation

■ Commercial, Industrial and Military Temperature Range

■ 5 Volt Power Supply (3.3V parts also available)

■ Low Power CMOS

■ TTL Compatible Inputs and Outputs

* This data sheet describes a product that may or may not be under

development and is subject to change or cancellation without notice.

PIN CONFIGURATION FOR WS512K16-XXX

A0-17 Address Inputs

LB Lower-Byte Control (I/O1-8)
UB Upper-Byte Control (I/O9-16)

I/O1-16 Data Input/Output

CS1-2 Chip Select

OE Output Enable
WE Write Enable
VCC +5.0V Power

GND Ground

NC No Connection

PIN DESCRIPTION

44 CSOJ
44 FLATPACK

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

A0
A1
A2
A3

A4
CS1
I/O1
I/O2
I/O3
I/O4

V

CC

GND

I/O5
I/O6
I/O7
I/O8

WE

A5

A6

A7

A8

A9

A17
A16
A15
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
GND
V

CC

I/O12
I/O11
I/O10
I/O9
CS2
A14
A13
A12
A11
A10

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

WS512K16-XXX

April 1998

TOP VIEW

BLOCK DIAGRAM

256K x 16

256K x 16

UB

OE

WE

CS

1

CS

2

I/O

1-16

A

0-17

LB

2

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SRAM MONOLITHICS

WS512K16-XXX

TRUTH TABLE

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Min Max Unit

Operating Temperature T

A -55 +125 °C

Storage Temperature T

STG -65 +150 °C

Signal Voltage Relative to GND V

G -0.5 Vcc+0.5 V

Junction Temperature T

J 150 °C

Supply Voltage V

CC -0.5 7.0 V

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Max Unit

Supply Voltage V

CC 4.5 5.5 V

Input High Voltage V

IH 2.2 VCC + 0.3 V

Input Low Voltage V

IL -0.3 +0.8 V

Operating Temp. (Mil.) T

A -55 +125 °C

Parameter

Symbol

Condition Max Unit

Input capacitance CIN

VIN = 0V, f = 1.0MHz

25 pF

Output capicitance C

OUT

V

OUT

= 0V, f = 1.0MHz

25 pF

This parameter is guaranteed by design but not tested.

CAPACITANCE

(T

A = +25°C)

DC CHARACTERISTICS

(V

CC

= 5.0V, GND = 0V, TA = -55°C to +125°C)

Parameter Sym Conditions Units

Min Max

Input Leakage Current ILI VCC = 5.5, VIN = GND to VCC 10 µA
Output Leakage Current ILO CS = VIH, OE = VIH, VOUT = GND to VCC 10 µA
Operating Supply Current ICC CS = VIL, OE = VIH, f = 5MHz, Vcc = 5.5 290 mA
Standby Current ISB CS = VIH, OE = VIH, f = 5MHz, Vcc = 5.5 30 mA
Output Low Voltage VOL IOL = 8mA, VCC = 4.5 0.4 V
Output High Voltage V

OH IOH = -4.0mA, VCC = 4.5 2.4 V

NOTE: DC test conditions: V

IH = VCC -0.3V, VIL = 0.3V

Parameter Symbol Conditions Units

Min Typ Max

Data Retention Supply Voltage V

DR CS ≥ VCC -0.2V 2.0 5.5 V

Data Retention Current I

CCDR1 VCC = 3V 2.0 12.0* mA

* Also available in Low Power version. Please call factory for informaion.

DATA RETENTION CHARACTERISTICS

(TA = -55°C to +125°C)

CS1 CS2 WE OE LB UB Mode Data I/O Power

I/O1-8 I/O9-16

H H X X X X Not Select High Z High Z Standby
LH
HL

Output Disable High Z High Z Active

LH
HL

L H Data Out High Z

H L H L Read High Z Data Out Active

L L Data Out Data Out
L H Data In High Z

L X H L Write High Z Data In Active

L L Data In Data In

HH X X

XX H H

HL
LH

HL
LH

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3

SRAM MONOLITHICS

3

WS512K16-XXX

I

Current Source

D.U.T.

C = 50 pf

eff

I

OL

V ≈ 1.5V
(Bipolar Supply)

Z

Current Source

OH

NOTES:

V

Z is programmable from -2V to +7V.

I

OL & IOH programmable from 0 to 16mA.

Tester Impedance Z

0 = 75 Ω.

V

Z is typically the midpoint of VOH and VOL.

I

OL & IOH

are adjusted to simulate a typical resistive load circuit.

ATE tester includes jig capacitance.

AC TEST CIRCUIT

AC TEST CONDITIONS

Parameter Typ Unit

Input Pulse Levels VIL = 0, VIH = 3.0 V
Input Rise and Fall 5 ns
Input and Output Reference Level 1.5 V
Output Timing Reference Level 1.5 V

AC CHARACTERISTICS

(VCC = 5.0V, GND = 0V, TA = -55°C to +125°C)

Parameter Symbol -17 -20 -25 -35 Units
Read Cycle Min Max Min Max Min Max Min Max

Read Cycle Time tRC 17 20 25 35 ns
Address Access Time tAA 17 20 25 35 ns
Output Hold from Address Change tOH 0000ns
Chip Select Access Time tACS 17 20 25 35 ns
Output Enable to Output Valid tOE 10 12 15 20 ns
Chip Select to Output in Low Z tCLZ

1

2555ns

Output Enable to Output in Low Z tOLZ

1

0000ns

Chip Disable to Output in High Z tCHZ

1

9101215ns

Output Disable to Output in High Z tOHZ

1

9101215ns
LB, UB Access Time tBA 10 12 14 17 ns
LB, UB Enable to Low Z Output tBLZ

1

0000ns

LB, UB Disable to High Z Output t

BHZ

1

9101215ns

1. This parameter is guaranteed by design but not tested.

AC CHARACTERISTICS

(VCC = 5.0V, GND = 0V, TA = -55°C to +125°C)

Parameter Symbol -17 -20 -25 -35 Units
Write Cycle Min Max Min Max Min Max Min Max

Write Cycle Time tWC 17 20 25 35 ns
Chip Select to End of Write tCW 14 17 20 25 ns
Address Valid to End of Write tAW 14 17 20 25 ns
Data Valid to End of Write tDW 10 12 15 20 ns
Write Pulse Width tWP 14 17 20 25 ns
Address Setup Time tAS 0000ns
Address Hold Time tAH 0000ns
Output Active from End of Write tOW

1

0000ns

Write Enable to Output in High Z t WHZ

1

9101015ns
Data Hold Time tDH 0000ns
LB, UB Valid to End of Write t

BW 14 17 20 25 ns

1. This parameter is guaranteed by design but not tested.

4

White Microelectronics • Phoenix, AZ • [phone]

3

SRAM MONOLITHICS

WS32K32-XHX

TIMING WAVEFORM - READ CYCLE

WRITE CYCLE - CS CONTROLLED

WRITE CYCLE - WE CONTROLLED

ADDRESS

DATA I/O

READ CYCLE 1 (CS = OE = V

IL

, UB or LB = VIL, WE = VIH)

t

AA

t

OH

t

RC

DATA VALIDPREVIOUS DATA VALID

ADDRESS

DATA I/O

READ CYCLE 2 (WE = V

IH

)

t

AA

t

ACS

t

OE

t

CLZ

t

OLZ

t

OHZ

t

RC

DATA VALID

HIGH IMPEDANCE

CS

OE

t

CHZ

LB, UB

t

BHZ

t

BA

t

BLZ

ADDRESS

DATA I/O

WRITE CYCLE 1, WE CONTROLLED

t

AW

t

CW

t

AH

t

WP

t

DW

t

WHZ

t

AS

t

OW

t

DH

t

WC

DATA VALID

CS

WE

t

BW

LB, UB

ADDRESS

DATA I/O

WRITE CYCLE 2, CS CONTROLLED

t

AW

t

AS

t

CW

t

AH

t

WP

t

DH

t

DW

t

WC

CS

WE

DATA VALID

t

BW

LB, UB

WRITE CYCLE - LB, UB CONTROLLED

ADDRESS

DATA I/O

WRITE CYCLE 3, LB, UB CONTROLLED

t

AW

t

AS

t

CW

t

AH

t

WP

t

DH

t

DW

t

WC

CS

WE

DATA VALID

t

BW

LB, UB

WS512K16-XXX

White Microelectronics • Phoenix, AZ • [phone]

3

SRAM MONOLITHICS

5

PACKAGE 209: 44 LEAD, CERAMIC FLAT PACK

ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES

28.45 (1.120)

± 0.26 (0.010)

12.95 (0.510)

± 0.13 (0.005)

3.18 (0.125)
MAX

0.13 (0.005)
± 0.05 (0.002)

PIN 1
IDENTIFIER

1.27 (0.050) TYP

9.90 (0.390)
± 0.13 (0.005)

26.67 (1.050) TYP

10.16 (0.400)
± 0.51 (0.020)

0.43 (0.017)
± 0.05 (0.002)

ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES

PACKAGE 102: 44 LEAD, CERAMIC SOJ

1.27 (0.050) TYP

28.70 (1.13) ± 0.25 (0.010)

PIN 1 IDENTIFIER

26.7 (1.050) TYP

11.3 (0.446)

± 0.2 (0.009)

3.96 (0.156) MAX

0.2 (0.008)

± 0.05 (0.002)

9.55 (0.376) ± 0.25 (0.010)

1.27 (0.050) ± 0.25 (0.010)

0.89 (0.035)
Radius TYP

WS512K16-XXX

6

White Microelectronics • Phoenix, AZ • [phone]

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SRAM MONOLITHICS

ORDERING INFORMATION

LEAD FINISH:

Blank = Gold plated leads
A = Solder dip leads

DEVICE GRADE:

M= Military Screened -55°C to +125°C
I = Industrial -40°C to +85°C
C = Commercial 0°C to +70°C

PACKAGE:

DL = 44 Lead Ceramic SOJ (Package 102)
FL = 44 Lead Ceramic Flatpack (Package 209)

ACCESS TIME (ns)

ORGANIZATION, two banks of 256K x 16

SRAM

WHITE MICROELECTRONICS

WS512K16-XXX

W S 512K16 - XX X X X