Datasheet WS256K64-35G4WM, WS256K64-35G4WI, WS256K64-35G4WC, WS256K64-25G4WM, WS256K64-25G4WC Datasheet (White Electronic Designs)

WS256K64-XG4WX

256Kx64 SRAM MODULE

ADVANCED*

FEATURES

■ Access Times 20, 25, 35ns

■ MIL-STD-883 Compliant Devices Available

■ Packaging:

•116 lead, 40mm, Hermetic CQFP (Package 504)

■ Organized as 256Kx64, User Configurable as 512Kx32 or

1Mx16.

■ Data I/O Compatible with 3.3V devices

■ 2V Data Retention devices available

■ Commercial, Industrial and Military Temperature Range

■ 5 Volt Power Supply

■ Low Power CMOS

■ TTL Compatible Inputs and Outputs

■ Weight

* This data sheet describes a product that may or may not be under

FIG. 1 PIN CONFIGURATION FOR WS256K64-XG4WX

TOP VIEW

I/O2

I/O1

I/O0

I/O3
I/O4
I/O5
I/O6
I/O7

GND

I/O

I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
GND
I/O
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O
I/O25
I/O26
I/O27
I/O28

VCCNCNCNCA0A1A2A3A4WE1

1514131211
16
17
18
19
20
21
22

8

23
24
25
26
27
28
29
30
31

16

32
33
34
35
36
37
38
39
40

24

41
42
43
44

4546474849505152535455565758596061626364656667686970717273

987654321

10

CS1NCNCNCA5A6A7A8A9NC

116

115

114

113

112

111

110

109

CS4WE4

108

107

VCC

106

I/O63

105

I/O62

104

102
101
100

I/O61

103

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74

WS256K64-XG4WX - 20 grams typical

development and is subject to change or cancellation without notice.

BLOCK DIAGRAM

A

I/O60
I/O59
I/O58
I/O57
I/O56
GND
I/O
I/O54
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
GND
I/O
I/O46
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40
GND
I/O
I/O38
I/O37
I/O36
I/O35

0-17

55

47

39

WE

256K x 16

16

I/O

0-15

1

OE

WE

CS

1

256K x 16

16

I/O

16-31

CS

2

2

PIN DESCRIPTION

I/O0-63 Data Inputs/Outputs

A0-17 Address Inputs

WE1-4 Write Enables

CS1-4 Chip Selects

OE Output Enable

VCC Power Supply

GND Ground

WE

256K x 16

16

I/O

32-47

CS

3

WE

3

256K x 16

16

I/O

48-63

4

CS

4

4

SRAM MODULES

September 1998

NCNCNC

CS2

VCC

WE2

I/O29

I/O30

I/O31

NC

NC

A17

OE

A16

A15

A14

A13

A12

CS3

A11

WE3

NCNCNC

A10

CC

V

I/O32

I/O33

I/O34

1

White Microelectronics • Phoenix, AZ • [phone]

WS256K64-XG4WX

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Min Max Unit

Operating Temperature T
Storage Temperature T
Signal Voltage Relative to GND V
Junction Temperature T
Supply Voltage V

A -55 +125 °C

STG -65 +150 °C

G -0.5 Vcc + 0.5 V

J 150 °C

CC -0.5 7.0 V

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Max Unit

Supply Voltage V
Input High Voltage V
Input Low Voltage V
Operating Temp. (Mil.) T

CC 4.5 5.5 V
IH 2.2 VCC + 0.3 V

IL -0.3 +0.8 V
A -55 +125 °C

4

SRAM MODULES

(VCC = 5.0V, GND = 0V, TA = -55°C to +125°C)

Parameter Sym Conditions Units

Input Leakage Current ILI VCC = 5.5, VIN = GND to VCC 10 µA
Output Leakage Current ILO CS = VIH, OE = VIH, VOUT = GND to VCC 10 µA
Operating Supply Current ICC CS = VIL, OE = VIH, f = 5MHz, Vcc = 5.5 920 mA
Standby Current ISB CS = VIH, OE = VIH, f = 5MHz, Vcc = 5.5 68 mA
Output Low Voltage VOL IOL = 8mA, VCC = 4.5 0.4 V
Output High Voltage V

NOTE: DC test conditions: V

IH = VCC -0.3V, VIL = 0.3V

OH IOH = -4.0mA, VCC = 4.5 2.4 V

CS OE WE Mode Data I/O Power

H X X Standby High Z Standby
L L H Read Data Out Active
L X L Write Data In Active
L H H Out Disable High Z Active

Parameter Symbol Condition Max Unit

Output Enable Capacitance COE VIN = 0V, f = 1.0MHz 50 pF
Write Enable Capacitance CWE VIN = 0V, f = 1.0MHz 20 pF
Chip Select Capacitance CCS VIN = 0V, f = 1.0MHz 20 pF
Data I/OCapacitance C

Address Input Capacitance CAD VIN = OV, f = 1.OMHZ 50 pF
This parameter is guaranteed by design but not tested.

DC CHARACTERISTICS

TRUTH TABLE

CAPACITANCE

(TA = +25°C)

I/O VIN = 0V, f = 1.0MHz 20 pF

Min Max

White Microelectronics • Phoenix, AZ • [phone]

2

WS256K64-XG4WX

AC CHARACTERISTICS

CC

= 5.0V, GND = 0V, TA = -55°C to +125°C)

(V

Parameter Symbol -20 -25 -35 Units
Read Cycle Min Max Min Max Min Max

Read Cycle Time tRC 20 25 35 ns
Address Access Time tAA 20 25 35 ns
Output Hold from Address Change tOH 000 ns
Chip Select Access Time tACS 20 25 35 ns
Output Enable to Output Valid tOE 12 15 20 ns
Chip Select to Output in Low Z t CLZ
Output Enable to Output in Low Z tOLZ
Chip Disable to Output in High Z tCHZ
Output Disable to Output in High Z tOHZ

1. This parameter is guaranteed by design but not tested.

1

1

1

1

555 ns
000 ns

12 15 15 ns
12 15 15 ns

AC CHARACTERISTICS

CC

= 5.0V, GND = 0V, TA = -55°C to +125°C)

(V

4

SRAM MODULES

Parameter Symbol -20 -25 -35 Units
Write Cycle Min Max Min Max Min Max

Write Cycle Time tWC 20 25 35 ns
Chip Select to End of Write tCW 17 20 25 ns
Address Valid to End of Write tAW 17 20 25 ns
Data Valid to End of Write tDW 12 15 20 ns
Write Pulse Width tWP 17 20 25 ns
Address Setup Time tAS 000ns
Address Hold Time tAH 222ns
Output Active from End of Write tOW
Write Enable to Output in High Z tWHZ
Data Hold Time t

1

1

DH 000ns

000ns

10 10 15 ns

1. This parameter is guaranteed by design but not tested.

FIG. 2

AC TEST CIRCUIT

Current Source

I

OL

AC TEST CONDITIONS

Parameter Typ Unit

Input Pulse Levels VIL = 0, VIH = 3.0 V
Input Rise and Fall 5 ns
Input and Output Reference Level 1.5 V

D.U.T.

C = 50 pf

eff

Current Source

I

OH

V ≈ 1.5V

Z

(Bipolar Supply)

Output Timing Reference Level 1.5 V

NOTES:

V

Z is programmable from -2V to +7V.

OL & IOH programmable from 0 to 16mA.

I
Tester Impedance Z
V

Z is typically the midpoint of VOH and VOL.

OL & IOH

are adjusted to simulate a typical resistive load circuit.

I
ATE tester includes jig capacitance.

0 = 75 Ω.

3

White Microelectronics • Phoenix, AZ • [phone]

FIG. 3

TIMING WAVEFORM - READ CYCLE

t

ADDRESS

t

DATA I/O

RC

t

AA

OH

WS256K64-XG4WX

t

ADDRESS

CS

OE

DATA VALIDPREVIOUS DATA VALID

DATA I/O

HIGH IMPEDANCE

RC

t

AA

t

t

CHZ

OHZ

t

ACS

t

CLZ

t

OE

t

OLZ

DATA VALID

READ CYCLE 1 (CS = OE = V

4

FIG. 4

SRAM MODULES

WRITE CYCLE - WE CONTROLLED

FIG. 5

WRITE CYCLE - CS CONTROLLED

ADDRESS

DATA I/O

ADDRESS

CS

WE

CS

, WE = VIH)

IL

t

t

WC

t

AW

t

CW

t

AS

WRITE CYCLE 1, WE CONTROLLED

t

WHZ

t

WP

t

WC

WS32K32-XHX

t

AS

AW

t

CW

t

DW

DATA VALID

READ CYCLE 2 (WE = V

t

AH

t

OW

t

DH

t

AH

)

IH

White Microelectronics • Phoenix, AZ • [phone]

WE

DATA I/O

t

WP

WRITE CYCLE 2, CS CONTROLLED

4

t

DW

DATA VALID

t

DH

WS256K64-XG4WX

PACKAGE 504: 116 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G4W)

39.6 (1.56) ± 0.38 (0.015) SQ

PIN 1 IDENTIFIER

Pin 1

12.7 (0.500)
± 0.5 (0.020)

4 PLACES

5.1 (0.200)

± 0.25 (0.010)

4 PLACES

4 PLACES

0.38 (0.015)

± 0.08 (0.003)

68 PLACES

ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES

ORDERING INFORMATION

1.27 (0.050)
REF

38 (1.50) REF

5.1 (0.200) MAX

1.27 (0.050)
± 0.1 (0.005)

0.25 (0.010)

± 0.05 (0.002)

4

SRAM MODULES

W S 256K64 - XXX G4W X

DEVICE GRADE:

M = Military Screened -55°C to +125°C
I = Industrial -40°C to +85°C
C = Commercial 0°C to +70°C

PACKAGE:

G4W = 116 Lead 40mm Ceramic Quad Flat Pack, CQFP (Package 504)

ACCESS TIME (ns)

ORGANIZATION, 256K x 64

User configurable as 1M x 16 or 512K x 32

SRAM

WHITE MICROELECTRONICS

5

White Microelectronics • Phoenix, AZ • [phone]