Datasheet WS1M32-17H2I, WS1M32-17H2CA, WS1M32-17H2C, WS1M32-17G3MA, WS1M32-17G3M Datasheet (White Electronic Designs)

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White Electronic Designs

WS1M32-XXX

1Mx32 SRAM MODULE

FEATURES

■ Access Times of 17, 20, 25ns

■ Packaging

 84 lead, 28mm CQFP, (Package 511)

 66 pin PGA Type, 1.385" sq., Hermetic Ce-

ramic HIP (Package 402)*

■ Organized as two banks of 512Kx32, User
Configurable as 2Mx16 or 4Mx8

* Package to be developed.

■ Commercial, Industrial and Military Temperature
Ranges

■ TTL Compatible Inputs and Outputs

■ 5 Volt Power Supply

■ Low Power CMOS

■ Built-in Decoupling Caps and Multiple Ground

Pins for Low Noise Operation

■ Weight
WS1M32-XH2X* - 13 grams (typical)
WS1M32-XG3X - 20 grams (typical)

July 2002 Rev. 4

PIN DESCRIPTION

PIN CONFIGURATION FOR WS1M32-XH2X*

I/O

8

I/O

9

I/O

10

A

13

A

14

A

15

A

16

A

17

I/O

0

I/O

1

I/O

2

WE

2

OE

2

GND

I/O

11

A

10

A

11

A

12

V

CC

CS

1

NC

I/O

3

I/O

15

I/O

14

I/O

13

I/O

12

OE

1

A

18

WE

1

I/O

7

I/O

6

I/O

5

I/O

4

I/O

24

I/O

25

I/O

26

A

6

A

7

CS

2

A

8

A

9

I/O

16

I/O

17

I/O

18

V

CC

OE

4

WE

4

I/O

27

A

3

A

4

A

5

WE

3

OE

3

GND

I/O

19

I/O

31

I/O

30

I/O

29

I/O

28

A

0

A

1

A

2

I/O

23

I/O

22

I/O

21

I/O

20

11 22 33 44 55 66

1 12 23 34 45 56

BLOCK DIAGRAM

TOP VIEW

I/O0-31 Data Inputs/Outputs

A0-18 Address Inputs

WE 1-4 Write Enables

CS1-2 Chip Selects

OE1-4 Output Enable

VCC Power Supply

GND Ground

NC Not Connected

8

I/O0-7

CS1

I/O8-15

CS2

I/O16-23 I/O24-31

A0-18

WE1

8

2M x 8

8

512K x 8

8

512K x 8

2M x 8

512K x 8

512K x 8

2M x 8

512K x 8

512K x 8

2M x 8

512K x 8

512K x 8

OE1

WE2

OE2

WE3

OE3

WE4

OE4

NOTE: CS1& CS2 are used as bank select

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WS1M32-XXX

PIN CONFIGURATION FOR WS1M32-XG3X

TOP VIEW

BLOCK DIAGRAM

8

I/O0-7

CS1

I/O8-15

CS2

I/O16-23 I/O24-31

A0-18

WE1

8

2M x 8

8

512K x 8

8

512K x 8

2M x 8

512K x 8

512K x 8

2M x 8

512K x 8

512K x 8

2M x 8

512K x 8

512K x 8

OE1

WE2

OE2

WE3

OE3

WE4

OE4

NOTE: CS1& CS2 are used as bank select

1.146"

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

9

V

CC

A

0

A

1

A

2

A

3

A

4

A

5

A

6

OE

1

OE

2

OE

3

OE

4

NC

A

7

A

8

A

9

A

10

A

11

A

12

A

13

GND

V

CC

I/O0I/O1I/O2I/O3I/O4I/O5I/O6I/O

7CS1

NC

CS

2

I/O8I/O

9

I/O10I/O11I/O12I/O13I/O14I/O

15

GND

GND

NC

NC

NC

NC

NC

NC

NC

NC

WE

4

WE

3

WE

2

WE

1

NC

NC

A

18

A

17

A

16

A

15

A

14

V

CC

GND

I/O31I/O30I/O29I/O28I/O27I/O26I/O25I/O24NCNCNC

I/O23I/O22I/O21I/O20I/O19I/O18I/O17I/O16V

CC

876543 184838281807978772

37

38 39 40 41 42 43 45 46 47 48 49 50 51 52 5344

76 75

11

10

33

34 35 36

The WEDC 84 lead G3 CQFP fills
the same fit and function as the
JEDEC 84 lead CQFJ or 84
PLCC. But the G3 has the TCE
and lead inspection advantage of
the CQFP form.

PIN DESCRIPTION

I/O0-31 Data Inputs/Outputs

A0-18 Address Inputs

WE 1-4 Write Enables

CS1-2 Chip Selects

OE1-4 Output Enables

VCC Power Supply

GND Ground

NC Not Connected

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WS1M32-XXX

Parameter

Symbol

Conditions Max Unit

OE1-4 capacitance COE

VIN = 0 V, f = 1.0 MHz

30 pF

WE1-4 capacitance CWE

VIN = 0 V, f = 1.0 MHz

30 pF

CS1-2 capacitance CCS

VIN = 0 V, f = 1.0 MHz

30 pF

Data I/O capacitance CI/O

V

I/O

= 0 V, f = 1.0 MHz

30 pF

Address input capacitance C

ADVIN

= 0 V, f = 1.0 MHz

75 pF

This parameter is guaranteed by design but not tested.

Parameter Symbol Min Max Unit

Operating Temperature T

A -55 +125 °C

Storage Temperature T

STG -65 +150 °C

Signal Voltage Relative to GND V

G -0.5 Vcc + 0.5 V

Junction Temperature TJ 150 °C

Supply Voltage V

CC -0.5 7.0 V

ABSOLUTE MAXIMUM RATINGS

CAPACITANCE

(T

A = +25°C)

TRUTH TABLE

CS1 CS2 OE WE Mode Data I/O Power

H H X X Standby High Z Standby
LHLH ReadData OutActive
L H H H Out Disable High Z Active
L H X L Write Data In Active
HLLH ReadData OutActive
H L H H Out Disable High Z Active
H L X L Write Data In Active
L L X X In va lid Stat e Invalid State Invalid State

Parameter Symbol Conditions Units

Min Max

Input Leakage Current ILI VCC = 5.5, VIN = GND to VCC 10 µA

Output Leakage Current ILO CS = VIH, OE = VIH, VOUT = GND to VCC 10 µA

Operating Supply Current x 32 Mode ICC x 32 CS = VIL, OE = VIH, f = 5MHz, Vcc = 5.5 720 mA

Standby Current ISB CS = VIH, OE = VIH, f = 5MHz, Vcc = 5.5 120 mA

Output Low Voltage VOL IOL = 8mA, Vcc = 4.5 0.4 V

Output High Voltage V

OH IOH = -4.0mA, Vcc = 4.5 2.4 V

NOTE: DC test conditions: V

IH = VCC -0.3V, VIL = 0.3V

DC CHARACTERISTICS

(VCC = 5.0V, GND = 0V, TA = -55°C to +125°C)

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Max Unit

Supply Voltage VCC 4.5 5.5 V

Input High Voltage VIH 2.2 VCC + 0.3 V

Input Low Voltage VIL -0.5 +0.8 V

Operating Temp (Mil) TA -55 +125 °C

Operating Temp (Ind.) T

A -40 +85 °C

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WS1M32-XXX

Parameter Symbol -17 -20 -25 Units

Read Cycle Min Max Min Max Min Max

Read Cycle Time tRC 17 20 25 ns

Address Access Time t AA 17 20 25 ns

Output Hold from Address Change tOH 00 0ns

Chip Select Access Time tACS 17 20 25 ns

Output Enable to Output Valid tOE 10 10 12 ns

Chip Select to Output in Low Z t CLZ

1

22 2ns

Output Enable to Output in Low Z tOLZ

1

00 0ns

Chip Disable to Output in High Z tCHZ

1

12 12 12 ns

Output Disable to Output in High Z t

OHZ

1

12 12 12 ns

1. This parameter is guaranteed by design but not tested.

AC CHARACTERISTICS

(V

CC

= 5.0V, GND = 0V, TA = -55°C to +125°C)

NOTES:
V

Z is programmable from -2V to +7V.

I

OL & IOH programmable from 0 to 16mA.

Tester Impedance Z0 = 75W.
V

Z is typically the midpoint of VOH and VOL.

I

OL & IOH

are adjusted to simulate a typical resistive load circuit.

ATE tester includes jig capacitance.

I

Current Source

D.U.T.

C = 50 pf

eff

I

OL

V 1.5V

(Bipolar Supply)

Z

Current Source

OH

AC CHARACTERISTICS

(V

CC

= 5.0V, GND = 0V, TA = -55°C to +125°C)

AC TEST CONDITIONS

Parameter Typ Unit

Input Pulse Levels VIL = 0 , V IH = 3 . 0 V

Input Rise and Fall 5 ns

Input and Output Reference Level 1.5 V

Output Timing Reference Level 1.5 V

Parameter Symbol -17 -20 -25 Units

Write Cycle Min Max Min Max Min Max

Write Cycle Time tWC 17 20 25 ns

Chip Select to End of Write tCW 15 15 17 ns

Address Valid to End of Write tAW 15 15 17 ns

Data Valid to End of Write tDW 11 12 13 ns

Write Pulse Width tWP 15 15 17 ns

Address Setup Time tAS 22 2ns

Address Hold Time tAH 00 0ns

Output Active from End of Write t OW

1

23 4ns

Write Enable to Output in High Z tWHZ

1

91113ns

Data Hold Time t

DH 00 0ns

1. This parameter is guaranteed by design but not tested.

AC TEST CIRCUIT

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White Electronic Designs

WS1M32-XXX

WS32K32-XHX

TIMING WAVEFORM - READ CYCLE

WRITE CYCLE - CS CONTROLLED

WRITE CYCLE - WE CONTROLLED

ADDRESS

DATA I/O

WRITE CYCLE 2, CS CONTROLLED

t

AW

t

AS

t

CW

t

AH

t

WP

t

DH

t

DW

t

WC

CS

WE

DATA VALID

ADDRESS

DATA I/O

READ CYCLE 2 (WE = V

IH

)

t

AA

t

ACS

t

OE

t

CLZ

t

OLZ

t

OHZ

t

RC

DATA VALID

HIGH IMPEDANCE

CS

OE

t

CHZ

ADDRESS

DATA I/O

READ CYCLE 1 (CS = OE = V

IL

, WE = VIH)

t

AA

t

OH

t

RC

DATA VALIDPREVIOUS DATA VALID

ADDRESS

DATA I/O

WRITE CYCLE 1, WE CONTROLLED

t

AW

t

CW

t

AH

t

WP

t

DW

t

WHZ

t

AS

t

OW

t

DH

t

WC

DATA VALID

CS

WE

6

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WS1M32-XXX

PACKAGE 402: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H2)

35.2 (1.385) ± 0.38 (0.015) SQ

25.4 (1.0) TYP

15.24 (0.600) TYP

0.76 (0.030) ± 0.1 (0.005)

5.7 (0.223)
MAX

3.81 (0.150)

± 0.1 (0.005)

2.54 (0.100)
TYP

25.4 (1.0) TYP

1.27 (0.050) ± 0.1 (0.005)

1.27 (0.050) TYP DIA

0.46 (0.018) ± 0.05 (0.002) DIA

PIN 1 IDENTIFIER

SQUARE PAD

ON BOTTOM

ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES

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WS1M32-XXX

ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES

PACKAGE 511: 84 LEAD, CERAMIC QUAD FLAT PACK (G3)

0.38 (0.015)

± 0.05 (0.002)

4.12 (0.162) ± 0.20 (0.008)

1.27 (0.050) TYP

29.11 (1.146)
± 0.25 (0.010)

25.40 (1.000) TYP

4.29 (0.169)
± 0.28 (0.011)

0.19 (0.008)
± 0.06 (0.003)

1.02 (0.040)

± 0.12 (0.005)

0.25 (0.010)

± 0.03 (0.002)

1 / 7

R 0.127
(0.005) MIN

DETAIL A

SEE DETAIL "A"

Pin 1

0.27 (0.011)

± 0.04 (0.001)

+

30.23 (1.190) ± 0.25 (0.010) SQ

27.18 (1.070) ± 0.25 (0.010) SQ

The WEDC 84 lead G3
CQFP fills the same fit
and function as the
JEDEC 84 lead CQFJ or
84 PLCC. But the G3 has
the TCE and lead inspec­tion advantage of the
CQFP form.

1.146"

8

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WS1M32-XXX

ORDERING INFORMATION

LEAD FINISH:

Blank = Gold plated leads

A = Solder dip leads

DEVICE GRADE:

M = Military Screened -55°C to +125°C
I = Industrial -40°C to +85°C
C = Commercial 0°C to +70°C

PACKAGE TYPE:

H2 = Ceramic Hex-In-line Package, HIP (Package 402)*
G3 = 28 mm Ceramic Quad Flatpack, CQFP (Package 511)

ACCESS TIME (ns)

ORGANIZATION, two banks of 512Kx32

User configurable as 2Mx16 or 4Mx8

SRAM

WHITE ELECTRONIC DESIGNS CORP.

W S 1M32 - XX X X X

* Package to be developed.