Datasheet WM8144-10CFT-V Datasheet (Wolfson)

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Page 1

WM8144-10

October 1997 Rev. 3.0

Integrated 10-bit Data Acquisition system for

Imaging Applications

Description

WM8144-10 integrates the analogue signal conditioning required by CCD sensors with a 10-bit ADC and optional pixel-by-pixel image compensation. WM8144-10 requires minimal external circuitry and provides a cost effective sensor-to-digital domain system solution.

Each analogue conditioning channel provides reset level clamp, CDS, fine offset level shifting and gain amplification. The three channels are multiplexed into the ADC. Output from the ADC can either be direct or passed through a digital post-processing function. The postprocessing provides compensation for variations in offset and shading on a pixel-by-pixel basis.

Features

• Reset level clamp

• Correlated Double Sampling (CDS)

• Fine offset level shifting

• Programmable Gain Amplification

• 10-Bit ADC with maximum 6 MSPS

• Digital post-processing for pixel-by-pixel image compensation

• Simple clocking scheme

• Control by serial or parallel interface

• Time-multiplexed eight-bit data output mode

• 48 pin TQFP package

• Pin compatible with WM8144-12

Production Data

The flexible output architecture allows ten-bit data to be accessed either on a ten-bit bus or via a time-multiplexed eight-bit bus. The WM8144-10 can be configured for pixelby-pixel or line-by-line multiplexing operation. Reset level clamp and/or CDS features can be optionally bypassed. Device configuration is either by a simple serial or eightbit parallel interface.

Block Diagram

VSMP

TIMING CONTROL

OFFSET

RINP

GINP

BINP

VRUV

RLC

MID

RTVRB

RSCL

S/H

CDS

S/H

CDS

S/H

CDS

MUX

PGA

5-BIT REG

PGA

5-BIT REG

PGA

5-BIT REG

RLVMID

8-BIT + SIGN DAC

Applications

• Document scanners

• CCD sensor interfaces

• Contact image sensor (CIS) interfaces

RLC

MCLK

WM8144-10

MID

10 BIT

ADC

MID

VDDAGNDDVDD1DVDD2DGND

EXTERNAL DATA STORE INTERFACE

IMAGE COMPENSATION PROCESSING

CONFIGURABLE SERIAL/PARALLEL CONTROL INTERFACE

10/8 MUX

CC[2:0] DV

CDATA(7:0)

ORNG OEB OP[9:0]

PNS SDI / DNA SCK / RNW SEN / STB NRESET

Production Data data sheets contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics standard terms and conditions

Wolfson Microelectronics

Lutton Court, Bernard Terrace, Edinburgh EH8 9NX, UK

Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176

email: [email protected]

www: http://www.wolfson.co.uk

Page 2

WM8144-10

CDATA4

CDATA5

3635343332

OP9 OP8 OP7 OP6 OP5 OP4 OP3

37 38 39 40 41 42 43 44 45 46 47 48

OP1

OP2

CDATA3 CDATA2 CDATA1 CDATA0

DGND

NC - Make no external connection

MCLK

CDATA7

CDATA6

WM8144-10

OP0

DVDD2

VSMP

3130292827

DVDD1

RLC

CC2

SEN/STB

SDI/DNA

SCK/RNW

CC1

CC0

ORNG

OEB

24 23 22 21 20 19 18 17 16 15 14 13

NRESET

Ordering InformationPackage Outline

DEVICE TEMP RANGE PACKAGE

WM8144-10CFT/V 00C - 700C48 Pin TQFP

PNS RINP GINP BINP VMID VRLC AGND AVDD VRL VRU VRB VRT

Absolute Maximum Ratings

Analogue Supply Voltage. . . AGND - 0.3 V, AGND +7 V

Digital Supply Voltage. . . . DGND - 0.3 V, DGND +7 V

Digital Inputs . . . . . . . . DGND - 0.3 V, DVDD + 0.3 V

Operating temperature range, T

A . . . . . 0

Storage T emperature . . . . . . . . . . -50oC to +150oC

Lead T emperature (soldering, 10 sec) . . . . . . +260oC

C to +70oC

Digital Outputs. . . . . . . .DGND - 0.3 V, DVDD + 0.3 V

Reference inputs . . . . . . AGND - 0.3 V, AVDD + 0.3 V

RINP, GINP, BINP . . . . . .AGND - 0.3 V, AVDD + 0.3 V

Note: Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by

continuously operating at or beyond these limits. Device functional operating range limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified.

ESD Sensitive Device. The WM8144-10 is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device.

As per JEDEC specifications A112-A and A113-A this product requires specific storage conditions prior to surface mount assembly. It has been classified as having a Moisture Sensitivity level of 2 and as such will be supplied in vacuum sealed moisture barrier bags.

Recommended Operating Conditions

PARAMETE R TE ST CO NDITIONS MI N TY P MAX UNIT

Voltage 4.75 5.25 V

Suppl Operatin

Temperature Range

Input Common Mode Range

CMR

070

0.5 4.5 V

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WM8144-10

Electrical Characteristics

VDD = 4.75V to 5.25V, GND = 0 V, ........TA = 0oC to +70oC, MLCK = 12MHz unless otherwise stated.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Supply Current - Active 110.0 150 mA Suppl

Current - Standb

Digital Inputs

h Level Input VoltageV Low Level Input VoltageV Hi

h Level Input Current I Low Level Input Current I

0.8*DVDD V

Input Capacitance 10.0 pF

Digital Outputs

h Level Output VoltageV

OHIOH

= 1.0mA

DVDD-0.75

Voltage output range VOLIOL = 1.0mA High Impedance Output Current

Input M ultiplexe r

Channel to Channel Gain Matchin Input Video Set-up Time Input Video Hold Time Reset Video Set-up Time Reset Video Hold Time

tVSU

tVH

tRSU

tRH

CDS Mode onl CDS Mode onl

10 ns 25 ns 10 ns 25 ns

Reference String

Reference Volta Reference Volta DAC Reference Voltage

e - Top e - Bottom

RTVRU RBVRU

MIDVRU

= 5.00 V, VRL = 0.00V = 5.00 V, VRL = 0.00V = 5.00 V, VRL = 0.00V

3.465 3.5 3.535 V

1.465 1.5 1.535 V

2.475 2.5 2.525 V R.L.C. Switch Impedence 200 Oh ms Reset Level Clamp Options

to V

Impedance V Impedance V

RLC

VRU = 5.00 V, VRL = 0.00V

e set by user

Volta

uration - Table 7

conf i

1.425 1.5 1.575 V

2.375 2.5 2.625 V

3.325 3.5 3.675 V

490 700 910 Ohms 1190 1700 2210 Ohms

8-bit DACs

Resolution 8 Bits Zero Code Volta Full Scale Volta

e V

e Error 0 10 mV Dif ferent ia l Non Linear it Inte

ral Non Linearit

DNL 0.1 1 LSB

INL 0.4 1 LSB

DAC

-10 V

10.0 15 mA

0.2*DVDD V

1.0 µ

DGND+0.75

1.0 µ

0.5 %

DAC

+10 mV

A A

V V

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WM8144-10

Electrical Characteristics (Contd.)

VDD = 4.75V to 5.25V, GND = 0 V, ........TA = 0oC to +70oC, MLCK = 12MHz unless otherwise stated.

PARAMETE R TE ST CO NDITIONS MI N TY P MAX UNIT

10- Bit ADC

Resolution V Maximum Sampling Rate VDD = 5V 6 MSPS

= 5V 10 Bits

Full Scale Transition Error Voltage at VINP

Zer o S c ale Trans i t ion Error Volta VINP

Differential Non Linear it N um b er of mis s in

PGA Gain

Red Channel Max. Gain, Note 1 Gr Green Cha nnel Max. Gain, Note 2 G Blue Ch annel Max. Gain, Note 2 Gb Red Channel Max. Gain, Note 2 Gr Green Cha nnel Max. Gain, Note 2 G Blue Ch annel Max. Gain, Note 2 Gb

Note 1: Guaranteed monotonic up to PGA Gain code 0Fh Note 2: Guaranteed monotonic up to PGA Gain code 1Fh

codes 0 Code

e at

DAC Code = 0 00H, VDD=5V, measured relative to VRT

DAC Code = 0 00H, VDD=5V, measured relative to VRB

DNL VDD = 5V -1 +1.25 LSB

MCLK=12MHz; VDD=5 V 4 Times

Mode=1 7 Times

12 12 8

MCLK=8MHz; VDD=5V 6 Times

Mode=1 7 Times

+/-50 +/-200 mV

7Times

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WM8144-10

[

Electrical Characteristics (Contd.)

VDD = 4.75V to 5.25V, GND = 0 V, ........TA = 0oC to +70oC, MLCK = 12MHz unless otherwise stated.

PARAMETE R TE ST CO NDITIONS MI N TY P MAX UNIT

Switching Characteri st i cs

MCLK Peri od MCLK High MCLK Low Data Set-up time VSMP, RL C Data Ho ld Tim e CDAT A Data Hold Tim e Output Propa Output Enable TIme Output Disable Time

Serial Interface

SCK Period SCK High SCK Low SDI Set up time SDI Hold Time Set up time - SCK to SEN Set up time - SEN to SCK SEN Pulse Width

Paralle l Int erface

RNW Low to OP Add r ess Setup Ti me to STB Low tASU 0 ns DNA Low Setup Time to STB Low tADL S 10 ns Stro be Low Time tSTB 50 ns Add r ess Hold T ime from STB Hi DNA L ow Ho ld Time from STB Hi Data Set-up Time to STB Low tDSU 0 ns DNA Hi Da ta Ho ld Ti me fro m S TB Hi DNA Hi RNW High to OP[9:2] Output tOPD 0 n s

ati on D ela

9:2] Tristate tOPZ 20 ns

h Setup Time to STB Low tADHS 10 ns

h tDH 10 ns

h Hold Time from STB High tADHH 10 ns

tPER 83.3 ns tCKH

tCKL

tDSU

tDH tDH tPD

IOH = 1.0mA 75 ns tPZE tPEZ

tSPER 83.3

tSCKH

tSCKL

tSSU

tSH tSCE tSEC

tSEW

h tAH 10 ns

h tADLH 10 ns

= 1.0mA 75 ns

37.5 ns

37.5 ns 10

10 ns 30 ns

25 ns

37.5 ns

37.5 ns 10 ns 10 ns 20 ns 20 ns 50 ns

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WM8144-10

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

[9]Dig

[8]Dig

[7]Dig

[6]Dig

[5]Dig

]

]Dig

[3]Dig

[

]

[

]

[

]

Pin Descriptions

Pin No. Name Type D escription

23 RINP Analo 22 GINP Analo 21 BINP Analo 33 CD ATA 34 C DATA 35 C DATA 36 C DATA 37 C DATA 38 C DATA 39 C DATA 40 C DATA 32 MCLK Di

31 VSMP Digital IP Video sample synchro ni s at i on pulse. This signal is applied synchronously with

29 R LC Digital IP Se l ects whether reset le vel cla m p is a pplied on a pi xel-by-pixel basis. If RLC

19 V 13 V 14 V 15 V 16 V 20 V 42 OP 43 OP 44 OP 45 OP 46 OP 47 OP[4 48 OP 1OP 2OP 3OP

RLC RT RB RU RL MID

2 1 0

ue IP Red Channel input video ue IP Green Channel input video

ue IP Blue Channel in put video Digital IO Image compensation data read/write at twice ADC conversion rate Digital IO Digital IO Digital IO Digital IO Digital IO Digital IO Digital IO

ital IP M ast er c l ock. Thi s clock is applied at either six, four or t w o t im es the input

pix el rate dependin define the ADC samples rate and to provide the clock source for di

MLCK to specif internal multiplexing between the R, G and B channels is derived from this

nal

uired on each pixel then this pin can be tied high

is re

Analogue OP Selectable analogue output vol tage for RLC Analogue IP ADC reference voltages. The ADC reference range is a pplied be t ween Analogue IP VRT (full scale) and VRB (zero level). VRU and VRL can be used to Analogue IP derive optimum reference voltages from an ext erna l 5V r eference Analogue IP Analogue OP Buffered mid-point of ADC reference string.

ital IO Tri-state digital 10-bit bi-directional bus. There are four modes: ital IO Tri-state: when OEB = 1 ital IO Output ten-bit: ten bit data is output from bus ital IO Output 8-bit multiplexed: data output on OP[9:2] at 2*ADC conversion rate ital IO Input 8-bit: control data is input on bits OP[9:2 ital IO

ital IO Digital IO Digital IO Digital IO

on the operational mode. MCLK is divided internally to

ital logic.

the point in time that the input is sampled. The timing of

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WM8144-10

[

]

[

]

[0]Dig

)

Pin Descriptions (contd.)

Pi n No . Nam e Type Descript io n

8CC 9CC 10 C C 11 ORNG Digita l OP Out-of-ra nge signal, active high. This signal indicates that the curr ent

25 OEB Di

7DV Di 12 NRESET Di

2 1

Digital OP Col our code outputs. These outputs indicate from which channel the Digital OP current output sample was taken (R = 00X, G = 01X, B = 10X).

ital OP Two codes are provided per channel.

output pixel has exceeded the maximum or minimum achievable somewhere within the pixel processin

ital IP Output tri-state control, all outputs (OP[9:0], DV, ORNG, CC[2:]) enabled

when OEB=0

ital OP Data valid output, active low. ital IP Reset input, active low. This signal forces a reset of all internal registers.

24 PNS Di 27 SDI/DNA Digital IP Serial Interface: serial i nterface input data signal

28 SCK/RNW Digital IP Serial Interface: serial interface clock signal

26 SEN/STB Di

30 DVDD1 Di 4DVDD2Di 41 DGND Digital supplyDigital ground (0V 17 AVDD Analogue supplyPositive Analogue supply (5V 18 AGND Analogue supplyAnalogue Ground (0V 5 N C U nused Pin must be l eft unconnected 6 N C U nused Pin must be l eft unconnected

ital IP Control inter fa c e p a rallel (high) or serial (low, default

Parallel interface: hi

ital IP Serial Interface: enable, active high

Parallel interface: strobe, active low ital supplyPositive Digital Supply (5V ital supplyPositive Digital Supply (5V

h = data, low = address

h = OP[9:2] is output, low = OP[9:2] is input bus

Wolfson Microelectronics

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WM8144-10

Typical Performance

VDD = 5V, GND = 0 V, ........TA = 25oC.

0.8

0.6

0.4

0.2 0

LSB's

-0. 2

-0. 4

LSB's

-0. 6

-0. 8

-1 0 256 51 2 768 10 24

WM8144 10 Bit D N L Plot

ADC Code

ADC 10 Bit DNL

PGA Gain

8 7 6

Red Green Blue

5 4 3 2

Actual Gain

1 0

012345678

MCLK = 12.3MHz. Input set to 2.5V +/- 100mV. Other 2 are at 2.5V Col

PGA Gain Code

Gai n

PGA Gain Code vs. Actual Gain @ MCLK = 12.3MHz

5 4 3 2 1 0

DNL

-1

-2

-3

-4

-5 012345678

MCLK = 12.3MHz. Input 2.5V +/- 100mV. Other 2 are at 2.5V. Colour. V

Gain DNL

Red Gr een Blue

PGA Gain Code

Gai n

PGA DNL @ MCLK = 12.3MHz

5 4 3 2 1 0

LSB's

-1

-2

LSB's

-3

-4

-5 0 256 51 2 768 1024

WM8144 10 Bit INL Plot

ADC Code

ADC 10 Bit INL

PGA Gain

8 7 6

Red Green Blue

5 4 3 2

Actual Gain

1 0

012345678

MCLK = 8MHz. Input set to 2.5V +/- 100mV. Other 2 are at 2.5V Colo ur.

PGA Gain Code

Gai n

PGA Gain Code vs. Actual Gain @ MCLK = 8MHz

5 4 3 2 1 0

DNL

-1

-2

-3

-4

-5

MCLK = 8MHz. Input 2.5V +/- 100mV. Other 2 are at 2.5V. Colour. Vdd

Red Gr een Blue

012345678

Gain DNL

PGA Gain Code

Gai n

PGA DNL @ MCLK = 8MHz

Wolfson Microelectronics

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System Diagram

OPTIONAL

EXTERNAL

RAM

WM8144

TEN BIT IMAGE DATA

AT UPTO 6MSPS

IMAGE

10 BIT

SIMPLE SERIAL OR

PARALLEL CONTROL

COMPENSATION

LOGIC

ADC

INTERFACE

CONTROL

INTERFACE

WM8144-10

SIMPLE TWO PIN

TIMING INTERFACE

VMID

INTEGRATED TIMING CONTROL

S/H

RED

S/H

GREEN

COLOUR

CCD

S/H

SENSOR

VMID

S/H

BLUE

VMID

OFFSET DACGAIN

AMPS

CDSCLAMP

S/H

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WM8144-10

S/H

Gain=G

VMID

VRLC

RINP

Cin

WM8144

Theory of Operation

S/H, Offset DAC’s and PGA

Each analogue input (RINP , GINP, BINP) of the WM814410 consists of a sample and hold, a programmable gain amplifier, and a DC offset correction block. The operation of the red input stage is summarised in Figure 1.

The output from the offset DAC stage is referenced to the V

MID voltage. This allows the input to the ADC to

maximise the dynamic range, and is shown diagrammatically in Figure 1 by the final VMID addition. For the input stage the final analogue voltage applied to the ADC can be expressed as:

RINP

VMID

S/H

Gain=G

+ +

VMIDVoffset

Figure 1

The sample/hold block can operate in two modes of operation, CDS (Correlated Double Sampling) or Single Ended. In CDS operation the video signal processed is the difference between the voltage applied at the RINP input when RS occurs, and the voltage at the RINP input when VS occurs. This is summarised in Figure 2.

Vrs

Vvs

Figure 2

When using CDS the actual DC value of the input signal is not important, as long as the signal extremes are maintained within 0.5 volts of the chip power supplies. This is because the signal processed is the difference between the two sample voltages, with the common DC voltage being rejected. In single ended operation, the VS and RS control signals occur simultaneously, and the voltage applied to the reset switch is fixed at V

MID. This means that the voltage

processed is the difference between the voltage applied to RINP when VS/RS occurs, and V

MID. When using Sin-

gle ended operation the DC content of the video signal is not rejected. The Programmable Gain Amplifier block multiplies the resulting input voltage by a value between 0.5 and 8.25 which can be programmed independently for each of the three input channels via the serial (or parallel) interface. PGA gain is dependent on the 5-bit binary code programmed in the PGA registers. A typical plot of PGA gain versus code is shown on Page 8. The DC value of the gained signal can then be trimmed by the 8 bit plus sign DAC. The voltage output by this DAC is shown as Voffset in Figure 1. The range of the DAC is (V

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MID/2).

VADC

VADC G Vvs Vrs 1 2 * Sign *

=−+−

()

Where: V



()





ADC is the voltage applied to the ADC

DAC_CODE

255

VMID



VMID





G is the programmed gain Vvs is the voltage of the video sample Vrs is the voltage of the reset sample Sign is the Offset DAC sign bit DAC_CODE is the offset DAC value

MID is the WM8144-10 generated VMID voltage

The ADC has a lower reference of V and an upper reference of V

RB (typically 1.5 V)

RT (typically 3.5 V). When

an ADC input voltage is applied to the ADC equal to VRB the resulting code is 000(hex). When an ADC input voltage is applied to the ADC equal to V

RT the resulting code

is 3FF(hex).

Reset Level Clamp

Both CDS and Single ended operation can be used with Reset Level Clamping. A typical input configuration is shown in Figure 3.

Figure 3

Page 11

Theory of Operation (contd.)

Clamp Pulse

Video Input

The position of the clamp relative to the video sample is programmable by CDSREF1-0 (see Table 7). By default, the reset sample occurs on the fourth MCLK rising edge after VSMP. The relative timing between the reset sample ( and CL) and video sample can be altered as shown in Figure 4.

Figure 4: Reset Sample and Clamp Timing

When the clamp pulse is active the voltage on the WM8144-10 side of Cin, i.e. RINP, will be forced to be equal to the VRLC clamp voltage (see Figure 5). The VRLC clamp voltage is programmable to three different levels via the serial interface (1.5V, 2.5V or 3.5V). The voltage to which the clamp voltage should be programmed is dependent on the type of sampling selected and the polarity of the input video signal. For CDS operation it is important to match the clamp voltage to the amplitude and polarity of the video signal. This will allow the best use of the wide input common-mode range offered by the WM8144-10. If the input video is positive going it is advisable to clamp to Vcl (Lower clamp voltage). If the video is negative going it is advisable to clamp to Vcu (Upper clamp voltage). Regardless of where the video is clamped the offset DAC is programmed to move the ADC output corresponding to the reset level to an appropriate value to maximise the ADC dynamic range. For Single Ended operation it is recommended that the clamp voltage is set to Vcm (Middle clamp voltage).

WM8144-10

Figure 5

A reset level clamp is activated if the RLC pin is high on an MCLK rising edge (Figure 6). By default this initiates an internal clamp pulse three MCLK pulses later (Figure 4: CL). The relationship between CL and RS is fixed. Therefore altering the RS position also alters the CL position (Figure 4). Table 7 shows the three possible voltages to which the reset level can be clamped.

Figure 6: RLC Timing

RINP, GINP and BINP Input Impedence

The input impedence of the WM8144-10 analogue inputs is dependent on the sampling frequency of the input signal and the configuration of the internal gain amplifiers.

The input impedence = 1/(Capacitance * frequency) where the Capacitance value changes from 0.3pF for

minimum gain to 9.6pF for maximum gain. Table 1 illustrates the minimum and maximum input impedence at different frequencies.

Sampling

Frequency

(MHz)

0.5 6.6 208 1 3.3 104

21.6 52

40.8 26

60.5 17

Table 1: Effects of Frequency on Input Impedence

Impedence with

minimum gain

(MΩ)

Impedence with

maxi mum g a in

(KΩ)

Wolfson Microelectronics

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WM8144-10

Theory of Operation (Contd)

Example of Gain and Offset Operation

Input Video polarity negative Input sampling CDS Input voltage amplitude (V Programmable gain x1 Clamping Yes, V

After the input capacitor the input to the WM8144-10 can be represented as:

VS - VRS) 1.6V

CL = 3.5V

Vrs

Vvs

For a white pixel: VRS = VCL

VVS = VCL - 1.6

For the white pixel, using the same offset DAC value, the ADC input can be expressed as:

164 V

V = 1*(V - 1.6 - V ) + (1 - 2*0) * * + V

ADC CL CL MID

V = -1.6 + * V + V

ADC MID MID

V = * V - 1.6

ADC MID

255

337 255

MID

255 2

Figure 7

For a black pixel: V

RS = VCL

VVS = VCL

Assuming that the offset DAC is set to 00dec:

VADC =1* Vcl- Vcl

()()

VADC 0 + 0 + VMID

VADC = VMID



+−

120





** *VMID

255 2

VMID

 



VMID

An input voltage of VMID corresponds to a code of 512(dec) from the ADC.

To maximise the dynamic range of the ADC input it is necessary to program the offset DAC code to move the ADC code corresponding to the black level towards code 1024(dec).

Hence set the offset DAC to 164(dec) with the sign bit not set.

164 V

V = 1*(V - V ) + (1 - 2*0) * * + V

ADC CL CL MID

V = 0 + * V + V

ADC MID MID

V = * V

ADC MID

255

337 255

MID

255 2

When the VMID is 2.5v, the ADC input voltage becomes

3.3 volts which will result in an ADC code of 921(dec). This is near the ideal full-scale of 1023(dec).

When the VMID is 2.5V, the ADC input voltage becomes

1.7 volts which will result in a code of 102(dec). This is near the ideal full-scale of 000(dec).

Therefore the output codes from the ADC are between 921(dec) and 102(dec), which implies that the ADC input has been set up to maximise the dynamic range available. If a digital representation of the ADC output with a black level near 000(dec) and a white level near 1023(dec) is required then the INVOP control bit should now be set

to ONE.

Wolfson Microelectronics

Page 13

Theory of Operation (contd.)

WM8144-10

CDATA

ADCOP

Figure 8

DEMUX

AND MUX

DEFAULT

DATA

PARTITIONING

612

DEFAULT

10 11

PIXEL OFFSET

ADDER

4,5 or 6

MUX MUX

12,11 or 10

LIMIT

MUX

PIXEL GAIN

ADJUST

Figure 12

Digital Signal Processing

By default, the output from the ADC passes through the digital compensation block without being altered and is output directly on the OP[9:0] pins. If required, the pixel data from the ADC can be processed further by the digital compensation block (Figure 8). This section describes the sub-blocks of the digital compensation block.

CDATA Demultiplexor

The input to this block is coefficient data presented to the CDATA[7:0] pins at twice the pixel rate. i.e. two eight-bit words are input for each pixel of video data.

Data Partitioning

The sixteen bits of data per pixel from the CDATA Demultiplexor is partitioned into pixel offset, pixel gain and pixel valid bits (Table 3) . Table 4 details the resulting range and resolution options.

Pixel Offset Adder

This uses the offset coefficients that are either supplied externally via the CDATA interface or from the internal default registers. The object of this block is to correct for the small offsets which can occur from the CCD on a pixel-by-pixel basis. The output from the Pixel Offset Adder is limited to be between 0 and 1023(dec).

Pixel Gain Adjust

This block corrects for the pixel-by-pixel shading curve non-uniformity and photo response non-uniformity within the CCD sensor. This block has a gain range of 0 to 2. The output word from the Pixel Gain Adjust is limited to between 0 and 1023(dec).

DATA VALID

GENERATION

DEFAULT

22 10 10

LIMIT

ADC

DATA

LATCH

OUT OF RANGE

GENERATION

DV OUTPUT

OP[9:0] INPUT TO 8/10 MUX BLOCK

ORNG INPUT TO 8/10 MUX BLOCK

Effect of digital compensation on ADC output

The combined effect of the digital compensation sections on the ADC output is summarised by the formula:

OP[9:0] = (ADCOP + POC) * PSCF

where: All values are decimal OP[9:0] is the 10 bit result output from the WM8144-10 ADCOP is a 10 bit unsigned number from the ADC POC is a 2's compliment number divided byNUMBER OF POC BITS ALLOCATED/2 PSCF is an unsigned number divided by NUMBER OF PSC BITS ALLOCATED/2

For this example assume PSC is allocated 12 bits and POC is allocated 4 bits (refer to table 3:DVMODE,PWP0,PWP1 = 0). Table 1 shows some examples of the effect of the digital backend on the ADC output.

Range 0: 1023 -8:7 0:4095 0: 1023 0: 1 Default 0 2048 (x1)

ADCOP POC PSC OP[9:0] ORNG

Ex 1 512 0 2048 512 0 Ex 2 512 -7 204 8 505 0 Ex 3 512 6 2048 518 0 Ex 4 1022 6 2048 1023 1 Ex 5 1022 6 512 257 1 Ex 6 512 0 2560 640 0 Ex 7 512 0 512 128 0 Ex 8 512 0 4095 1023 1 Ex 9 511 0 4095 1021 0

Table 2: Examples of digital backend calculation

Wolfson Microelectronics

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WM8144-10

Theory of Operation (contd.)

D V M O D E

0 0 0 G1 1 G1 0 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 O3 O2 O1 O0 0 0 1 G10G9G8G7G6G5G4G3G2G1G0O4O3O2O1O0 0 1 0 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 O5 O4 O3 O2 O1 O0

1 0 0 G10G9G8G7G6G5G4G3G2G1G0DVO3O2O1O0 1 0 1 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 DV O4 O3 O2 O1 O0

B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0

CDATA WORD 1 CDATA WORD 2

Table 3: Bit Allocation Assignment

DVMODE PWP1 PWP0 No. of

0 0 0 4 -8 : 7 12 0:2 0.25 0 0 0 1 5 -16 - 15 11 0:2 0.5 0 0 1 0 6 -32 - 31 10 0:2 1 0 1 0 0 4 -8 - 7 11 0:2 0.5 1 1 0 1 5 -16 : 15 10 0:2 1 1

offset range No. of gain

offset

bi t s

bits

gain

range

reso l ution

(LSB

gain

DV bits

Table 4: Bit Range and Resolution Options

Data Valid Generation

The DV pin can be controlled to determine whether a DV pulse will be generated for a particular pixel. For example, if red pixels only are required the following DV pulse can be generated.

Output data interface

By default, data is output from the device as a ten-bit wide word on OP[9:0]. Optionally, data can be output in an eight-bit word format. Figure 11 shows this function.

Data is presented on pins OP[9:2] at twice pixel rate.

OP[9:0]

BBG GRR

Figure 9

Data Latch

Under control of the LATCHOP bit the output data bus can be prevented from clamping until the next Data Valid pulse. Hence the above output would become:

OP[9:0]

Figure 10

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A = d9,d8,d7,d6,d5,d4,d3,d2 B = d1,d0,X,X,X,X,X,ORNG

Figure 11: Eight-bit Multiplexed Bus Output

Page 15

Operational Modes

Video Sampling Options

WM8144-10 can interface to CCD sensors using four basic modes of operation ( summarised in T able 4). Mode configurations are controlled by a combination of control bits and timing applied to MCLK and VMSP pins. The default operational mode is mode 1: colour with CDS enabled.

Colour mode definition (mode 1)

Figure 12 summarises the timing relationships within the Colour mode. MCLK is applied at twice the required ADC conversion rate. Synchronisation of sampling and channel multiplexing to the incoming video signal is performed by the VSMP pulse (active high). The three input channels (R,G,B) are sampled in parallel on the rising edge of MCLK following a VSMP pulse. The sampled data is multiplexed into a single data stream at three times the VSMP rate and passes through the internal pipeline and emerges on the OP[9:0] bus 20.5 MCLK periods later. If the digital post-processing stage is activated, compensation data will be clocked into the device at twice the ADC conversion rate (e.g. two reads per red pixel ). The first of the two bytes will be required on the CDATA bus

15.5 MCLK periods after the corresponding VSMP pulse. CC[2:0] can be used to control the three lower address lines of an external RAM. Both Correlated Double Sampling (CDS) and single sample modes of operation are available.

WM8144-10

MSPS. This is achieved by altering the MCLK:VSMP ratio to 3:1. In this mode, the timing of RS and CL must be fixed (refer to Table 5). The sampled video data will pass through the internal pipeline and emerge on the OP[9:0] bus 29.5 MCLK periods later. If the digital post-processing stage is activated compensation data will be clocked into the device at twice the internal pixel rate (e.g. two reads per red pixel ). The first of the two bytes will be required on the CDATA bus 22.5 MCLK periods after the corresponding VSMP pulse.

Details of Max. Speed Monochrome mode (mode 4)

Figure 15 summarises the timing relationships. This mode allows the maximum sample rate to be increased to 6 MSPS. This is achieved by altering the MCLK:VSMP ratio to 2:1. The latency through the device is identical to modes 1 and 2. CDS is not available in this mode.

Monochrome mode definitions

One input channel is continuously sampled on the rising edge of MCLK following a VSMP pulse. The user can specify which input channel (R,G,B) to be sampled by writing to WM8144-10 internal control registers. There are three separate monochrome modes with different maximum sample rates and CDS availability .

Details of Monochrome mode timing (mode 2)

Figure 13 summarises the timing relationships. The timing in this mode is identical to mode 1 except for the CC[2:0] outputs. One input channel is sampled three times ( due to the multiplexer being held in one position) and passes through the device as three separate samples. Two of the samples can be ignored at the output. The CC[2:1] output pins reflect the input channel selected (R,G or B).

Details of Fast Monochrome mode timing (mode 3)

Figure 14 summarises the timing relationships. This mode allows the maximum sample rate to be increased to 4

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Page 16

WM8144-10

y g

g g

Operational Modes (Contd.)

1: 19(H)

without CDS*

1: 1B(H) Setup Re

with CDS*

Setup Re

Timing Requirements Register Contents

Sensor Interface

MCLK max. 12MHz.

MCLK:VSMP ratio is 6:1.

multiplexed into a

ivin

le data stream

inter nal seria l data

rate of max. 6MSPS.

before the internal

ADC

sin

Description

channels (R,G,B) are

sampled in parallel at

max. 2MSPS. The

sampled data is

1: 1D(H)

Setup Re

1: 1F(H)

Identical to Mode 1 Setup Re

3: bits b[7

Setup Re

3: bits

Setup Re

continuousl

6] defin e which

b[7-6] define which

sampled. The internal

channel to be

sampled

channel to be

sampled

multi plexer is held in

one position under

1: 5D(H)

3: bits b[7

Identical to Mod e 2

3: bits

b[5-4] must be set to

00(H)

Identical to Mod e 2

plus Setup Re

MCLK:VSMP ratio is 3:1.

control of the user.

6] defin e which

channel to be

sampled

Setup Re

Not Applicable Setup Re

MCLK:VSMP ratio is 2:1.

Rate

Max.

Sample

available

Table 5: WM8144-10 Mode Summary

Mode Description C DS

1 Colour Yes 2 MSPS The three input

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2 Monochrome Yes 2 MSPS One input channel is

Yes 4 MS PS Identical to Mode 2 MCLK max. 12MHz.

Monochrome

3Fast

No 6 MSPS Identical to Mode 2 MCLK max. 12MH z.

Monochrom e

4 Max Speed

ister bits

indicates relevant re

* Onl

Page 17

WM8144-10

Operational Modes (Contd.)

r1:1 r1:2 g1:1 g1:2 b1:1 b1:2

Device timing for mode 1

b2 b3 r4 g4 b4

g2r2 g3r3b1

1111

0000 22221

2345

r2,g2,b2 r3,g3,b3 r4,g4,b4 r5,g5,b5

2345

b0 g1r1

ADC input

ADC sample

SIGNALS

20.5 MCLK periods

ORNG

OP[9:0]

MCLK

VSMP

INPUT

SIGNALS

Input video

15.5 MCLK periods

r1,g1,b1

CDATA[7:0]

INTERNAL

Figure 12: Default Timing in CDS Colour Mode

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OUTPUT

SIGNALS

CC[0]

CC[1]

CC[2]

CC[2:1]

Page 18

WM8144-10

Operational Modes (Contd.)

r1:1 r1:2 X XXXXXXXXX XXXXX XXXX

Device timing for mode 2

XXXXX XXXXX

2345

r2,g2,b2 r3,g3,b3 r4,g4,b4 r5,g5,b5

XXXXr1 XX XXX

20.5 MCLK periods

ADC input

INTERNAL

SIGNALS

ADC sample

ORNG

OP[9:0]*

OUTPUT

SIGNALS

CC[0]

MCLK

VSMP

INPUT

Input video

SIGNALS

2345

15.5 MCLK periods

r1,g1,b1

CDATA[7:0]

Figure 13: Default Timing in CDS Monochrome Mode

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CC[1]*

00000000000000

* This example shows function when Red channel selected. CC[1] and CC[2] indicate the selected channel (R,G or B)

'X' indicates don't care

CC[2]*

CC[2:1]

Page 19

WM8144-10

Operational Modes (Contd.)

Device timing for mode 3

n:2

n:1

00 000000000

CC[1]*

CC[2]*

CC[2:1]*

MCLK

VSMP

INPUT

Input video

SIGNALS

n+1

22.5 MCLK periods

CDATA[7:0]

ADC input

INTERNAL

SIGNALS

29.5 MCLK periods

ADC sample

OP[9:0]

ORNG

OUTPUT

CC[0]

SIGNALS

Figure 14: Default Timing in Fast CDS Monochrome Mode

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* This example shows function when Red channel selected. CC[1] and CC[2] indicate the selected channel (R,G or B)

Page 20

WM8144-10

Operational Modes (Contd.)

n:1 n:2

Device timing for mode 4

000

MCLK

VSMP

INPUT

SIGNALS

Input video

15.5 MCLK periods 1

CDATA[7:0]

INTERNAL

ADC input

ADC sample

SIGNALS

20.5 MCLK periods

ORNG

OP[9:0]

OUTPUT

CC[0]

SIGNALS

CC[1]*

CC[2]*

CC[2:1]*

Figure 15: Default Timing in Max. Speed non-CDS Monochrome Mode

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* This example shows function when Red channel selected. CC[1] and CC[2] indicate the selected channel (R,G or B)

Page 21

Configuration of the WM8144-10

The WM8144-10 can be configured through a serial interface or a parallel interface. Selection of the interface type is by the PNS pin which must be tied high (parallel) or low (serial).

Serial Interface

The serial interface consists of three pins (refer to figure 16 ). A six-bit address is clocked in MSB first followed by an eight-bit data word, also MSB first. Each bit is latched on the rising edge of SCK, which can operate at upto 12MHz. Once the data has been shifted into the device, a pulse is applied to SEN to transfer the data to the appropriate internal register.

Parallel Interface

The parallel interface uses bits [9:2] of the OP bus as well as the STB, DNA and RNW pins (refer to figure

17). Pin RNW must be low during a write operation. The DNA pin defines whether the data byte is address (low) or data (high). The data bus OP[9:2] is latched in during the low period of STB. This interface is compatible with the Extended Parallel Port interface.

Internal Register Definition

Table 5 summarises the internal register content. The first 4 addresses in the table are used to program setup registers and to provide a software reset feature ( 00H is reserved ). The remaining 7 entries in the table define

WM8144-10

Figure 16: Serial Interface Timing

Figure 17: Parallel Interface Timing

the address location of internal data registers. In each case, a further three sub-addresses are defined for the red, green and blue register. Selection between the red, green and blue registers is performed by address bits a1 and a0, as defined in the table. Setting both a1 and a0 equal to 1 forces all three registers to be updated to the same data value. Blank entries can be taken as 'don't care' values.

Address Description Def'lt Bit

<a5:a0> (Hex) b7 b6 b5 b4 b3 b2 b1 b0

000000 Reserved 000001 Setup Regis ter 1 1B DVMODE VSMP6M DEFDV D EFPO DEFPG MONO CDS ENADC 000010 Setup Regis ter 2 00 CDATOUT BYPASS LATCHOP INVOP MUXOP 000011 Setup Register 3 11 CHAN[1] CHAN[0] CDSREF[1] CDSREF[0] PWP[1] PWP[0] RLC[1] RLC[0] 000100 Software Reset 00 000101 Setup Register 4 00 DACRNG 1000xx DAC values 00 DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0] 1001xx DAC signs 00 DSIGN 1010xx PGA Gains 00 PGA[4] PGA[3] PGA[2] PGA[1] PGA[0] 1011xx Pixel Offsets 00 OFF[5] OFF[4] OFF[3] OFF[2] OFF[1] OFF[0] 1100xx Pixel Gain MSB 80 GAIN[11] GAIN[10] GAIN[9] GAIN[8] GAIN[7] GAIN[6] GAIN[5] GAIN[4] 1101xx Pixel Gain LSB 00 GAIN[3] GAIN[2] GAIN[1] GAIN[0] 1110 xx Dat a Val id 01 DV

Address LSB decode a1 a0

Red Register 0 0 Gree n R eg iste r 0 1 Blue Register 1 0 Red, Green and Blue 1 1

Table 6: Register Map Contents

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Page 22

WM8144-10

Configuration of the WM8144-10 (Contd.)

Setup 0 ENADC 1 ADC standby control: 0 = standby, 1 = active Register 1 1 CDS 1 Select Correlated double sampling mode: 0 = normal sampling, 1 =

2 MONO 0 Mono / Co lour sel ec t: 0 = colo ur, 1 = monoc hro m e op er at ion 3 DEFPG 1 Select Default Pixel Gain: 0 = external pixel 4 DEFPO 1 Sel ect Default Pixel Of fsets: 0 = external pixel offsets, 1 = internal 5 DEFDV 0 Select default internal Data Valid: 0 = external DV, 1 = internal 6 VSMP6M 0 Required when VSMP at 6MSPS: 0 = other mode, 1 = VSMP at 6MSPS

CDS mode

ain, 1 = internal

7 DVMODE 0 External Data Valid control (refer to Bit Allocation Assi

Setup 0 MUXOP 0 Ei Register 2 1

2 INVOP 0 Inverts ADC output: 0 = non-inverting, 1 = invertin 3 LATCHOP 0 OP bus updated on DV pulse; OP bus updated each sample, 1 = update

4 BYPASS 0 B 5 CDATOUT 0 Data on OP pins available on CDAT pins; 0 = no, 1 =

6 7

Setup 1-0 RLC1-0 01 Reset Level Clamp volta Re

ister 3 00 = 1.5V

3-2 PWP1-0 00 Parallel Word Partitionin

5-4 CDSREF1-0 01 CDS Mode Reset Timing Adjust

7-6 CHAN1-0 00 Monochrome mode channel select

Setup 1 DACRNG 0 Alters ran Register 4 0 = DAC output range equal to Vmid/2 (1.25V)

ht bit output m ode: 0 = ten-bit, 1 = 8-bit multiplexed

onl

on DV pulse

pass digital post-processi ng; 0 = no bypass , 1 = bypass

01 = 2.5V 10 = 3.5V 11 = Reserved

See Bit Allocation Assignment (Tab le 3)

00 = Advance 1 MCLK Period 01 = Normal 10 = Retard 1 MCLK Period 11 = Retard 2 MCLK Period

00 = Red Channel 01 = Green Channel 10 = Blue Channel 11 = Reserved

e of off s et D AC outp ut

1 = DAC output range equ al t o 1. 5 * Vm id /2 ( 1. 875 V )

nment table)

Table 7: Control Bit Descriptions

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Detailed timing diagramsDetailed timing diagrams

Figure 18: Detailed Video Input Timing - Modes 1 and 2

WM8144-10

Figure 19: Detailed Digital Timing - Modes 1 and 2

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WM8144-10

Detailed timing Diagrams (Contd.)

Figure 20: Detailed Video Input Timing - Mode 3

Figure 21: Detailed Digital Timing - Mode 3

Figure 22: Detailed Video Input Timing - Mode 4

Figure 23: Detailed Digital Timing - Mode 4

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Detailed timing Diagrams (Contd.)

Address In

SCKHtSCKL

STB

ADLH

DSU

ADHS

SPER

SCK

SSU

SDI

SEN

Figure 24: Detailed Timing Diagram for Serial Interface

STB

ASU

OP[9:2]

DNA

8144 Out

ADLS

RNW

OPZ

Figure 25: Detailed Timing Diagram for Parallel Interface

SCEtSEWtSEC

STB

Data In

ADHH

WM8144-10

8144 Out

OPD

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WM8144-10

External component recommendations

DGND

CDATA3

CDATA2

CDATA1

CDATA0

DGND

OP9

OP8

OP7

OP6

OP5

OP4

OP3

DVDD

C13 10µF

C14

0.1µF

DGND

36 35 34 33 32 31 30 29 28 27 26 25

RLC

MCLK

VSMP

DVDD1

CDATA7

CDATA6

CDATA5

CDATA4

SCK/RNW

WM8144-10

CC1

CC2

DVDD2

OP0

OP1

OP2

123456789101112

DVDD

C15 10µF

C16

0.1µF

DGND

OEB

SDI/DNA

SEN/STB

AGND

NRESET

ORNG

CC0

PNS

RINP

GINP

BINP VMID VRLC

AVDD

VRL VRU VRB

VRT

C5 22µF

0.1µF

C7 33µF

0.1µF

AGND

24 23 22 21 20 19 18 17 16 15 14 13

C9 10µF

C10

0.1µF C11

10µF C12

0.1µF

AGND

C1 10µF

0.1µF

AVDD

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Page 27

Package Dimensions

0.50

WM8144-10

0.27

0.08

0.17

2536

1.60MAX

1.45

1.35

112

5.50TYP

7.00

9.00

0.05MIN

Seating Plane

0.08

48 Pin TQFP

0.25

0.75

0.45

0.13NOM

Gage Plane

0o - 7

Notes: A. All linear dimensions are in millimeters

B. This drawing is subject to change without notice. C. Falls within JEDEC MO-026

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