Datasheet WM2639IDT, WM2639CDT Datasheet (Wolfson)

Download

Page 1

WM2639

GND

BUFFER

DNL - LSB

12-Bit Parallel Input Voltage Output DAC

with Internal Reference

Production Data, July 1999, Rev 1.0

FEATURES

• 12-bit voltage output DAC

• Single supply 2.7V to 5.5V operation

• DNL ±±0.3 LSBs, INL ±±1.2 LSBs

• Internal programmable voltage reference

• Settling time 1µµs typical

• 12-bit microprocessor compatible interface

• Power down mode 10nA

APPLICATIONS

• Battery powered test instruments

• Digital offset and gain adjustment

• Battery operated/remote industrial controls

• Machine and motion control devices

• Wireless telephone and communication systems

• Speech synthesis

• Arbitrary waveform generation

• Mass storage devices

ORDERING INFORMATION

DEVICE TEMP. RANGE PACKAGE

WM2639CDT 0° to 70°C 20-pin TSSOP

WM2639IDT -40° to 85°C 20-pin TSSOP

DESCRIPTION

The WM2639 is a 12-bit voltage output, resistor string, digital-toanalogue converter. A hardware controlled power down mode is provided that reduces current consumption to 10nA. The device has been designed to interface efficiently to industry standard microprocessors and DSPs.

The WM2639 features an internal programmable voltage reference simplifying overall system design. The reference voltage can also be supplied externally.

Excellent performance is delivered with a typical DNL of 0.3 LSBs and typical INL of 1.2 LSBs. The output stage is buffered by a x2 gain near rail-to-rail amplifier, which features a Class A output stage (slow mode, Class AB). The 12 data bits are double buffered enabling the output to be asynchronously updated under hardware control. The settling time of the DAC is software programmable to allow the designer to optimise speed versus power dissipation.

The device is available in a 20-pin TSSOP package. Commercial temperature (0° to 70°C) and Industrial temperature (-40° to 85°C) variants are supported.

BLOCK DIAGRAM TYPICAL PERFORMANCE

VDD (11)

REFERENCE

OUTPUT BUFFER

WITH OUPUT

REF(12)

D[0-11]

(19,20, 1-10)

NWE (17)

NCS (18)

REG (15)

12-BIT INPUT

POWER-ON

RESET

(14)

ENABLE

REFERENCE

SELECT

LATCH

data

2-BIT

NLDAC

1.024V/2.048V SELECTABLE

REFERENCE

INPUT

12-BIT

DAC

LATCH

2-BIT

CONTROL

LATCH

(16)

POWERDOWN

CONTROL

OUTPUT BUFFER

WM2639

DAC

WOLFSON MICROELECTRONICS LTD

Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: [email protected] http://www.wolfson.co.uk

(13) OUT

5V = VDD, V

0.8

0.4

0.2

-0.2

-0.4

-0.8

-1

REF

512 1024 2048 2559 3583 4095

Production Data contain final specifications

current on publication date. Supply of products

conforms to Wolfson Microelectronics’ Terms

1999 Wolfson Microelectronics Ltd.

and conditions..

Master 15/07/99 15:02

Page 2

WM2639 Production Data PIN CONFIGURATION

NCS

NWE

NLDAC

REG

AGND

OUT

REF

VDD

D10 D11

9 10

PIN DESCRIPTION

PIN NO NAME TYPE DESCRIPTION

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

17 18 19 20

D2 Digital input Data input. D3 Digital input Data input. D4 Digital input Data input. D5 Digital input Data input. D6 Digital input Data input. D7 Digital input Data input. D8 Digital input Data input.

D9 Digital input Data input. D10 Digital input Data input. D11 Digital input Data input.(MSB)

VDD Supply Positive power supply. REF Analogue I/O Analogue reference voltage input/output. OUT Analogue output DAC analogue voltage output.

AGND Supply Analogue Ground.

REG Digital input Register select. Digital input used to access control register.

NLDAC Digital input Load DAC. Digital input active low. NLDAC must be taken low to update

the DAC latch from the holding latches.

NWE Digital input Write enable. Digital input active low.

NCS Digital input Chip select. Digital input active low.

D0 Digital input Data input. (LSB)

D1 Digital input Data input.

WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 July 1999

Page 3

Production Data WM2639

Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at

or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical

ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible

to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage

ABSOLUTE MAXIMUM RATINGS

Characteristics at the test conditions specified

of this device.

CONDITION MIN MAX

Digital supply voltages, VDD to GND 7V Reference input voltage -0.3V VDD + 0.3V Digital input voltage range to GND Operating temperature range, T

WM2639CDT WM2639IDT

-0.3V VDD + 0.3V 0°C

-40°C

70°C

85°C Storage temperature -65°C 150°C Lead temperature 1.6mm (1/16 inch) soldering for 10 seconds

260°C

RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Supply voltage High-level digital input voltage Low-level digital input voltage Reference voltage to REF Load resistance Load capacitance Operating free-air temperature

VDD 2.7 5.5 V

REF

VDD = 2.7V to 5.5V 2 V VDD = 2.7V to 5.5V 0.8 V

See Note VDD - 1.5 V

2 kΩ

WM2639CDT 0 70 °C

WM2639IDT -40 85 °C

Note: Reference voltages greater than VDD/2 will cause output saturation for large DAC codes.

100 pF

WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 July 1999

Page 4

WM2639 Production Data ELECTRICAL CHARACTERISTICS

Test Conditions:

RL = 10kΩ, CL = 100pF. VDD = 5V ±± 10%, V temperature range (unless noted otherwise)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Static DAC Specifications

Resolution Integral non-linearity Differential non-linearity Zero code error Gain error d.c. power supply rejection ratio Zero code error temperature coefficient Gain error temperature coefficient

DAC Output Specifications

Output voltage range Output load regulation

Power Supplies

Active supply current

Power down supply current

Dynamic DAC Specifications

Slew rate

Settling time

Glitch energy

= 2.048V and VDD = 3V ±± 10%, V

REF

= 1.024V over recommended operating free-air

REF

12 bits

INL See Note 1

DNL See Note 2

±±1.2 ±±3 ±±0.3 ±±0.5

ZCE See Note 3 3

GE See Note 4

±±20

±±0.3

LSB LSB

% FSR

DC PSRR See Note 5 0.5 mV/V

See Note 6 20 ppm/°C See Note 6 20 ppm/°C

0 VDD - 0.4 V

2kΩ to 10kΩ load

0.1 0.3 %

See Note 7

No load, V

VDD = 5V, V

= VDD, V

REF

= 0V

= 2.048V,

Internal

Slow

VDD = 5V, V

Fast

= 2.048V,

REF

1.3

2.3

1.6

2.8

mA mA

External

VDD = 3V, V

Slow

Fast

REF

= 1.024V,

0.9

1.9

1.2

2.4

mA mA

Internal

Slow

VDD = 3V, V

Fast

= 1.024V,

REF

1.2

2.1

1.5

2.6

mA mA

External

Slow

Fast

0.9

1.8

1.1

2.3

mA mA

See Note 8

No load,

0.01 1 µA

all inputs 0V or VDD

See Note 9

DAC code 32-4095,

10%-90%

Slow

Fast

1.2

6.0

1.7 10

V/µs V/µs

See Note 10

DAC code 32-4095

Slow

Fast

3.5

µs

See Note 11

Code 2047 to 2048 5 nV-s

WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 July 1999

Page 5

Production Data WM2639

OUT

Test Conditions:

RL = 10kΩ, CL = 100pF. VDD = 5V ±± 10%, V

= 2.048V and VDD = 3V ±± 10%, V

REF

= 1.024V over recommended operating free-air

REF

temperature range (unless noted otherwise)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Signal to noise ratio

SNR

fs = 480ksps, f

= 1kHz,

OUT

73 78 dB

BW = 20kHz, TA=25°C

See Note 12

Signal to noise and distortion ratio

SNRD

= 1kHz, BW

61 67 dB

= 20kHz, TA=25°C

See Note 12

Total harmonic distortion

THD

= 480ksps, f

= 1kHz, BW

-69 -62 dB

= 20kHz, TA=25°C

See Note 12

Spurious free dynamic range

SPFDR = 480ksps, f

= 1kHz, BW

63 74 dB

= 20kHz, TA = 25°C

See Note 12

Reference configured as input

Reference input resistance Reference input capacitance Reference feedthrough

R C

REFIN

= 1VPP at 1kHz

REF

10 MΩ 55 pF

-60 dB

+ 1.024Vdc, DAC code 0

Reference input bandwidth

= 0.2VPP + 1.024V d.c.

REF

DAC code 2048

Slow

Fast

500 900

kHz kHz

Reference configured as output

Low reference voltage High reference voltage Output source current Output sink current Load Capacitance PSRR

REFOUTL

REFOUTH

REFSRC

REFSNK

1.003 1.024 1.045 V

VDD > 4.75V 2.027 2.048 2.069 V

1 mA

-1 mA 100 pF

-48 dB

Digital Inputs

High level input current Low level input current Input capacitance

Input voltage = VDD 1 µA

Input voltage = 0V -1 µA

8 pF

Notes:

1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects of zero code and full scale errors).

2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in digital input code.

3. Zero code error is the voltage output when the DAC input code is zero.

4. Gain error is the deviation from the ideal full scale output excluding the effects of zero code error.

5. Power supply rejection ratio is measured by varying VDD from 4.5V to 5.5V and measuring the proportion of this signal imposed on the zero code error and the gain error.

6. Zero code error and Gain error temperature coefficients are normalised to full scale voltage.

7. Output load regulation is the difference between the output voltage at full scale with a 10kΩ load and 2kΩ load. It is expressed as a percentage of the full scale output voltage with a 10kΩ load.

8. IDD is measured while continuously writing code 2048 to the DAC. For VIH < VDD - 0.7V and VIL > 0.7V supply current will increase.

9. Typical supply current in power down mode is 10nA. Production test limits are wider for speed of test.

10. Slew rate results are for the lower value of the rising and falling edge slew rates.

11. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling edges. Limits are ensured by design and characterisation, but are not production tested.

WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 July 1999

Page 6

WM2639 Production Data

12. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency f

SERIAL INTERFACE

SUD

D[0-11]

REG

NCS

NWE

NLDAC

Figure 1 Timing Diagram

SUCSWE

DATA

SUR

REG

HDR

WHWE

SUWELD

generated with a sampling frequency fs

OUT

WLD

Test Conditions:

RL = 10kΩ, CL = 100pF. V

= 5V±±10%, V

= 2.048V and V

REF

= 3V±±10%, V

= 1.024V over recommended operating free-air

REF

temperature range (unless noted otherwise)

SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

SUCSWE

SUD

SUR

HDR

SUWELD

WHWE

WLD

Setup time NCS low before positive NWE edge Setup time data ready before positive NWE edge Setup time REG ready before positive NWE edge Data and REG hold after positive NWE edge Setup time NWE high before NLDAC low High pulse width of NWE Low pulse width of NLDAC

15 ns 10 ns 20 ns

5 ns

5 ns 20 ns 23 ns

WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 July 1999

Page 7

Production Data WM2639

INL - LSB

Vo - OUTPUT VOLTAGE - V

REF

Vo - OUTPUT VOLTAGE - V

TYPICAL PERFORMANCE GRAPHS

5V = VDD, V

= External. 2.048V, Speed = Fast mode, Load = 10k/100pF

REF

-1

-2

-3 0 512 1024 1536 2048 2559 3071 3583 4095

DIGITAL CODE

Figure 2 Integral Non-Linearity

VDD = 3V, V

2.5

1.5

0.5

0 0.5 1 1.5 2 2.5 3 3.5 4

= Internal. 1V, Input Code = 0

REF

ISINK - mA

Slow Fast

VDD = 5V, V

4.5

3.5

2.5

1.5

0.5

0 0.5 1 1.5 2 2.5 3 3.5 4

= Int. 2V, Input Code = 0

ISINK - mA

Slow Fas)

Figure 3 Sink Current VDD = 3V Figure 4 Sink Current VDD = 5V

2.0395

VDD = 3V, V

2.039

2.0385

2.038

2.0375

2.037

2.0365

2.036

2.0355

2.035 0 0.5 1 1.5 2 2.5 3 3.5 4

= Int. 1V, Input Code = 4095

REF

ISOURCE - mA

Slow Fast

4.0795

VDD = 5V, V

4.079

4.0785

4.078

4.0775

4.077

4.0765

4.076

4.0755

4.075 0 0.5 1 1.5 2 2.5 3 3.5 4

= Int. 2V, Input Code = 4095

REF

ISOURCE - mA

Slow Fast

Figure 5 Source Current VDD = 3V Figure 6 Source Current VDD = 5V

WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 July 1999

Page 8

WM2639 Production Data

DEVICE DESCRIPTION

GENERAL FUNCTION

The device uses a resistor string network buffered with an op amp to convert 12-bit digital data to analogue voltage levels (see Block Diagram). The output voltage is determined by the reference input voltage and the input code according to the following relationship:

Output voltage =

INPUT OUTPUT

1111 1111 1111

: :

1000 0000 0001

1000 0000 0000

0111 1111 1111

: :

0000 0000 0001

0000 0000 0000 0V

Table 1 Binary Code Table (0V to 2V

( )

V2 REF

CODE

4096

( )

V2 =

Output), Gain = 2

REF

( )

V2 REF

( )

V2 REF

2048 4096

( )

V2 REF

( )

V2 REF

4095 4096

2049 4096

REFREF V

2047 4096

4096

POWER ON RESET

An internal power-on-reset circuit resets the DAC register to all 0s on power-up.

BUFFER AMPLIFIER

The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a 2kΩ load with a 100pF load capacitance.

HARDWARE CONFIGURATION OPTIONS

The WM2639 has one configuration option that is controlled by a device pin.

DAC UPDATE

The NLDAC pin (Pin 16) can be held high to prevent word writes from updating the DAC latch. By writing the new value to the DAC then pulling NLDAC low, the new DAC code is loaded into the DAC latch.

PARALLEL INTERFACE

The device registers data on the positive edge of NWE (Pin 17). It must be enabled with NCS (Pin 18) low. Whether the data is written to the DAC holding latch or the control register, depends on the state of input pin REG (Pin 15). REG = 0 selects the DAC holding latch, REG = 1 selects the control register.

WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 July 1999

Page 9

Production Data WM2639

SOFTWARE CONFIGURATION OPTIONS

DATA FORMAT

The WM2639 writes data either to the DAC holding latch or to the control register depending on the state of input pin REG.

REG

(PIN 15)

0 1

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X X X X X X X REF1 REF0 X PWR SPD

Table 1 Register Bits

DATA DESTINATION

DAC holding latch Control register

PROGRAMMABLE SETTLING TIME

Settling time is a software selectable 3.5µs or 1µs, typical to within ±0.5LSB of final value. This is controlled by the value of SPD – Bit D0. A ONE defines a settling time of 1µs, a ZERO (default) defines a settling time of 3.5µs.

PROGRAMMABLE POWER DOWN

The power down function can be controlled by PWR. A ZERO configures the device as active, or fully powered up, a ONE configures the device into power down mode. When the power down function is released the device reverts to the DAC code set prior to power down.

PROGRAMMABLE INTERNAL REFERENCE

The reference can be sourced internally or externally under software control. If an external reference voltage is applied to the REF pin, the device must be configured to accept this.

If an external reference is selected, the reference voltage input is buffered which makes the DAC input resistance independent of code. The REF pin has an input resistance of 10MΩ and an input capacitance of typically 55pF. The reference voltage determines the DAC full-scale output.

If an internal reference is selected, a voltage of 1.024V or 2.048 is available. The internal reference can source up to 1mA and can therefore be used as an external system reference.

REF1 REF0 REFERENCE

0 0 External (default) 0 1 1.024V 1 0 2.048V 1 1 External

Table 2 Programmable Internal Reference

WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 July 1999

Page 10

WM2639 Production Data PACKAGE DIMENSIONS

DM008.CDT: 20 PIN TSSOP (6.5 x 4.4 x 1.0 mm)

1120

E1 E

GAUGE PLANE

101

0.05

-C-

SEATING PLANE

θθ

0.25

Dimensions

Symbols

(mm)

MIN NOM MAX A A

b c D e E E

----- ----- 1.20

0.05 ----- 0.15

0.80 1.00 1.05

0.19 ----- 0.30

0.09 ----- 0.20

6.40 6.50 6.60

0.65 BSC

6.4 BSC

4.30 4.40 4.50

0.45 0.60 0.75

REF:

NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MO-153, VARIATION = AC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.

WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 July 1999