Datasheet WM2638ID, WM2638CD Datasheet (Wolfson)

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Page 1

WM2638

DNL- LSB

Dual 12-Bit Serial Input Voltage Output DAC

with Internal reference

Production Data, Rev 1.0, July 1999

FEATURES

• Two 12-bit voltage output DACs

• Single 2.7V to 5.5V supply operation

• DNL ±±0.4 LSBs, INL ±±2 LSBs

• Low power consumption

• 12mW typical in fast mode

• 6mW typical in slow mode

• TMS320, (Q)SPI, and Microwire compatible

serial interface

• Programmable settling time 1µµs or 3.5µµs typical

• Power down mode 10nA

APPLICATIONS

• Battery powered test instruments

• Digital offset and gain adjustment

• Battery operated/remote industrial controls

• Machine and motion control devices

• Cellular telephones

• Wireless telephones and communication systems

• Speech synthesis

• Arbitrary waveform generation

ORDERING INFORMATION

DEVICE TEMP. RANGE PACKAGE

WM2638CD 0° to 70°C 8-pin SOIC

WM2638ID -40° to 85°C 8-pin SOIC

DESCRIPTION

The WM2638 is a dual 12-bit voltage output, resistor string, digitalto-analogue converter. A software controlled power down mode is provided that reduces current consumption to 10nA.

The WM2638 features an internal programmable voltage reference simplifying overall system design. A reference voltage may also be supplied externally.

The device has been designed to interface efficiently to industry standard microprocessors and DSPs, including the TMS320 family. The WM2638 is programmed with a 16-bit serial word comprising of a latch address, mode control bits and DAC or control data.

Excellent performance is delivered with a typical DNL of 0.4LSBs. The programmable settling time allows the designer to optimise speed versus power consumption. The output stage is buffered by a x2 gain near rail-to-rail amplifier.

The device is available in an 8-pin SOIC package ideal for spacecritical applications. Commercial temperature (0° to 70°C) and Industrial temperature (-40° to 85°C) variants are supported.

BLOCK DIAGRAM TYPICAL PERFORMANCE

VDD

(8)

DAC OUTPUT BUFFER

WM2638

REF(6)

DIN (1)

SCLK (2)

NCS (3)

16-BIT SHIFT

AND

CONTROL

LOGIC

POWER-ON

RESET

(5)

AGND

REFERENCE

OUTPUT BUFFER

WITH OUPUT

ENABLE

REFERENCE

HOLDING

CONTROL

2-BIT

SELECT

LATCH

12-BIT DAC A LATCH

12-BIT DAC B

LATCH

2-BIT

LATCH

1.024V/2.048V SELECTABLE REFERENCE

REFERENCE

INPUT BUFFER

12-BIT DAC B LATCH

POWERDOWN/

SPEED

CONTROL

REFERENCE

INPUT

BUFFER

WOLFSON MICROELECTRONICS LTD

Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: [email protected] http://www.wolfson.co.uk

(4) OUTA

(7) OUTB

5V = VDD, V

= External, Speed = Fast mode, Load = 10k/100pF

0.8

0.6

0.4

0.2

-0.2

-0.4

-0.6

-0.8

REF

-1 0 512 1024 1536 2048 2559 3071 3583 4095

DIGITAL CODE

Production Data contains final specifications

current on publication date. Supply of products

conforms to Wolfson Microelectronics' Terms

Last printed 15/07/99 15:58

1999 Wolfson Microelectronics Ltd.

and Conditions.

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WM2638 Production Data

PIN CONFIGURATION

DIN

SCLK

NCS

OUTA

1 2 3 4

VDD

OUTB

REF

AGND

PIN DESCRIPTION

PIN NO NAME TYPE DESCRIPTION

1 2 3 4 5 6 7 8

DIN Digital input Serial data input.

SCLK Digital input Serial clock input.

NCS Digital input Chip select. This pin is active low. OUTA Analogue output DAC A analogue output. AGND Supply Analogue ground.

REF Analogue I/O Reference voltage input/output. OUTB Analogue output DAC B analogue output

VDD Supply Positive power supply.

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified

ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device.

CONDITION MIN MAX

Supply voltage, VDD to AGND Digital input voltage range to AGND Reference input voltage range to AGND Output voltage at OUT from external source Operating temperature range, T

Storage temperature Lead temperature 1.6mm (1/16 inch) soldering for 10 seconds

WM2638C WM2638I

-0.3V VDD + 0.3V

0°C

-40°C

-65°C 150°C

VDD + 0.3V

70°C 85°C

260°C

RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Supply voltage High-level digital input voltage Low-level digital input voltage Reference voltage to REF Load resistance Load capacitance Serial clock rate Operating free-air temperature

Note: Reference voltages greater than VDD/2 will cause saturation for large DAC codes.

VDD 2.7 5.5 V

V V

REF

R C

SCLK

IH IL

L L

WM2638C 0 70 °C

WM2638I -40 85 °C

2 0.8 V

VDD - 1.5 V

2 kΩ

100

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 99

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WM2638 Production Data

ELECTRICAL CHARACTERISTICS

Test Conditions:

RL = 10kΩ, CL = 100pF. VDD = 5V ± 10%, V temperature range (unless noted otherwise)

PARAMETER Static DAC Specifications

Resolution Integral non-linearity Differential non-linearity Zero code error Gain error D.c. power supply rejection ratio Zero code error temperature coefficient Gain error temperature coefficient

DAC Output Specifications

Output voltage range Output load regulation

Power Supplies

Active supply current

Power down supply current

Dynamic DAC Specifications

Slew rate

Settling time

Glitch energy Signal to noise ratio

Signal to noise and distortion ratio

= 2.048V and VDD = 3V ± 10%, V

REF

SYMBO

TEST CONDITIONS MIN TYP MAX UNIT

= 1.024V over recommended operating free-air

REF

12 bits

INL See Note 1 DNL See Note 2 ZCE See Note 3

GE See Note 4

±2.0 ±4.0 ±0.4 ±1

±24 ±0.6

LSB LSB

% FSR

DC PSRR See Note 5 0.5 mV/V

See Note 6 10 ppm/°C See Note 6 10 ppm/°C

0 VDD - 0.4 V

2kΩ to 10kΩ load

±0.1 ±0.25

See Note 7

No load, V

VDD = 5V, V

VDD = 3V, V

= VDD, V

REF

= 2.048V, Internal

Slow

Fast

= 2.048V, External

REF

Slow

Fast

= 1.024V, Internal

REF

Slow

Fast

= 1.024V, External

REF

Slow

Fast

= 0V

2.2

4.3

1.8

3.9

1.8

3.8

1.5

3.5

2.7

5.2

2.2

4.8

2.3

4.7

1.9

4.3

mA mA

See Note 8

No load,

0.01 10 µA

all digital inputs 0V or VDD,

See Note 9

DAC code 32 to 4095, 10%-90%

Slow Fast

1.5

8.0

V/µs V/µs

See Note 10

DAC code 32 to 4095

Slow Fast

3.5

1.0

µs µs

See Note 11

Code 2047 to 2048 10 nV-s

SNR fs = 400ksps, f

= 1kHz,

OUT

69 74 dB BW = 20kHz See Note 12

SNRD fs = 400ksps, f

= 1kHz,

OUT

58 67 dB BW = 20kHz See Note 12

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 99

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WM2638 Production Data

Test Conditions:

RL = 10kΩ, CL = 100pF. VDD = 5V ± 10%, V temperature range (unless noted otherwise)

PARAMETER

Total harmonic distortion

Spurious free dynamic range

Reference configured as input

Reference input resistance Reference input capacitance Reference feedthrough

Reference input bandwidth

Reference configured as output

Low reference voltage High reference voltage Output source current Output sink current Load Capacitance PSRR

Digital Inputs

High level input current Low level input current Input capacitance

Notes:

1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects of zero code and full scale errors).

2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in digital input code.

3. Zero code error is the voltage output when the DAC input code is zero.

4. Gain error is the deviation from the ideal full scale output excluding the effects of zero code error.

5. Power supply rejection ratio is measured by varying VDD from 4.5V to 5.5V and measuring the proportion of this signal imposed on the zero code error and the gain error.

6. Zero code error and Gain error temperature coefficients are normalised to full scale voltage.

7. Output load regulation is the difference between the output voltage at full scale with a 10kΩ load and 2kΩ load. It is expressed as a percentage of the full scale output voltage with a 10kΩ load.

8. IDD is measured while continuously writing code 2048 to the DAC. For V increase.

9. Typical supply current in power down mode is 10nA. Production test limits are wider for speed of test.

10. Slew rate results are for the lower value of the rising and falling edge slew rates

11. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling edges. Limits are ensured by design and characterisation, but are not production tested.

12. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency f fs.

= 2.048V and VDD = 3V ± 10%, V

REF

SYMBO

TEST CONDITIONS MIN TYP MAX UNIT

THD fs = 400ksps, f

BW = 20kHz See Note 12

SPFDR fs = 400ksps, f

BW = 20kHz See Note 12

REFIN

= 1VPP at 1kHz

REF

+ 1.024V dc, DAC code 0

= 0.2VPP + 1.024V dc

REF

DAC code 2048

Slow

Fast

REFOUTL

REFOUTH

REFSRC

REFSNK

VDD > 4.75V 2.027 2.048 2.069 V

Input voltage = VDD 1 µA

Input voltage = 0V -1 µA

= 1.024V over recommended operating free-air

REF

OUT

= 1kHz,

57 72 dB

-69 -57 dB

10 MΩ 55 pF

-60 dB

1.0

1.003 1.024 1.045 V

-1 mA

-48 dB

8 pF

< VDD - 0.7V and VIL > 0.7V supply current will

generated with a sampling frequency

OUT

MHz MHz

1 mA

100 pF

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 99

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WM2638 Production Data SERIAL INTERFACE

SUCSS

NCS

SCLK

SUDCLK

WCLtWCH

HDCLK

SUCS1

SUCS2

DIN

D15 D14 D13 D12 D11 D0

Figure 1 Timing Diagram Test Conditions:

RL = 10kΩ, CL = 100pF. VDD = 5V ±± 10%, V

= 2.048V and VDD = 3V ±± 10%, V

REF

= 1.024V over recommended operating free-

REF

air temperature range (unless noted otherwise)

SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

SUCSS

SUSCS1

SUSCS2

WCL

WCH

SUDCLK

HDCLK

Setup time NCS low before SCLK low Setup time, rising edge of SCLK to rising edge of NCS,

external end of write Setup time, rising edge of SCLK to falling edge of NCS,

start of next write cycle Pulse duration, SCLK high Pulse duration, SCLK low Setup time, data ready before SCLK falling edge Hold time, data held valid after SCLK falling edge

10 ns 10 ns

5 ns

25 ns 25 ns 10 ns

5 ns

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 99

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WM2638 Production Data

INL - LSB

OUTPUT VOLTAGE - V

TYPICAL PERFORMANCE GRAPHS

VDD = 5V, V

-1

-2

-3 0 512 1024 1536 2048 2559 3071 3583 4095

Figure 2 Integral Non-Linearity

0.4

0.35

0.3

0.25

0.2

0.15

0.1

0.05

0 1 2 3 4 5 6 7 8 9 10

= External 2.048V, Speed = Fast Mode, Load = 10k/100pF

REF

VDD = 3V, V

= 1V, Input Code = 0

REF

ISINK- mA

DIGITAL CODE

Slow Fast

0.4

VDD = 5V, V

0.35

0.3

0.25

0.2

0.15

0.1

0.05

0 1 2 3 4 5 6 7 8 9 10

= 2V, Input Code = 0

REF

ISINK - mA

Slow Fast

Figure 3 Sink Current VDD = 3V Figure 4 Sink Current VDD = 5V

2.06

VDD = 3V, V

2.055

2.05

2.045

2.04

2.035

2.03

2.025

2.02 0 1 2 3 4 5 6 7 8 9 10 11

= 1V, Input Code = 4095

REF

ISOURCE- mA

Slow Fast

4.1

VDD = 5V, V

4.095

4.09

4.085

4.08

4.075

4.07

4.065

4.06 0 1 2 3 4 5 6 7 8 9 10 11

= 2V, Input Code = 4095

REF

ISOURCE - mA

Slow Fast

Figure 5 Source Current VDD = 3V Figure 6 Source Current VDD = 5V

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 99

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WM2638 Production Data

DEVICE DESCRIPTION

GENERAL FUNCTION

The device uses a resistor string network buffered with an op amp to convert 12-bit digital data to analogue voltage levels (see Block Diagram). The output voltage is determined by the reference input voltage and the input code according to the following relationship:

Output voltage =

INPUT OUTPUT

1111 1111 1111

: :

1000 0000 0001

1000 0000 0000

0111 1111 1111

: :

0000 0000 0001

0000 0000 0000 0V

Table 1 Binary Code Table (0V to 2V

( )

V2 REF

CODE

4096

( )

Output), Gain = 2

REF

4095

( )

V2 REF

4096

2049

( )

V2 REF

4096

2048

V2 =

4096

2047

( )

V2 REF

4096

( )

V2 REF

4096

REFREF V

POWER ON RESET

An internal power-on-reset circuit resets the DAC registers to all 0s on power-up.

BUFFER AMPLIFIER

The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a 2kΩ load with a 100pF load capacitance.

SERIAL INTERFACE

When chip select (NCS) is low, the input data is read into a 16-bit shift register with the input data clocked in most significant bit first. The falling edge of the SCLK input shifts the data into the input register. After 16 bits have been transferred, the next rising edge on SCLK or NCS then transfers the data to the DAC latch. When NCS is high, input data cannot be clocked into the input register (see Table 2).

SERIAL CLOCK AND UPDATE RATE

Figure 1 shows the device timing. The maximum serial rate is: f

max = MHz20

SCLK

The digital update rate is limited to an 800ns period, or 1.25MHz frequency. However, the DAC settling time to 12 bits limits the update rate for large input step transitions.

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 99

minWCLminWCH

Page 8

WM2638 Production Data

SOFTWARE CONFIGURATION OPTIONS

The 16 bits of data can be transferred with the sequence shown in Table 2. D11-D0 contains the 12-bit data word. D15-D12 hold the programmable options which are summarized in Table 3.

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

R1 SPD PWD R0 New DAC value or control register value

Table 2 Serial Word Format

PROGRAMMABLE SETTLING TIME

Settling time is a software selectable 3.5µs or 1µs typical, to within ±0.5LSB of final value. This is controlled by the value of D14. A ONE defines a settling time of 1µs, a ZERO defines a settling time of 3.5µs.

PROGRAMMABLE POWER DOWN

The power down function is controlled by D13. A ZERO configures the device as active, or fully powered up, a ONE configures the device into power down mode. When the power down function is released the device reverts back to the DAC code set prior to power down.

A separate internal control register is available. This is accessed from the register access bits R1 (Bit D15) and R0 (Bit D12).

(BIT D15)

0 0 0 1 1 0 1 1

Table 3 Programmable Options

(BIT D12)

Write data to DAC B and BUFFER Write data to BUFFER Write data to DAC A and update DAC B with BUFFER content Write data to control register

The contents of the control register, shown below in Table 3, are used to program the internal reference function

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

x x x x x x x x x X REF1 REF0

Table 4 Control Register Contents

PROGRAMMABLE INTERNAL REFERENCE

The reference can be sourced internally or externally under software control. If an external reference voltage is applied to the REF pin, the device must be configured to accept this.

If an external reference is selected, the reference voltage input is buffered which makes the DAC input resistance independent of code. The REF pin has an input resistance of 10MΩ and an input capacitance of typically 55pF. The reference voltage determines the DAC full-scale output.

If an internal reference is selected, a voltage of 1.024V or 2.048V is available. The internal reference can source up to 1mA and can therefore be used as an external system reference.

REF1

(BIT D1)

0 0 External 0 1 1.024V 1 0 2.048V 1 1 External

Table 5 Internal Reference Options

REF0

(BIT D0)

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 99

Page 9

WM2638 Production Data

Examples:

1. Set internal reference voltage to 2.048V D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1 x 0 1 x x x x x x x x x x 1 0

2. Write new DAC A value and update DAC A output D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 x 0 0 New DAC A output value

FUNCTION OF THE LATCH CONTROL BITS (D15 AND D12)

PURPOSE AND USE OF THE DOUBLE BUFFER

Normally only one DAC output can change after a write. The double buffer allows both DAC outputs to change after a single write. This is achieved by the two following steps.

• A double buffer only write is executed to store the new DAC B data without changing the DAC A

and B outputs.

• Following the previous step, a write to latch A is executed. This writes the serial interface register

(SIR) data to latch A and also writes the double buffer contents to latch B. Thus both DACs receive their new data at the same time and so both DAC outputs begin to change at the same time.

Unless a double buffer only write is issued, the latch B and double buffer contents are identical. Thus, following a write to latch A or B with another write to latch A does not change the latch B contents.

Three data transfer options are possible. All transfers occur immediately after NCS goes high (or on the sixteenth positive SCLK edge, whichever is earlier) and are described in the following sections).

LATCH A WRITE, LATCH B UPDATE (D15 = HIGH, D12 = LOW)

The serial interface register (SIR) data are written to latch A and the double buffer latch contents are written to latch B. The double buffer contents are unaffected. This program bit condition allows simultaneous output updates of both DACs.

SERIAL

LATCH A TO DAC A

INTERFACE

D12 = LOW D15 = HIGH

Figure 2 Latch A Write, Latch B Update LATCH B AND DOUBLE BUFFER 1 WRITE (D15 = LOW, D12 = LOW)

The SIR data are written to both latch B and the double buffer. Latch A is unaffected.

SERIAL

DOUBLE

BUFFER LATCH

LATCH B TO DAC B

LATCH A TO DAC A

INTERFACE

D12 = LOW D15 = LOW

Figure 3 Latch B and Double Buffer Write DOUBLE BUFFER ONLY WRITE (D15 = LOW, D12 = HIGH)

The SIR data are written to the double buffer only. Latch A and B contents are unaffected.

DOUBLE

BUFFER LATCH

LATCH B TO DAC B

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 99

Page 10

WM2638 Production Data

SERIAL

LATCH A TO DAC A

INTERFACE

D12 = HIGH D15 = LOW

Figure 4 Double Buffer Only Write OPERATIONAL EXAMPLES

1. changing the latch A data from zero to full code

Assuming that latch A starts at zero code (e.g. after power up), the latch can be filled with 1s by writing (bit D15 on the left, D0 on the right)

1X00 1111 1111 1111 to the serial interface. Bit D14 can be zero to select slow mode or one to select fast mode. The latch B contents and DAC B output are not changed by this write unless the double buffer

contents are different from the latch B contents. This can only be true if the last write was a double buffer-only write.

2. changing the latch B data from zero to full code

Assuming that latch B starts at zero code (e.g. after power up), the latch can be filled with 1s by writing (bit D15 on the left, D0 on the right)

DOUBLE

BUFFER

LATCH B TO DAC B

0X00 1111 1111 1111 to the serial interface. Bit D14 can be zero to select slow mode or one to select fast mode. The data

(bits D0 to D11) are written to both the double buffer and latch B. The latch A contents and the DAC A output are not changed by this write.

3. double buffered change of both DAC outputs

Assuming that DACs A and B start at zero code (e.g. after power up), if DAC A is to be driven to mid-scale and DAC B to full-scale, and if the outputs are to begin rising at the same time, this can be achieved as follows:

First, 0d01 1111 1111 1111

is written (bit D15 on the left, D0 on the right) to the serial interface. This loads the full-scale code into the double buffer but does not change the latch B contents and the DAC B output voltage. The latch A contents and the DAC A output are also unaffected by this write operation.

Changing from fast to slow to fast mode changes the supply current which can glitch the outputs, and so D14 (designated by d in the above data word) should be set to maintain the speed mode set by the previous write.

Next, 1d00 1000 0000 0000 is written (bit D15 on the left, D0 on the right) to the serial interface. This writes the mid-scale code

(100000000000) to latch A and also copies the full-scale code from the double buffer to latch B. Both DAC outputs thus begin to rise after the second write.

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 99

Page 11

WM2638 Production Data

PACKAGE DIMENSIONS

D: 8 PIN SOIC 3.9mm Wide Body

0.10 (0.004)

E H

-C-

SEATING PLANE

h x 45

DM009.B

Symbols

Dimensions

(mm)

Dimensions

(Inches)

MIN MAX MIN MAX A A

1.35 1.75 0.0532 0.0688

0.10 0.25 0.0040 0.0098

B 0.33 0.51 0.0130 0.0200 C D e E h

0.19 0.25 0.0075 0.0098

4.80 5.00 0.1890 0.1968

1.27 BSC 0.050 BSC

3.80 4.00 0.1497 0.1574

0.25 0.50 0.0099 0.0196

H 5.80 6.20 0.2284 0.2440 L

αα

REF:

NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES). B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN). D. MEETS JEDEC.95 MS-012, VARIATION = AA. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.

0.40 1.27 0.0160 0.0500

JEDEC.95, MS-012

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 99