Page 1
WM2636
12-bit Serial Input Voltage Output DAC
with Internal Reference
Production Data, July 1999, Rev 1. 0
FEATURES
• 12-bit voltage output DAC
• Single supply from 2.7V to 5.5V
• DNL ±0.5 LSBs, INL ±2. 0 LSBs
• Very low power consumption (3V supply):
- 4.2mW, slow mode
- 8.1mW, fast mode
• TMS320, (Q)SPI, and Microwire compatible serial
interface
• Programmable settling time of 3.5µs or 1µs typical
• High impedance reference input buffer
• Power down mode 10nA
APPLICATIONS
• Battery powered test instruments
• Digital offset and gain adjustment
• Battery operated/remote industrial controls
• Machine and motion control devices
• Wireless telephone and communication systems
• Speech synthesis
• Arbitrary waveform generation
ORDERING INFORMATION
DEVICE TEMP. RANGE PACKAGE
WM2636CD 0° to 70°C 8-pin SOIC
WM2636ID -40° to 85°C 8-pin SOIC
DESCRIPTION
The WM2636 is a 12-bit volt age output, res istor s tring digi tal-toanalogue converter that can be powered down under software
control. Power down reduces current consumption to 10nA.
An internal precision voltage reference is provided which can
source up to 1mA. This can therefore be used as an external
system reference.
The device has been designed to interface effi ciently t o industry
standard microprocessors and DSPs, including the TMS320
family. The W M2636 is programmed with a 16-bit serial word
comprising 4 control bits and 12 data bits.
Excellent performance is delivered with a typical DNL of 0.5
LSBs. The settling t ime of the DAC is programmable to al low
the designer to optimize speed versus power dissipation. The
output stage is buffered by a x2 gain near rail-t o-rai l amplifier.
The device is available in an 8-pin SOI C package. Commerc ial
temperature (0° to 70°C) and Industrial temperature (-40° to
85°C) variants are supported.
BLOCK DIAGRAM TYPICAL PERFORMANCE
VDD
(8)
REFERENCE
OUTPUT BUFFER
REF(6)
DIN (1)
SCLK (2)
NCS (3)
FS (4)
WITH OUPUT
ENABLE
16-BIT
SHIFT
REGISTER
AND
CONTROL
LOGIC
POWER-ON
RESET
(5)
AGND
X1
REFERENCE
2-BIT
SELECT
LATCH
data
1.024V/2.048V
SELECTABLE
REFERENCE
12-BIT
DAC
LATCH
2-BIT
CONTROL
LATCH
REFERENCE INPUT
BUFFER
X1
POWERDOWN/
SPEED
CONTROL
OUTPUT
BUFFER
WM2636
DAC
X2
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edi nburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: [email protected]
http://www.wolfson.co.uk
(7) OUT
1
VDD = 5V, V
= External, Speed = Fast mode, Load = 10k/100pF
0.8
0.6
0.4
0.2
0
DNL - LSB
-0.2
-0.4
-0.6
-0.8
-1
0 512 1024 1536 2048 2559 3071 3583 4095
REF
DIGITAL CODE
Production Data contain final specifications
current on publication date. Supply of
products conforms to Wolfson
Microelectronics’ Terms and Condit i ons.
1999 Wolfson Microelectronics Ltd.
Page 2
WM2636 Production Data
PIN CONFIGURATION
DIN
SCLK
NCS
FS
1
2
3
4
VDD
8
OUT
7
REF
6
AGND
5
PIN DESCRIPTION
PIN NO NAME TYPE DESCRIPTION
1
2
3
4
5
6
7
8
DIN Digital input Serial data input.
SCLK Digital input Serial clock i nput.
NCS Digital input Chip select. This pin is active low.
FS Digit al i nput Fram e synchronisation for serial input data.
AGND Supply Analogue ground.
REF Analogue I/O Analogue reference voltage input/output.
OUT Analogue output DAC analogue output
VDD Supply Positive power supply.
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are s tres s rat ings only. P erm anent damage to the device may be c aused by c onti nuously operat ing at
or beyond these limits. Device functional operating lim its and guaranteed performance s pecifications are gi ven under Electrical
Characteristics at the test conditions s pecified
ESD Sensitive Device. Thi s device i s m anufactured on a CMOS process . It i s t herefore generi cally suscept ible
to damage from excessi ve stati c voltages . Proper ES D precautions mus t be tak en during handling and st orage
of this device.
CONDITION MIN MAX
Supply voltage, VDD to AGND
Digital input voltage
Reference input voltage
Operating temperature range, T
A
WM2636CD
WM2636ID
Storage temperature
Lead temperature 1.6mm (1/16 inch) soldering for 10 sec onds
-0.3V VDD + 0.3V
-0.3V VDD + 0.3V
0°C
-40°C
-65°C 150°C
7V
70°C
85°C
260°C
RECOMMENDED OPERATING CONDITIONS
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Supply voltage
High-level digital input voltage
Low-level digital input voltage
Reference voltage to REF
Load resistance
Load capacitance
Serial clock rate
Operating free-air temperature
Note: Reference voltages greater than V DD/ 2 will caus e saturation for large DAC codes.
VDD 2.7 5.5 V
V
F
V
IH
V
IL
REF
R
C
SCLK
T
A
L
L
VDD = 2.7V to 5.5V 2 V
VDD = 2.7V to 5.5V 0.8 V
See Note
VDD - 1.5 V
210 kΩ
100 pF
20 MHz
WM2636CD 0 70 °C
WM2636ID -40 85 °C
WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 1999
2
Page 3
WM2636 Production Data
ELECTRICAL CHARACTERISTICS
Test Conditions:
R
= 10kΩ, CL = 100pF. VDD = 5V ± 10%, V
L
free-air temperature range (unless noted otherwise).
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Static DAC Specifications
Resolution
Integral non-linearity
Differential non-linearity
Zero code error
Gain error
D.c. power supply rejection rati o
Zero code error temperature coeffi cient
Gain error temperature coefficient
DAC Output Specifications
Output voltage range
Output load regulation
Power Supplies
Active supply current
Power down supply current
Dynamic DAC Specifications
Slew rate
Settling time
Glitch energy
Signal to noise ratio
Signal to noise and distort i on rat i o
Total harmonic distort i on
Spurious free dynamic range
= 2.048V and VDD = 3V ± 10%, V
REF
= 1.024V over recommended operati ng
REF
12 bits
INL See Note 1
DNL See Note 2
ZCE See Note 3
GE See Note 4
±2.0 ±4.0
±0.5 ±1.0
±20
±0.6
LSB
LSB
mV
% FSR
DC PSRR See Note 5 0.5 mV/V
See Note 6 10 ppm/°C
See Note 6 10 ppm/°C
0 VDD - 0.1 V
2kΩ to 10kΩ load
±0.1 ±0.25
%
See Note 7
I
DD
No load, V
V
REF
V
REF
V
REF
V
REF
= VDD, V
IH
VDD = 5V,
= 2.048V Slow
VDD = 5V,
= 2.048V Fast
VDD = 3V,
= 1.024V Slow
VDD = 3V,
= 1.024V Fast
IL
= 0V
1.6 1.9 mA
2.9 3.4 mA
1.4 mA
2.7 mA
See Note 8
No load,
0.01 10 µA
all digital inputs 0V or VDD
See Note 9
DAC code 128 to 4095,
10%-90% See Note 10
Slow
Fast
14
2
V/µs
V/µs
DAC code 128 to 4095
See Note 11
Slow
Fast
3.5
1.0
µs
µs
Code 2047 to 2048 10 nV-s
SNR fs = 400ksps, f
OUT
= 1kHz,
71 75 dB
BW = 20kHz
See Note 12
SNRD fs = 400ksps, f
OUT
= 1kHz,
59 66 dB
BW = 20kHz See Not e 12
THD fs
= 400ksps, f
OUT
= 1kHz,
-67 -59 dB
BW = 20kHz See Not e 12
SPFDR fs
= 400ksps, f
OUT
= 1kHz,
59 69 dB
BW = 20kHz See Not e 12
WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 1999
3
Page 4
WM2636 Production Data
Test Conditions:
R
= 10kΩ, CL = 100pF. VDD = 5V ± 10%, V
L
free-air temperature range (unless noted otherwise).
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Reference Configured as Input
Reference input resistanc e
Reference input capacitanc e
Reference feedthrough
Reference input bandwidth
Reference configured as output
Low reference voltage
High reference voltage
Output source current
Output sink current
Load Capacitance
PSRR
Digital Inputs
High level input current
Low level input current
Input capacitance
Notes:
1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding t he effects
of zero code and full scale errors ).
2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude c hange of any adjacent two
codes. A guarantee of monotonicity means the output voltage changes in the sam e di rection (or remains constant) as a change in
digital input code.
3. Zero code error is the voltage output when the DAC input code i s zero.
4. Gain error is the deviation from the ideal full scale output excludi ng t he effects of zero code error.
5. Power supply rejection ratio is measured by varying VDD from 4.5V to 5. 5V and measuring the proportion of t hi s signal imposed
on the zero code error and the gain error.
6. Zero code error and Gain error temperature coefficients are norm al i sed to full scale voltage.
7. Output load regulation is the difference between the output voltage at full scale with a 10kΩ load and 2kΩ load. It is expressed as
a percentage of the full sc al e out put voltage with a 10kΩ load.
8. I
is measured while continuous l y writing code 2048 to the DAC. For VIH < VDD - 0.7V and VIL > 0.7V supply current will increase.
DD
9. Typical supply current in power down mode is 10nA. Production test limits are wider for speed of test.
10. Slew rate results are for the lower value of the rising and falling edge slew rates
11. Settling time is the time taken for the signal t o settle to within 0.5LSB of the final measured value for both rising and falling edges.
Limits are ensured by desi gn and characterisation, but are not production tested.
12. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency f
= 2.048V and VDD = 3V ± 10%, V
REF
R
REFIN
C
REFIN
V
= 1VPP at 1kHz
REF
+ 1.024V dc, DAC code 0
V
= 0.2VPP + 1.024V dc
REF
DAC code 2048
Slow
Fast
V
REFOUTL
V
REFOUTH
I
REFSRC
I
REFSNK
I
I
C
IH
IL
I
VDD > 4.75V 2.027 2.048 2.069 V
Input voltage = VDD 1 µA
Input voltage = 0V -1 µA
= 1.024V over recommended operati ng
REF
10 MΩ
55 pF
-65 dB
1.0
1.0
1.003 1.024 1.045 V
1mA
-1 mA
100 pF
-48 dB
8pF
generated with a sampling frequency f s
OUT
MHz
MHz
.
WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 1999
4
Page 5
WM2636 Production Data
SERIAL INTERFACE
*
SCLK
DIN
123451516
t
SUDtHD
t
SUCSFS
t
WLtWH
D0D1D12D13D14D15
t
SUC16CS
NCS
t
WHFS
t
SUFS
t
SUC16FS
FS
Figure 1 Timing Diagram
Test Conditions:
R
= 10kΩ, CL = 100pF. VDD = 5V ± 10%, V
L
= 2.048V and VDD = 3V ± 10%, V
REF
= 1.024V over recommended operati ng
REF
free-air temperature range (unless noted otherwise).
SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
t
SUCSFS
t
SUFS
t
SUC16FS
Setup time NCS low before negative FS edge.
Setup time FS low before firs t negative SCLK edge.
Setup time, sixteenth negat i ve edge af ter FS low on
which D0 is sampled before risi ng edge of FS.
10 ns
8ns
10 ns
Setup time, sixteenth positive SCLK edge (first
positive after D0 sam pl ed) before NCS rising edge. If
t
SUC16CS
t
WH
t
WL
t
SUD
t
HD
t
WHFS
FS is used instead of the sixteenth positive edge to
update the DAC, then the setup t i me is between the
FS rising edge and the NCS rising edge.
Pulse duration, SCLK high.
Pulse duration, SCLK low.
Setup time, data ready before SCLK falling edge.
Hold time, data held valid after SCLK falling edge.
Pulse duration, FS high.
10 ns
25 ns
25 ns
8ns
5ns
20 ns
WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 1999
5
Page 6
WM2636 Production Data
TYPICAL PERFORMANCE GRAPHS
3
VDD = 5V, V
2
1
0
INL - LSB
-1
-2
-3
0 512 1024 1536 2048 2559 3071 3583 4095
Figure 2 Integral Non-Linearity
= External 2.048V, Speed = Fast mode
REF
DIGITAL CODE
3
VDD = 3V, V
= 1V, Input Code =
REF
2.5
2
1.5
Output Voltage - V
1
0.5
0
01233.54
Isink - mA
Slow Fast
5
VDD = 5V, V
= 2V, Input Code = 0
4.5
4
3.5
3
2.5
2
Output Voltage - V
1.5
1
0.5
0
00.511.522.533.54
REF
Isink - mA
Figure 3 Sink Current VDD = 3V Figure 4 Sink Current VDD = 5V
2.071
VDD = 3V, V
= 1V, Input Code = 4095
2.0705
2.07
2.0695
2.069
2.0685
Output Voltage - V
2.068
2.0675
2.067
2.0665
2.066
REF
00.511.522.533.5 4
Isource - mA
Slow Fast
4.135
VDD = 5V, V
= 2V, Input Code = 4095
REF
4.134
4.133
4.132
Output Voltage - V
4.131
4.13
4.129
00.511.522.533.54
Isource - mA
Slow Fast
Slow Fast
Figure 5 Source Current VDD = 3V Figure 6 Source Current VDD = 5V
WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 1999
6
Page 7
WM2636 Production Data
DEVICE DESCRIPTION
GENERAL FUNCTION
The device uses a resistor s tring network buf fered with an op amp t o convert 12-bit digit al data
to analogue voltage levels (see Block Diagram). The output voltage is determined by the
reference input voltage and the input c ode according to the following relationship:
CODE
()
Output voltage =
INPUT OUTPUT
1111 1111 1111
::
1000 0000 0001
1000 0000 0000
0111 1111 1111
::
0000 0000 0001
0000 0000 0000 0V
Table 1 Binary Code Table (0V to 2V
REF
V2
4096
()
REF
V2
()
REF
V2
2048
()
V2 =
4096
()
REF
V2
()
REF
V2
Output), Gain = 2
REF
4095
4096
2049
4096
REFREF V
2047
4096
1
4096
SERIAL INTERFACE
POWER ON RESET
An internal power-on-reset circuit resets the DAC register to al l 0s on power-up.
BUFFER AMPLIFIER
The output buffer has a near rail-to-rail out put with s hort ci rcui t protec ti on and c an rel iably drive
a 2kΩ load with a 100pF load capacitance.
Explanation of data transfer:
First, the device has to be enabled with NCS set to low. Then, a falling edge of FS starts
shifting the data bit-per-bit (st arti ng with the MSB) t o the i nternal regi st er on t he fall ing edges of
SCLK. After 16 bits have been transferred or FS ris es, the c ontent of the s hif t regi st er is m oved
to the DAC latch which updates the voltage output to the new level.
The serial interface of the devi ce can be used in two basic modes :
• four wire (with chip select)
• three wire (without chip select)
Using chip select (four wire mode), it is possible to have more than one devic e connected to
the serial port of the data source (DSP or microcont roller). If there is no need to have more
than one device on the serial bus, then NCS can be tied low.
SERIAL CLOCK AND UPDATE RATE
Figure 1 shows the device timing. The maximum serial rate is:
max = MHz20
f
SCLK
The digital update rate is limited to an 800ns period, or 1.25MHz f requency. However, the DAC
settling time to 12 bits limits the update rate for large input step transitions.
1
+
=
minWCLminWCH
tt
WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 1999
7
Page 8
WM2636 Production Data
SOFTWARE CONFIGURATION OPTIONS
The 16 bits of data can be transf erred with the sequence shown in Table 2. D11-D0 contains
the 12-bit data word. D15-D12 hold the programm abl e options.
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
R1 SPD PWR R0 New DAC or control register value (12 bits)
Table 2 Serial Word Format
PROGRAMMABLE SETTLING TIME
Settling time is a sof tware s elec table 3.5 µs or 1µs, typical to within ±0.5LSB of final value. This
is controlled by the value of D14. A ONE defines a settling tim e of 1µs, a ZERO defines a
settling time of 3.5µs.
PROGRAMMABLE POWER DOWN
The power down function is controlled by D13. A ZERO c onfi gures t he devi ce as ac tive, or f ully
powered up, a ONE configures the device into power down mode. When the power down
function is released the device reverts to the DAC code s et prior to power down.
REGISTER ADDRESSING
A separate internal control regi ster is available. Thi s is acces sed from the register access bits
R1 (Bit D15) and R0 (Bit D12).
R1
(BIT D15)
00
01
10
11
Table 3 Register Access Control
The contents of the control register, shown below in Table 4, are us ed to program the internal
reference function.
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
xxXxxxxxxXREF1REF0
Table 4 Control Register Contents
R0
(BIT D12)
REGISTER
Write data to DAC
Reserved
Reserved
Write data to control register
PROGRAMMABLE INTERNAL REFERENCE
The reference can be sourced internally or externally under software control. If an external
reference voltage is applied to t he RE F pi n, the device must be configured to accept this.
If an external reference is selec ted, the reference voltage input is buffered which m akes the
DAC input resistance independent of code. The REF pin has an input resis tance of 10MΩ and
an input capacitance of typical ly 55pF. The reference voltage determines the DAC full-sc ale
output.
If an internal reference is selected, a voltage of 1.024V or 2.048 is available. The internal
reference can source up to 1m A and can therefore be used as an external system reference.
REF1 REF0) REGISTER
00
01
10
11
Table 5 Programmable Internal Reference
External
1.024V
2.048V
External
WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 1999
8
Page 9
WM2636 Production Data
Examples:
1. Set internal reference voltage to 2.048V
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1x01xxxxxxxxxx10
2. Write new DAC value and update DAC out put
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 x 0 0 New DAC value
WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 1999
9
Page 10
WM2636 Production Data
PACKAGE DIMENSIONS
D: 8 PIN SOIC 3.9mm Wide Body
e
D
A1
A
B
58
41
E H
-C-
h x 45
α
DM009.B
L
o
Symbols
0.10 (0.004)
Dimensions
(mm)
SEATING PLANE
Dimensions
(Inches)
MIN MAX MIN MAX
A
A
1
B
C
D
e
E
h
H
L
α
REF:
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES).
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN).
D. MEETS JEDEC.95 MS-012, VARIATION = AA. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
1.35 1.75 0.0532 0.0688
0.10 0.25 0.0040 0.0098
0.33 0.51 0.0130 0.0200
0.19 0.25 0.0075 0.0098
4.80 5.00 0.1890 0.1968
1.27 BSC 0.050 BSC
3.80 4.00 0.1497 0.1574
0.25 0.50 0.0099 0.0196
5.80 6.20 0.2284 0.2440
0.40 1.27 0.0160 0.0500
o
0
o
8
o
0
o
8
JEDEC.95, MS-012
C
WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 1999
10
Loading...