Page 1
WM2633
Byte-wide Parallel Input, 12-bit Volt age Output DAC
with Internal Reference
Production Data, July 1999, Rev 1. 0
FEATURES
• 12-bit voltage output DAC
• Dual supply 2.7V to 5.5V operation
• DNL ±0.3 LSBs, INL ±1. 2 LSBs
• Internal programmable voltage reference
• Programmable settling time
• 8-bit micro controller compatible interface
• Power down mode (10nA)
APPLICATIONS
• Battery powered test instruments
• Digital offset and gain adjustment
• Battery operated/remote industrial controls
• Machine and motion control devices
• Wireless telephone and communication systems
• Speech synthesis
• Arbitrary waveform generation
ORDERING INFORMATION
DEVICE TEMP. RANGE PACKAGE
WM2633CDT 0° to 70°C 20-pin TSSOP
WM2633IDT -40° to 85°C 20-pin TSSOP
DESCRIPTION
The WM2633 is a 12-bit voltage output, resist or string, digitalto-analogue converter. A hardware controlled power down mode
is provided that reduces current consumption to 10nA. The
WM2633 features an internal programm able voltage reference
simplifying overall syst em design. A ref erence voltage m ay also
be supplied externally.
The device has an 8-bit microcontroller compatible parallel
interface. The eight data LSBs, the four data MSBs, and the f ive
control bits are written using t hree di fferent addresses.
Excellent performance is delivered with a typical DNL of 0.3
LSBs and a typical INL of 1.2 LSBs. The output stage is
buffered by a x2 gain near rail-to-rail am plifier, which features a
Class A output stage (s low mode, Class AB). The set tling time
of the DAC is software or pin programmable to allow the
designer to optimise speed versus power dissipation.
The device is available in a 20-pin TSSOP package.
Commercial temperature (0° to 70°C) and Industrial
temperature (-40° to 85°C) variants are supported.
BLOCK DIAGRAM TYPICAL PERFORMANCE
DVDD
AVDD
(10)
REFERENCE
OUTPUT BUFFER
WITH OUPUT
REF(12)
SPD (9)
NPD (15)
A[0-1] (8, 7)
NCS (18)
NWE (17)
D[0-7]
(19,20, 1-6)
ENABLE
PARALLEL
INTERFACE
AND
CONTROL
LOGIC
POWER-ON
RESET
X1
2-BIT
REFERENCE
SELECT
LATCH
POWERDOWN/
CONTROL
CONTROL
4-BIT DAC
HOLDING
8-BIT DAC
HOLDING
(14)
GND
SPEED
3-BIT
LATCH
MSW
LATCH
LSW
LATCH
1.024V/2.048V
SELECTABLE
REFERENCE
(16)
NLDAC
12-BIT DAC
LATCH
REFERENCE
INPUT BUFFER
X1
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edi nburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: [email protected]
http://www.wolfson.co.uk
(11)
WM2633
DAC
OUTPUT
BUFFER
X2
(13) OUT
1
AVDD = DVDD 5V, V
0.8
0.6
0.4
0.2
0
DNL - LSB
-0.2
-0.4
-0.6
-0.8
-1
0 512 1024 1536 2048 2559 3071 3583 4095
= External. 2.048V, Speed = Fast mode, Load = 10k/100pF
REF
DIGITAL CODE
Production Data contain final specifications
current on publication date. Supply of
products conforms to Wolfson
Microelectronics’ Term s and conditions.
masterrev1.0.doc 07/ 15/ 99 3:52
1999 Wolfson Microelectronics Ltd.
Page 2
WM2633 Production Data
PIN CONFIGURATION
1
SPD
DVDD
D2
2
D3
3
D4
4
D5
5
D6
6
D7
7
A1
8
A0
9
10
20
D1
19
D0
18
NCS
17
NWE
16
NLDAC
15
NPD
14
AGND
13
OUT
12
REF
11
AVDD
PIN DESCRIPTION
PIN NO NAME TYPE DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
D2 Digital input Data input.
D3 Digital input Data input.
D4 Digital input Data input.
D5 Digital input Data input.
D6 Digital input Data input.
D7 Digital input Data input.
A1 Digital input Address input.
A0 Digital input Address input.
SPD Digit al i nput Speed s el ect. Digital input.
DVDD Supply Digital positive power supply.
AVDD Supply Analogue positi ve power supply.
REF Analogue I/O Analogue reference voltage input/ out put.
OUT Analogue output DAC analogue voltage output.
GND Supply Ground.
NPD Digital input Power down. Active low digital i nput which powers down all analogue
circuits.
NLDAC Digital input Load DAC. Digital input active low. NLDAC must be taken low to update
the DAC latch from t he hol di ng l atches.
NWE Digital input Write enable. Digital input ac tive low.
NCS Digital input Chip selec t. Digital input acti ve l ow.
D0 Digital input Data input.
D1 Digital input Data input.
WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 1999
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Production Data WM2633
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. P ermanent dam age to the device m ay be caused by c ontinuously operating at
or beyond these limits. Device f unctional operating limits and guaranteed perform ance specifications are given under Electric al
Characteristics at the test conditions s pecified
ESD Sensitive Device. Thi s device is manufactured on a CMOS process. It is therefore generically suscepti bl e to
damage from excessive static voltages . Proper ESD precautions mus t be taken during handling and storage of
this device.
CONDITION MIN MAX
Digital supply voltages, AVDD or DVDD to GND
Supply voltage differences , AVDD to DVDD
Reference input voltage
Digital input voltage range to GND
Operating temperature range, T
A
WM2633CDT
WM2633IDT
Storage temperature
Lead temperature 1.6mm (1/16 inch) soldering for 10 sec onds
-2.8V 2.8V
-0.3V AVDD + 0.3V
-0.3V DVDD + 0.3V
0°C
-40°C
-65°C 150°C
7V
70°C
85°C
260°C
RECOMMENDED OPERATING CONDITIONS
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Supply voltage
AVDD,
2.7 5.5 V
DVDD
High-level digital input voltage
Low-level digital input voltage
Reference voltage to REF
Load resistance
Load capacitance
Operating free-air temperature
V
IH
V
IL
V
REF
R
L
C
L
T
A
See Note 1 2 V
See Note 1 0.8 V
See Note 1 AVDD - 1.5 V
2kΩ
100 pF
WM2633CDT 0 70 °C
WM2633IDT -40 85 °C
Note: Reference input voltages greater t han A V DD/2 will cause saturation for large DAC codes.
WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 1999
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WM2633 Production Data
ELECTRICAL CHARACTERISTICS
Test Characteristics:
R
= 10kΩ, CL = 100pF AVDD = DVDD = 5V ± 10%, V
L
recommended operating free-ai r temperature range (unless noted otherwise).
= 2.048V and AVDD = DVDD = 3V ± 10%, V
REF
= 1.024V over
REF
PARAMETER SYMBOL
TEST
CONDITIONS
MIN TYP MAX UNIT
Static DAC Specifications
Resolution
Integral non-linearity
Differential non-linearity
Zero code error
Gain error
D.c power supply rejection ratio
Zero code error temperature
INL See Note 1
DNL See Note 2
ZCE See Note 3 12 m V
GE See Note 4
d.c. PSRR See Note 5 0.5 mV/V
See Note 6 20 ppm/°C
12 bits
±1.2 ±3
±0.3 ±0.5
±0.3
LSB
LSB
% FSR
coefficient
Gain error temperature coefficient
See Note 6 20 ppm/°C
DAC Output Specifications
Output voltage range
0 AVDD-
V
0.4
Output load regulation
2kΩ to 10kΩ load
0.1 0.3 %
See Note 7
Power Supplies
Active supply current
IDD No load, V
AVDD = DVDD = 5V, V
=DVDD, VIL=0V
IH
REF
=
2.048V, Internal
Slow
Fast
1.3
2.3
1.6
2.8
mA
mA
AVDD = DVDD = 5V
V
= 2.048V, External
REF
Slow
Fast
AVDD = DVDD = 3V, V
REF
0.9
1.9
1.2
2.4
=
mA
mA
1.024V, Internal
Slow
Fast
1.2
2.1
1.5
2.6
mA
mA
AVDD = DVDD = 3V,
V
= 1.024V, External
REF
Slow
Fast
0.9
1.8
1.1
2.3
mA
mA
See Note 8
Power down supply current
No load, all inputs 0V
0.01 1 µA
or DVDD
See Note 9
Dynamic DAC Specifications
Slew rate
DAC code 32-4095,
10%-90%
Slow
Fast
1.2
1.7
6
10
V/µs
V/µs
See Note 10
Settling time
DAC code 32-4095
Slow
Fast
3.5
µs
1
µs
See Note 11
WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 1999
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Production Data WM2633
Test Characteristics:
R
= 10kΩ, CL = 100pF AVDD = DVDD = 5V ± 10%, V
L
= 2.048V and AVDD = DVDD = 3V ± 10%, V
REF
= 1.024V over
REF
recommended operating free-ai r temperature range (unless noted otherwise).
PARAMETER SYMBOL
Glitch energy
Signal to noise ratio
SNR f
Code 2047 to code 2048 5 nV-s
f
OUT
TEST
CONDITIONS
= 480ksps,
S
= 1kHz BW = 20kHz,
MIN TYP MAX UNIT
73 78 dB
TA=25°C See Note 12
Signal to noise and distort i on rat i o
SNRD f
f
= 1kHz BW = 20kHz,
OUT
= 480ksps,
S
61 67 dB
TA=25°C See Note 12
Total harmonic distort i on
THD f
f
= 1kHz BW = 20kHz,
OUT
= 480ksps,
S
-69 -62 dB
TA=25°C See Note 12
Spurious free dynamic range
SPFDR f
= 1kHz BW = 20kHz, TA =
f
OUT
= 480ksps,
S
63 74 dB
25°C See Note 12
Reference Configured as Input
Reference input resistanc e
Reference input capacitanc e
Reference feedthrough
RREF 10 MΩ
CREF 55 pF
V
=1VPP at 1kHz
REF
-60 dB
+ 1.024V d.c., DAC code 0
Reference input bandwidth
V
= 0.2VPP + 1.024V d.c.
REF
DAC code 2048
Slow
Fast
500
900
kHz
kHz
Reference Configured as Output
Low reference voltage
High reference voltage
Output source current
Output sink current
Load Capacitance
PSRR
V
REFOUTL
V
REFOUTH
I
REFSRC
I
REFSNK
1.003 1.024 1.045 V
VDD > 4.75V 2.027 2.048 2.069 V
1mA
-1 mA
100 pF
-48 dB
Digital Inputs
High level input current
Low level input current
Input capacitance
I
IH
I
IL
C
I
Input voltage = DVDD 1 µA
Input voltage = 0V -1 µA
8pF
Notes:
1. Integral non-linearity (INL) is the maximum devi ation of the output from t he l i ne between zero and full scale excluding
the effects of zero c ode and full scale errors).
2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LS B amplitude change
of any adjacent two codes. A guarantee of monotonicity means the output voltage changes in t he same
direction (or remains constant) as a change in digital i nput code.
3. Zero code error is the voltage output when the DAC input code i s zero.
4. Gain error is the deviation from the ideal full scale output excluding the effec ts of zero code error.
5. Power supply rejection ratio is measured by varying AVDD from 4.5V to 5.5V and measuring the
proportion of this signal imposed on the zero code error and the gain error.
6. Zero code error and Gain error temperature coefficients are norm al i sed to full scale voltage.
7. Output load regulation is the difference between the output voltage at full scale with a 10kΩ load and 2kΩ
load. It is expressed as a percent age of the full scale output vol tage with a 10kΩ load.
WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 1999
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Page 6
WM2633 Production Data
is measured while continuous l y writing code 2048 to the DAC. For VIH < DVDD - 0.7V and VIL > 0.7V
8. I
DD
supply current will increase.
9. Typical supply current in powerdown mode is 10nA. Production test limits are wider for speed of test.
10. Slew rate results are for the lower value of the rising and falling edge s l ew rates.
11. Settling time is the time taken for the signal to settle to within 0.5LSB of the final meas ured val ue f or both rising and
falling edges. Limits are ensured by design and characterisation, but are not production tested.
12. SNR, SNRD, THD and SPFDR are measured on a synthesi sed sinewave at frequency f
a sampling frequency f
.
S
generated with
OUT
PARALLEL INTERFACE
D[0-7]
A[0-1]
t
SUCSWE
NCS
NWE
NLDAC
Figure 1 Timing Diagram
SYMBOL TEST
CONDITIONS
t
SUCSWE
t
SUD
t
HD
t
SUA
t
SUWELD
t
WWE
t
WLD
Setup time NCS low before posi t i ve NWE edge
Data ready before positive NWE edge
Data hold after positive NWE edge
Setup time for address bits A0, A1
Positive NWE edge before NLDAC low
High pulse width of NWE
Low pulse width of NLDAC
t
SUD
t
HD
DataX X
t
SUA
t
HA
AddressX X
t
WWE
t
SUWELD
t
WLD
MIN TYP MAX UNIT
15 ns
10 ns
5ns
20 ns
5ns
20 ns
23 ns
WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 1999
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Production Data WM2633
Figure
Source Current AVDD = 5V
TYPICAL PERFORMANCE GRAPHS
3
AVDD = DVDD = 5V, V
2
1
0
INL - LSB
-1
-2
-3
0 512 1024 1536 2048 2559 3071 3583 4095
Figure 2 Integral Non-Linearity
= External. 2.048 V, Spee d = Fast mode, Load = 1 0k/100pF
REF
DIGITAL CODE
3
AVDD = DVDD = 3V, V
Input Code = 0
2.5
2
1.5
Vo - OUTPUT VOLTAGE - V
1
0.5
0
00.511.522.533.54
= Internal. 1V,
REF
ISINK - mA
Slow Fast
5
AVDD = DVDD = 5V, V
4.5
4
3.5
3
2.5
2
Vo - OUTPUT VOLTAGE - V
1.5
1
0.5
0
00.511.522.533.54
= Int. 2V, Input Code = 0
REF
ISINK - mA
Figure 3 Sink Current AVDD = 3V Figure 4 Sink Current AVDD = 5V
2.0395
AVDD = DVDD = 3V, V
2.039
2.0385
2.038
2.0375
2.037
2.0365
Vo - OUTPUT VOLTAGE - V
2.036
2.0355
2.035
00.511.52 2.533.54
= Int. 1V, Input Code = 4095
REF
ISOURCE - mA
Slow Fast
4.0795
AVDD = DVDD = 5V, V
4.079
4.0785
4.078
4.0775
4.077
4.0765
Vo - OUTPUT VOLTAGE - V
4.076
4.0755
4.075
00.511.52 2.533.54
= Int. 2V, Input Code = 409
REF
ISOURCE - mA
Slow Fas)
5
Slow Fast
Figure 5 Source Current AVDD = 3V
WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 1999
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WM2633 Production Data
DEVICE DESCRIPTION
GENERAL FUNCTION
The device uses a resistor string network buffered with an op amp to convert 12-bi t digital data to
analogue voltage levels (see Block Diagram). The output voltage is determined by the reference
input voltage and the input code according to the following relationship:
CODE
()
Output voltage =
INPUT OUTPUT
1111 1111 1111
::
1000 0000 0001
1000 0000 0000
0111 1111 1111
::
0000 0000 0001
0000 0000 0000 0V
Table 1 Binary Code Table (0V to 2V
V2
REF
4096
4095
()
V2
REF
4096
2049
()
REF
V2
4096
2048
()
V2 =
4096
()
V2
REF
()
V2
REF
Output), Gain = 2
REF
REFREF V
2047
4096
1
4096
POWER ON RESET
An internal power-on-reset circuit resets the DAC register to al l 0s on power-up.
BUFFER AMPLIFIER
The output buffer has a near rail-to-rail out put with short circuit protec tion and can reliably drive a
2kΩ load with a 100pF load capacitance.
EXTERNAL REFERENCE
If an external reference is selec ted, the reference voltage input is buffered which m akes the DAC
input resistance independent of code. The REF pin has an input res istance of 10MΩ and an input
capacitance of typical l y 55pF. The reference voltage determines t he DAC full-scale output.
HARDWARE CONFIGURATION OPTIONS
The device has three configuration options that are controlled by devic e pi ns.
DEVICE POWER DOWN
The device can be powered-down by pulling pin NPD (pin 15) high. This powers down the DAC. This
will reduce power consumption significantly. The NPD pin low overrides the software control bit
PWR. W hen the power down function is released the device reverts to the DAC code set prior to
power down.
SETTLING TIME
The settling time of the device can be controlled by pin SPD (pin 9). A ONE on pin SPD will ensure a
FAST settling time; a ZERO will ensure a SLOW settling time. The SPD pin high overrides the
software control bit SPD.
SIMULTANEOUS DAC UPDATE
The NLDAC pin (Pin 16) can be held high to prevent word writes from updating the DAC latc h. By
writing the new value to the DAC then pulling NLDAC low, the new DAC code is loaded int o t he DAC
latch.
WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 1999
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Production Data WM2633
PARALLEL INTERFACE
The device latches data on the positive edge of NWE. It m us t be enabled with NCS low. Whether the
data is written to one of the DAC holdi ng l atches (MSW, LS W) or the control regi ster, depends on t he
address bits A1 and A0. NLDA C low updates the DAC with the val ue in the hol ding latc h. NLDAC is
an asynchronous input and can be held low, if a synchronous update is not necessary. Alternatively,
the RLDAC bit of the control register can be used to synchonously updat e the DAC l atc h via s oft ware
control.
D[0-7]
A[0-1]
NCS
NWE
NLDAC
X
MSW LSWXX
10XX
Figure 7 Example of a Complete Write Cycle Using NLDAC to Update the DAC
D[0-7]
X MSW LSWX
ControlX X
A[0-1]
NCS
NWE
NLDAC
X 3X X
01X
Figure 8 Example of a Complete Write Cycle Using the Control Word to Update the DAC. If NLDAC is held high as
shown above, the DAC latch is normally closed, but can be made transparent by setting the RLDAC control register bit
high. The procedure shown assumes t hat the RLDAC bit is low at the start and is written high on the final write.
WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 1999
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WM2633 Production Data
SOFTWARE CONFIGURATION OPTIONS
DATA FORMAT
The WM2613 writes data either to one of the DAC holding latches or to the control register
depending on the address bits A1 and A0.
A1 A0 LATCH D7D6D5D4D3D2D1D0
00
01
10
11
Table 2 Register Map
DAC LSW holding
DAC MSW holding
Reserved
Control
DAC 7 DAC 6 DAC 5 DAC 4 DAC 3 DAC2 DAC 1 DAC 0
X X X X DAC 11 DAC 10 DAC 9 DAC 8
00000000
X X X REF1 REF0 RLDAC PWR SPD
PROGRAMMABLE SETTLING TIME
Settling time is a software selectable 3.5µs or 1µs, typical to within ±0.5LSB of final value. This is
controlled by the value of SPD – Bit D12. A ONE defines a s ettling time of 1µs, a ZERO def ines a
settling time of 3.5µs.
PIN BIT
SPD SPD
00Slow
01Fast
10Fast
11Fast
Table 3 Programmable Settling Time
MODE
PROGRAMMABLE POWER DOWN
The power down function can be controlled by PWR. A ZERO configures t he devi ce as active, or full y
powered up, a ONE configures the device into power down mode. W hen t he power down function is
released the device reverts to t he DAC code set prior to power down.
PIN BIT
NPD PWD
00Down
01Down
10Normal
11Down
Table 4 Programmable Power Down
POWER
LOAD DAC LATCH
Bit RLDAC controls the function of the DAC latc h. A ONE c onfigures the DA C lat ch as trans parent. A
ZERO configures the DAC latch to be controlled by pin NLDAC.
PIN BIT
NLDAC RLDAC
0 0 Transparent
0 1 Transparent
10Hold
1 1 Transparent
Table 5 Load DAC Latch
LATCH
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Production Data WM2633
PROGRAMMABLE INTERNAL REFERENCE
The reference can be sourced internally or externally under software control. If an external reference
voltage is applied to the REF pin, the device must be confi gured to accept this.
If an external reference is selec ted, the reference voltage input is buffered which m akes the DAC
input resistance independent of code. The REF pin has an input res istance of 10MΩ and an input
capacitance of typical l y 55pF. The reference voltage determines t he DAC full-scale output.
If an internal reference is selected, a voltage of 1.024V or 2.048 is available. The internal reference
can source up to 1mA and c an therefore be used as an external system ref erence.
REF1 REF0 REFERENCCE
0 0 External (default)
0 1 1.024V
1 0 2.048V
1 1 External
Table 6 Programmable Internal Reference
WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 1999
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WM2633 Production Data
PACKAGE DIMENSIONS
DT: 20 PIN TSSOP (6.5 x 4.4 x 1.0 mm)
b
A2
A1
A
e
1120
D
101
0.05
E1 E
C
-C-
SEATING PLANE
GAUGE
PLANE
DM008.C
θ
0.25
c
L
Dimensions
Symbols
(mm)
MIN NOM MAX
A
A
1
A
2
b
c
D
e
E
E
1
L
θ
REF:
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM.
D. MEETS JEDEC.95 MO-153, VARIATION = AC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
----- ----- 1.20
0.05 ----- 0.15
0.80 1.00 1.05
0.19 ----- 0.30
0.09 ----- 0.20
6.40 6.50 6.60
0.65 BSC
6.4 BSC
4.30 4.40 4.50
0.45 0.60 0.75
o
0
----- 8
o
JEDEC.95, MO-153
WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 1999
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