Datasheet WM2616ID, WM2616CD Datasheet (Wolfson)

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Page 1

WM2616

DNL - LSB

12-bit Serial Input Voltage Output DAC

Production Data June 1999, Rev1.0

FEATURES

• 12-bit voltage output DAC

• Single supply from 2.7V to 5.5V

• DNL ±±0.5 LSB, INL ±±1.9 LSB

• Very low power consumption (3V supply):

- 900µµW, slow mode

- 2.1mW, fast mode

• TMS320, (Q)SPI, and Microwire compatible serial

interface

• Programmable settling time of 4µµs or 12µµs typical

• High impedance reference input buffer

APPLICATIONS

• Battery powered test instruments

• Digital offset and gain adjustment

• Battery operated/remote industrial controls

• Machine and motion control devices

• Wireless telephone and communication systems

• Speech synthesis

• Arbitrary waveform generation

ORDERING INFORMATION

DEVICE TEMP. RANGE PACKAGE

WM2616CD 0° to 70°C 8-pin SOIC

WM2616ID -40° to 85°C 8-pin SOIC

DESCRIPTION

The WM2616 is a 12-bit voltage output, resistor string digital-toanalogue converter that can be powered down under software control. Power down reduces current consumption to 10nA.

The device has been designed to interface efficiently to industry standard microprocessors and DSPs, including the TMS320 family. The WM2616 is programmed with a 16-bit serial word comprising 4 control bits and 12 data bits.

Excellent performance is delivered with a typical DNL of 0.5LSBs. The settling time of the DAC is programmable to allow the designer to optimize speed versus power dissipation. The output stage is buffered by a x2 gain rail-to-rail amplifier, which features a Class AB output stage.

The device is available in an 8-pin SOIC package. Commercial temperature (0° to 70°C) and Industrial temperature (-40° to 85°C) variants are supported.

BLOCK DIAGRAM TYPICAL PERFORMANCE

VDD

(8)

AVDD = DVDD = 5V, V

0.8

0.6

0.4

0.2

-0.2

-0.4

-0.6

-0.8

-1 0 512 1024 1536 2048 2559 3071 3583 4095

= 2.048V, Speed = Fast mode, Load = 10k/100pF

REF

DIGITAL CODE

REFIN(6)

DIN (1)

SCLK (2)

NCS (3)

FS (4)

16-BIT SHIFT

AND

CONTROL

LOGIC

POWER-ON

RESET

(5)

AGND

REFERENCE

INPUT BUFFER

12-BIT

data

DAC

LATCH

2-BIT

CONTROL

LATCH

POWERDOWN/

SPEED

CONTROL

DAC OUTPUT BUFFER

WM2616

(7) OUT

WOLFSON MICROELECTRONICS LTD

Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: [email protected] http://www.wolfson.co.uk

Production Data Datasheets contain final

specifications current on publication date.

Supply of products conforms to Wolfson

Microelectronics’ Terms and conditions.

2616 master.doc June 17, 1999 14:13

1999 Wolfson Microelectronics Ltd.

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WM2616 Production Data Rev 1.0 PIN CONFIGURATION

DIN

SCLK

NCS

1 2 3 4

VDD

OUT

REFIN

AGND

PIN DESCRIPTION

PIN NO NAME TYPE DESCRIPTION

1 2 3 4 5 6 7 8

DIN Digital input Serial data input.

SCLK Digital input Serial clock input.

NCS Digital input Chip select. This pin is active low.

FS Digital input Frame synchronisation for serial input data. AGND Supply Analogue ground. REFIN Analogue input Voltage reference input.

OUT Analogue output DAC analogue output VDD Supply Positive power supply.

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified

ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device.

CONDITION MIN MAX

Supply voltage, VDD to AGND Digital input voltage Reference input voltage Operating temperature range, T

Storage temperature Lead temperature 1.6mm (1/16 inch) soldering for 10 seconds

WM2616CD WM2616ID

-0.3V VDD + 0.3V

-0.3V VDD + 0.3V 0°C

-40°C

-65°C 150°C

70°C 85°C

260°C

RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Supply voltage High-level digital input voltage

Low-level digital input voltage Reference voltage to REFIN Load resistance Load capacitance

Serial clock rate Operating free-air temperature

Note: Reference input voltages greater then VDD/2 will cause saturation for large DAC codes.

WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999

VDD 2.7 5.5 V

V V

REF

R C

SCLK

VDD = 2.7V to 5.5V 2 V VDD = 2.7V to 5.5V 0.8 V

See Note

2 10 kΩ

WM2616CD 0 70 °C

WM2616ID -40 85 °C

VDD - 1.5 V

100 pF

20 MHz

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Production Data Rev 1.0 WM2616

ELECTRICAL CHARACTERISTICS

Test Conditions:

RL = 10kΩ, CL = 100pF. VDD = 5V ±± 10%, V temperature range (unless noted otherwise).

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Static DAC Specifications

Resolution Integral non-linearity Differential non-linearity Zero code error Gain error D.c. power supply rejection ratio Zero code error temperature coefficient Gain error temperature coefficient

DAC Output Specifications

Output voltage range Output load regulation

Power Supplies

Active supply current

Power down supply current

Dynamic DAC Specifications

Slew rate

Settling time

Glitch energy Signal to noise ratio

Signal to noise and distortion ratio

Total harmonic distortion

Spurious free dynamic range

= 2.048V and VDD = 3V ±± 10%, V

REF

= 1.024V over recommended operating free-air

REF

12 bits

INL See Note 1

DNL See Note 2

±±1.9 ±±4 ±±0.5 ±±1

ZCE See Note 3 2

GE See Note 4 0.1

±±10

±±0.6

LSB LSB

% FSR

d.c. PSRR See Note 5 0.5 mV/V

See Note 6 10 ppm/°C See Note 6 10 ppm/°C

0 VDD - 0.1 V

2kΩ to 10kΩ load

0.1 0.25 %

See Note 7

No load, V

VDD = 5V,

= 2.048V Slow

REF

VDD = 5V,

= 2.048V Fast

REF

VDD = 3V,

= 1.024V Slow

REF

VDD = 3V,

= 1.024V Fast

REF

= VDD, V

= 0V

0.4 0.6 mA

0.9 1.35 mA

0.3 0.45 mA

0.7 1.1 mA

See Note 8

No load,

0.01 10 µA

all digital inputs 0V or VDD

See Note 9

DAC code 128 to 4095,

10%-90%

Slow

Fast

0.5

2.5

0.9

3.6

V/µs V/µs

See Note 10

DAC code 128 to 4095

Slow

Fast

12.0

4.0

µs µs

See Note 11

Code 2047 to 2048 10 nV-s

SNR fs = 400ksps, f

= 1kHz,

OUT

66 74 dB

BW = 20kHz

See Note 12

SNRD fs = 400ksps, f

= 1kHz,

OUT

54 66 dB

BW = 20kHz

See Note 12

THD fs = 400ksps, f

= 1kHz,

OUT

-68 -56 dB

BW = 20kHz

See Note 12

SPFDR fs = 400ksps, f

= 1kHz,

OUT

56 70 dB

BW = 20kHz

See Note 12

WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999

Page 4

WM2616 Production Data Rev 1.0

Test Conditions:

RL = 10kΩ, CL = 100pF. VDD = 5V ±± 10%, V temperature range (unless noted otherwise).

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Reference

Reference input resistance Reference input capacitance Reference feedthrough

Reference input bandwidth

Digital Inputs

High level input current Low level input current Input capacitance

Notes:

1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects of zero code and full scale errors).

2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in digital input code.

3. Zero code error is the voltage output when the DAC input code is zero.

4. Gain error is the deviation from the ideal full scale output excluding the effects of zero code error.

5. Power supply rejection ratio is measured by varying VDD from 4.5V to 5.5V and measuring the proportion of this signal imposed on the zero code error and the gain error.

6. Zero code error and Gain error temperature coefficients are normalised to full scale voltage.

7. Output load regulation is the difference between the output voltage at full scale with a 10kΩ load and 2kΩ load. It is expressed as a percentage of the full scale output voltage with a 10kΩ load.

8. IDD is measured while continuously writing code 2048 to the DAC. For VIH < VDD - 0.7V and VIL > 0.7V supply current will increase.

9. Typical supply current in power down mode is 10nA. Production test limits are wider for speed of test.

10. Slew rate results are for the lower value of the rising and falling edge slew rates

11. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling edges. Limits are ensured by design and characterisation, but are not production tested.

12. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency f

= 2.048V and VDD = 3V ±± 10%, V

REF

REFIN

= 1VPP at 1kHz

REF

+ 1.024V dc, DAC code 0

= 0.2VPP + 1.024V dc

REF

DAC code 2048

Slow

Fast

Input voltage = VDD 1 µA

Input voltage = 0V -1 µA

= 1.024V over recommended operating free-air

REF

10 MΩ

5 pF

-75 dB

0.5

1.3

3 pF

generated with a sampling frequency fs

OUT

MHz MHz

WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999

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Production Data Rev 1.0 WM2616

SERIAL INTERFACE

SCLK

DIN

1 2 3 4 5 15 16

SUDtHD

SUCSFS

D0D1D12D13D14D15

SUC16CS

NCS

WHFS

SUFS

SUC16FS

Figure 1 Timing Diagram

Test Conditions:

RL = 10kΩ, CL = 100pF. VDD = 5V ±± 10%, V

= 2.048V and VDD = 3V ±± 10%, V

REF

= 1.024V over recommended operating free-air

REF

temperature range (unless noted otherwise).

SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

SUCSFS

SUFS

SUC16FS

Setup time NCS low before negative FS edge. Setup time FS low before first negative SCLK edge. Setup time, sixteenth negative SCLK edge after FS low

on which D0 is sampled before rising edge of FS.

10 ns

8 ns

10 ns

Setup time, sixteenth positive SCLK edge (first positive after D0 sampled) before NCS rising edge. If FS is used

SUC16CS

instead of the sixteenth positive edge to update the DAC,

10 ns then the setup time is between the FS rising edge and the NCS rising edge.

t t

WHFS

SUD

Pulse duration, SCLK high. Pulse duration, SCLK low. Setup time, data ready before SCLK falling edge. Hold time, data held valid after SCLK falling edge. Pulse duration, FS high.

25 ns

8 ns 5 ns

20 ns

WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999

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WM2616 Production Data Rev 1.0

INL - LSB

OUTPUT VOLTAGE - V

TYPICAL PERFORMANCE GRAPHS

AVDD = DVDD = 5V, VREF = 2.048V, Speed = Fast mode, Load = 10k/100pF

-1

-2

-3 0 512 1024 1536 2048 2559 3071 3583 4095

Figure 2 Integral Non-Linearity

DIGITAL CODE

0.4

VDD = 3V, V

0.35

0.3

0.25

0.2

0.15

0.1

0.05

0 1 2 3 4 5 6 7 8 9 10

= 1V, Input Code = 0

REF

ISINK - mA

Slow Fast

0.4

VDD = 5V, V

0.35

0.3

0.25

0.2

0.15

0.1

0.05

0 1 2 3 4 5 6 7 8 9 10

= 2V, Input Code = 0

REF

ISINK - mA

Figure 3 Sink Current VDD = 3V Figure 4 Sink Current VDD = 5V

2.06

2.055

2.05

2.045

2.04

VDD = 3V, V

= 1V, Input Code = 4095

REF

4.095

4.09

4.085

4.08

4.1

VDD = 5V, V

= 2V, Input Code = 4095

REF

Slow Fast

2.035

2.03

2.025 0 1 2 3 4 5 6 7 8 9 10

ISOURCE - mA

Slow Fast

4.075

4.07

4.065 0 1 2 3 4 5 6 7 8 9 10

ISOURCE - mA

Slow Fast

Figure 5 Source Current VDD = 3V Figure 6 Source Current VDD = 5V

WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999

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Production Data Rev 1.0 WM2616

DEVICE DESCRIPTION

GENERAL FUNCTION

The device uses a resistor string network buffered with an op amp to convert 12-bit digital data to analogue voltage levels (see Block Diagram). The output voltage is determined by the reference input voltage and the input code according to the following relationship:

Output voltage =

INPUT OUTPUT

1111 1111 1111

: :

1000 0000 0001

1000 0000 0000

0111 1111 1111

: :

0000 0000 0001

0000 0000 0000 0V

Table 1 Binary Code Table (0V to 2V

CODE

( )

V2 REFIN

4096

( )

REF

( )

V2 REF

2048

( )

V2 =

4096

( )

REF

( )

V2 REF

Output), Gain = 2

REFIN

4095 4096

2049 4096

REFREF V

2047 4096

4096

POWER ON RESET

An internal power-on-reset circuit resets the DAC register to all 0s on power-up.

BUFFER AMPLIFIER

The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a 2kΩ load with a 100pF load capacitance.

EXTERNAL REFERENCE

The reference voltage input is buffered which makes the DAC input resistance independent of code. The REFIN pin has an input resistance of 10MΩ and an input capacitance of typically 5pF. The reference voltage determines the DAC full-scale output.

SERIAL INTERFACE

Explanation of data transfer: First, the device has to be enabled with NCS set to low. Then, a falling edge of FS starts shifting the

data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred, the next rising edge on SCLK or FS causes the content of the shift register to be moved to the DAC latch which updates the voltage output to the new level.

The serial interface of the device can be used in two basic modes:

• four wire (with chip select)

• three wire (without chip select)

Using chip select (four wire mode), it is possible to have more than one device connected to the serial port of the data source (DSP or microcontroller). If there is no need to have more than one device on the serial bus, then NCS can be tied low.

SERIAL CLOCK AND UPDATE RATE

Figure 1 shows the device timing. The maximum serial rate is: f

max = MHz20

SCLK

The digital update rate is limited to an 800ns period, or 1.25MHz frequency. However, the DAC settling time to 12 bits limits the update rate for large input step transitions.

WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999

minWCLminWCH

Page 8

WM2616 Production Data Rev 1.0

SOFTWARE CONFIGURATION OPTIONS

The 16 bits of data can be transferred with the sequence shown in Table 2. D11-D0 contains the 12-bit data word. D14-D13 hold the programmable options.

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

x SPD PWR x New DAC value (12 bits)

Table 2 Register Map

PROGRAMMABLE SETTLING TIME

Settling time is a software selectable 12µs or 4µs typical, to within ±0.5LSB of final value. This is controlled by the value of D14. A ONE defines a settling time of 4µs, a ZERO defines a settling time of 12µs.

PROGRAMMABLE POWER DOWN

The power down function is controlled by D13. A ZERO configures the device as active, or fully powered up, a ONE configures the device into power down mode. When the power down function is released the device reverts to the DAC code set prior to power down.

WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999

Page 9

Production Data Rev 1.0 WM2616

PACKAGE DIMENSIONS

D: 8 PIN SOIC 3.9mm Wide Body

E H

-C-

h x 45

DM009.B

Symbols

0.10 (0.004)

Dimensions

(mm)

SEATING PLANE

Dimensions

(Inches)

MIN MAX MIN MAX A A

B C D e E h H L

αα

REF:

NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES). B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN). D. MEETS JEDEC.95 MS-012, VARIATION = AA. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.

1.35 1.75 0.0532 0.0688

0.10 0.25 0.0040 0.0098

0.33 0.51 0.0130 0.0200

0.19 0.25 0.0075 0.0098

4.80 5.00 0.1890 0.1968

1.27 BSC 0.050 BSC

3.80 4.00 0.1497 0.1574

0.25 0.50 0.0099 0.0196

5.80 6.20 0.2284 0.2440

0.40 1.27 0.0160 0.0500

JEDEC.95, MS-012

WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999