Datasheet WM2613IDT, WM2613CDT Datasheet (Wolfson)

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Page 1

WM2613

DNL - LSB

Byte-wide Parallel Input, 12-bit Voltage Output DAC

Production Data, June 1999, Rev 1.0

FEATURES

• Dual 12-bit voltage output DAC

• Dual supply 2.7V to 5.5V operation

• DNL ±±0.4 LSB, INL ±±1.5 LSB

• Programmable settling time 1µµs or 3µµs typical

• 8-bit micro controller compatible interface

• Power down mode (10nA)

APPLICATIONS

• Battery powered test instruments

• Digital offset and gain adjustment

• Battery operated/remote industrial controls

• Machine and motion control devices

• Wireless telephone and communication systems

• Speech synthesis

• Arbitrary waveform generation

ORDERING INFORMATION

DEVICE TEMP. RANGE PACKAGE

WM2613CDT 0° to 70°C 20-pin TSSOP

WM2613IDT -40° to 85°C 20-pin TSSOP

DESCRIPTION

The WM2613 is a 12-bit voltage output, resistor string, digital-toanalogue converter. The DAC can be powered down under software or hardware control, reducing power consumption to 10nA.

The device has an 8-bit microcontroller compatible parallel interface. The eight data LSBs, the four data MSBs, and the three control bits are written using three different addresses.

Excellent performance is delivered with a typical DNL of 0.4 LSBs. The output stage is buffered by a x2 gain near rail-to-rail amplifier, which features a Class A output stage (slow mode, class AB). The settling time of the DAC is software programmable to allow the designer to optimize speed versus power dissipation.

The device is available in a 20-pin TSSOP package. Commercial temperature (0° to 70°C) and Industrial temperature (-40° to 85°C) variants are supported.

BLOCK DIAGRAM TYPICAL PERFORMANCE

DVDD

AVDD

(10)

WM2613

(11)

DAC OUTPUT BUFFER

REFIN(12)

SPD (9)

NPD (15)

A[0-1] (8,7)

NCS (18)

NWE (17)

D[0-7]

(19,20, 1-6)

PARALLEL

INTERFACE

AND

CONTROL

LOGIC

POWER-ON

RESET

POWERDOWN/

CONTROL

(14)

GND

SPEED

3-BIT

CONTROL

LATCH

4-BIT DAC

MSW

HOLDING

LATCH

8-BIT DAC

LSW

HOLDING

LATCH

NLDAC

REFERENCE

INPUT BUFFER

12-BIT DAC

LATCH

(16)

WOLFSON MICROELECTRONICS LTD

Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: [email protected] http://www.wolfson.co.uk

(13) OUT

AVDD = DVDD = 5V, V

0.8

0.6

0.4

0.2

-0.2

-0.4

-0.6

-0.8

-1 0 512 1024 1536 2048 2559 3071 3583 4095

= 2.048V, Speed = Fast mode, Load = 10k/100pF

REF

DIGITAL CODE

Production Data Datasheets contain final

specifications current on publication date.

Supply of products conforms to Wolfson

Microelectronics’ Terms and conditions.

Master rev 1.0.doc June 17, 1999 14:12

1999 Wolfson Microelectronics Ltd.

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WM2613 Production Data Rev 1.0 PIN CONFIGURATION

D2 D3 D4 D5 D6

D7 A1 A0

SPD

DVDD

1 2 3 4 5 6 7

9 10

20 19 18 17 16 15 14 13

12 11

D1 D0

NCS NWE NLDAC NPD GND OUT8 REFIN

AVDD

PIN DESCRIPTION

PIN NO NAME TYPE DESCRIPTION

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15

17 18 19 20

D2 Digital input Data input. D3 Digital input Data input. D4 Digital input Data input. D5 Digital input Data input. D6 Digital input Data input. D7 Digital input Data input. A1 Digital input Address input. A0 Digital input Address input.

SPD Digital input Speed select. Digital input. DVDD Supply Digital positive power supply. AVDD Supply Analogue positive power supply.

REFIN Analogue input Voltage reference input.

OUT Analogue output DAC analogue voltage output.

GND Supply Ground. NPD Digital input Power down. Active low digital input which powers down all analogue

circuits.

NLDAC Digital input Load DAC. Digital input active low. NLDAC must be taken low to update

the DAC latch from the holding latches.

NWE Digital input Write enable. Digital input active low.

NCS Digital input Chip select. Digital input active low.

D0 Digital input Data input. D1 Digital input Data input.

WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999

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Production Data WM2613

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified

ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device.

CONDITION MIN MAX

Supply voltages, AVDD or DVDD to GND Supply voltage differences, AVDD to DVDD Reference input voltage Digital input voltage range to GND Operating temperature range, T

WM2613C WM2613I

Storage temperature Lead temperature 1.6mm (1/16 inch) soldering for 10 seconds

-2.8V 2.8V

-0.3V DVDD + 0.3V

-0.3V AVDD + 0.3V 0°C

-40°C

-65°C 150°C

70°C 85°C

260°C

RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Supply voltage High-level digital input voltage Low-level digital input voltage Reference voltage to REFIN

Load resistance Load capacitance Operating free-air temperature

AVDD, DVDD 2.7 5.5 V

REF

DVDD = 2.7V to 5.5V 2 V DVDD = 2.7V to 5.5V 0.8 V

See Note AVDD - 1.5 V

WM2613CDT 0 70 °C

WM2613IDT -40 85 °C

Note: Reference voltages greater than AVDD/2 will cause saturation for large DAC codes.

2 kΩ

100 pF

WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999

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WM2613 Production Data Rev 1.0 ELECTRICAL CHARACTERISTICS

Test Conditions:

RL = 10kΩ, CL = 100pF. AVDD = DVDD = 5V ±± 10%, V recommended operating free-air temperature range (unless noted otherwise)

= 2.048V and AVDD = DVDD = 3V ±± 10%, V

REF

= 1.024V over

REF

PARAMETER SYMBOL Static DAC Specifications

Resolution Integral non-linearity Differential non-linearity Zero code error Gain error D.c power supply rejection ratio

INL See Note 1 DNL See Note 2 ZCE See Note 3 3

GE See Note 4

d.c. PSRR See Note 5 0.5 mV/V

Zero code error temperature coefficient

Gain error temperature coefficient

DAC Output Specifications

Output voltage range Output load regulation

Power Supplies

Active supply current

IDD No load, VIH = DVDD, VIL = 0V

Power down supply current

Dynamic DAC Specifications

Slew rate

Settling time

Glitch energy Signal to noise ratio

Signal to noise and distortion ratio

Total harmonic distortion

Spurious free dynamic range

SNR fS = 480ksps,

SNRD fS = 480ksps,

THD fS = 480ksps,

SPFDR fS = 480ksps,

TEST

CONDITIONS

MIN TYP MAX UNIT

12 bits

±±1.5 ±±4 ±±0.4 ±±1

LSB LSB

±±20

±±0.25 ±±0.5

See Note 6 3 ppm/°C

See Note 6 1 ppm/°C

0 AVDD - 0.4 V

2kΩ to 10kΩ load. See Note 7 0.1 0.3 %

AVDD = DVDD = 5V,

= 2.048V See Note 8

REF

Slow

Fast

AVDD = DVDD = 3V,

= 1.024V

REF

Slow

Fast

No load, all digital inputs 0V

or DVDD. See Note 9

DAC code 128 to 4095,

10%-90% See Note 10

Slow

Fast

DAC code 128 to 4095

Slow

Fast

Code 2047 to code 2048 1 nV-s

65 78 dB

= 1kHz BW = 20kHz,

OUT

TA = 25°C See Note 12

58 69 dB

= 1kHz BW = 20kHz,

OUT

TA = 25°C See Note 12

= 1kHz BW = 20kHz,

OUT

TA = 25°C See Note 12

60 72 dB

= 1kHz BW = 20kHz, TA =

OUT

25°C See Note 12

0.5

1.6

0.4

1.4

1.3

3.0

1.1

2.7

0.01 10 µA

1.5 8

3.5

1.0

-68 -60 dB

% FSR

V/µs V/µs

mA mA

µs µs

WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999

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Production Data WM2613

Test Conditions: RL = 10kΩ, CL = 100pF. AVDD = DVDD = 5V ±± 10%, V

= 2.048V and AVDD = DVDD = 3V ±± 10%, V

REF

= 1.024V over

REF

recommended operating free-air temperature range (unless noted otherwise)

PARAMETER SYMBOL

TEST

CONDITIONS

MIN TYP MAX UNIT

Reference

Reference input resistance Reference input capacitance Reference feedthrough

RREFIN 10 MΩ CREFIN 5 pF

VREF = 1VPP at 1kHz

-60 dB

+ 1.024V d.c., DAC code 0

Reference input bandwidth

VREF = 0.2VPP + 1.024V d.c.

DAC code 2048

Slow

Fast

1.6

Digital Inputs

High level input current Low level input current Input capacitance

Input voltage = DVDD 1 µA

Input voltage = 0V -1 µA

8 pF

Notes:

1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full scale errors).

2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in digital input code.

3. Zero code error is the voltage output when the DAC input code is zero.

4. Gain error is the deviation from the ideal full scale output excluding the effects of zero code error.

5. Power supply rejection ratio is measured by varying AVDD from 4.5V to 5.5V and measuring the proportion of this signal imposed on the zero code error and the gain error.

6. Zero code error and Gain error temperature coefficients are normalised to full scale voltage.

7. Output load regulation is the difference between the output voltage at full scale with a 10kΩ load and 2kΩ load. It is expressed as a percentage of the full scale output voltage with a 10kΩ load.

8. IDD is measured while continuously writing code 2048 to the DAC. For VIH < DVDD - 0.7V and VIL > 0.7V supply current will increase.

9. Typical supply current in power down mode is 10nA. Production test limits are wider for speed of test.

10. Slew rate results are for the lower value of the rising and falling edge slew rates.

11. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling edges. Limits are ensured by design and characterisation, but are not production tested

12. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency f

generated with

OUT

a sampling frequency fS.

MHz MHz

WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999

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WM2613 Production Data Rev 1.0 SERIAL INTERFACE

D[0-7]

A[0-1]

SUCSWE

SUD

DataX X

SUA

AddressX X

NCS

WWE

NWE

SUWELD

WLD

NLDAC

Figure 1 Timing Diagram

SYMBOL TEST CONDITIONS MIN TYP MAX

SUCSWE

SUDWE

SUWELD

SUA

WWE

WLD

Setup time NCS low before positive NWE edge Data ready before positive NWE edge Data hold after positive NWE edge Setup time for address bits A0, A1 Address hold after positive NWE edge Positive NWE edge before NLDAC low High pulse width of NWE Low pulse width of NLDAC

13 ns 9 ns 0 ns

17 ns

0 0 ns

10 ns 10 ns

UNIT

WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999

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Production Data WM2613

INL - LSB

OUTPUT VOLTAGE - V

TYPICAL PERFORMANCE GRAPHS

AVDD = DVDD = 5V, V

-1

-2

-3 0 512 1024 1536 2048 2559 3071 3583 4095

Figure 2 Integral Non-Linearity

= 2.048V, Speed = Fast mode, Load = 10k/100pF

REF

DIGITAL CODE

AVDD = DVDD =3V, V

2.5

1.5

0.5

0 1 2 3 4 5 6 7 8 9 10

= 1V, Input Code = 0

REF

ISINK - mA

Slow Fast

AVDD = DVDD = 5V, V

4.5

3.5

2.5

1.5

0.5

0 1 2 3 4 5 6 7 8 9 10

= 2V, Input Code = 0

REF

ISINK - mA

Figure 3 Sink Current AVDD = DVDD = 3V Figure 4 Sink Current AVDD = DVDD = 5V

2.065

AVDD = DVDD = 3V, V

2.06

2.055

2.05

2.045

2.04

2.035

2.03

2.025 0 1 2 3 4 5 6 7 8 9 10

= 1V, Input Code = 4095

REF

ISOURCE - mA

Slow Fast

4.105

AVDD = DVDD = 5V, V

4.1

4.095

4.09

4.085

4.08

4.075

4.07

4.065 0 1 2 3 4 5 6 7 8 9 10

= 2V, Input Code = 4095

REF

ISOURCE - mA

Slow Fast

Figure 5 Source Current AVDD = DVDD = 3V Figure 6 Source Current AVDD = DVDD = 5V

WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999

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WM2613 Production Data Rev 1.0 DEVICE DESCRIPTION

GENERAL FUNCTION

The device uses a resistor string network buffered with an op amp to convert 12-bit digital data to analogue voltage levels (see Block Diagram). The output voltage is determined by the reference input voltage and the input code according to the following relationship:

Output voltage =

INPUT OUTPUT

1111 1111 1111

: :

1000 0000 0001

1000 0000 0000

0111 1111 1111

: :

0000 0000 0001

0000 0000 0000 0V

Table 1 Binary Code Table (0V to 2V

( )

REF

CODE

4096

( )

Output), Gain = 2

REF

( )

V2 REF

( )

V2 REF

2048 4096

( )

V2 REF

( )

V2 REF

4095 4096

2049 4096

2047 4096

4096

REfREF

POWER ON RESET

An internal power-on-reset circuit resets the DAC register to all 0s on power-up.

BUFFER AMPLIFIER

The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a 2kΩ load with a 100pF load capacitance.

EXTERNAL REFERENCE

The reference voltage input is buffered which makes the DAC input resistance independent of code. The REFIN pin has an input resistance of 10MΩ and an input capacitance of typically 5pF. The reference voltage determines the DAC full-scale output.

HARDWARE CONFIGURATION OPTIONS

The device has three configuration options that are controlled by device pins.

DEVICE POWER DOWN

The device can be powered-down by pulling pin NPD (pin 15) low. This powers down the DAC. This will reduce power consumption significantly. The NPD pin overrides the software control bit PWR. When the power down function is released the device reverts to the DAC code set prior to power down.

SETTLING TIME

The settling time of the device can be controlled by pin SPD (pin 9). A ONE on pin SPD will ensure a FAST settling time; a ZERO will ensure a SLOW settling time. The SPD pin high overrides the software control bit SPD.

SIMULTANEOUS DAC UPDATE

The NLDAC pin (Pin 16) can be held high to prevent word writes from updating the DAC latch. By writing the new value to the DAC then pulling NLDAC low, the new DAC code is loaded into the DAC latch.

WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999

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Production Data WM2613

PARALLEL INTERFACE

The device latches data on the positive edge of NWE. It must be enabled with NCS low. Whether the data is written to one of the DAC holding latches (MSW, LSW) or the control register, depends on the address bits A1 and A0. NLDAC low updates the DAC with the value in the holding latch, see Figure 7. NLDAC is an asynchronous input and can be held low, if a synchronous update is not necessary. Alternatively, the RLDAC bit of the control register can be used to synchonously update the DAC latch via software control, see Figure 8.

D[0-7]

A[0-1]

NCS

NWE

NLDAC

Figure 7 Example of a Complete Write Cycle Using NLDAC to Update the DAC

D[0-7]

X MSW LSWX X

0 1X X

X MSW LSWX

ControlX X

A[0-1]

NWE

NLDAC

Figure 8 Example of a Complete Write Cycle Using the Control Word to Update the DAC. If NLDAC is held low as shown

in Figure 8, latch will be transparent. This assumes that the RLDAC control register bit is low at the start and is written high on the final write.

WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999

X 3X X

NCS

0 1X

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WM2613 Production Data Rev 1.0

SOFTWARE CONFIGURATION OPTIONS

DATA FORMAT

The WM2613 writes data either to one of the DAC holding latches or to the control register depending on the address bits A1 and A0.

A1 A0 REGISTER

0 0 0 1 1 0 1 1

D7 D6 D5 D4 D3 D2 D1 D0

X X X X X RLDAC PWR SPD

Table 2 Register Map

PROGRAMMABLE SETTLING TIME

Settling time is a software selectable 3.5µs or 1µs, typical to within ±0.5LSB of final value. This is controlled by the value of SPD – Bit D12. A ONE defines a settling time of 1µs, a ZERO defines a settling time of 3.5µs.

DAC LSW holding DAC MSW holding Reserved Control

PIN BIT

SPD SPD

0 0 Slow 0 1 Fast 1 0 Fast 1 1 Fast

Table 3 Programmable Settling Time

MODE

PROGRAMMABLE POWER DOWN

The power down function can be controlled by PWR. A ZERO configures the device as active, or fully powered up, a ONE configures the device into power down mode. When the power down function is released the device reverts to the DAC code set prior to power down.

PIN BIT

NPD PWR

0 0 Down 0 1 Down 1 0 Normal 1 1 Down

Table 4 Programmable Power Down

POWER

LOAD DAC LATCH

Bit RLDAC controls the function of the DAC latch. A ONE configures the DAC latch as transparent. A ZERO configures the DAC latch to be controlled by pin NLDAC.

PIN BIT

NLDAC RLDAC

0 0 Transparent 0 1 Transparent 1 0 Hold 1 1 Transparent

Table 5 Load DAC Latch

LATCH

WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999

Page 11

Production Data WM2613

PACKAGE DIMENSIONS

DT: 20 PIN TSSOP (6.5 x 4.4 x 1.0 mm)

1120

101

0.05 C

E1 E

-C-

SEATING PLANE

GAUGE PLANE

DM008.C

θθ

0.25

Dimensions

Symbols

(mm)

MIN NOM MAX A A

b c D e E E

θθ

REF:

NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MO-153, VARIATION = AC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.

----- ----- 1.20

0.05 ----- 0.15

0.80 1.00 1.05

0.19 ----- 0.30

0.09 ----- 0.20

6.40 6.50 6.60

0.65 BSC

6.4 BSC

4.30 4.40 4.50

0.45 0.60 0.75

----- 8

JEDEC.95, MO-153

WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999