WM0831 and WM0832 are 8-bit analogue to digital
converters (ADC) with serial I/O interfaces, providing a
choice of input configurations in 8-pin SO or DIP packages.
WM0831 has a differential input, also configurable as a
single ended input. A-D conversion results are serially
output on Data Out (DO) under the control of clock and chip
select inputs. The device has a separate voltage reference
input.
WM0832's two input multiplexer is configurable via the Data
In (DI) serial input, as two single ended inputs or a single
differential input. The voltage reference operates
ratiometrically and is internally connected to the VCC pin.
Conversion is initiated by bringing and holding chip select
low while providing a clock input. With WM0831's fixed
input configuration, the conversion result is output at DO on
the clock's falling edges in MSB to LSB order.
With WM0832's configurable input multiplexer, data is input
to DI on the rising edges of the clock to setup the Mux and
initiate conversion. Conversion results appear serially at
DO on the falling edges of the clock, first in MSB to LSB
order, and then repeated in LSB to MSB order.
WM0831/2 operate on 5V or 3.3V supply voltages and are
available in small outline and DIP packages for commercial
o
C) and industrial (-40 to 85oC) temperature ranges.
(0 to 70
Block Diagrams
WM0831
Features
•Functionally Equivalent to National Semiconductor ADC0831 and ADC0832
•WM0831: Differential or single ended input
•WM0832: Two single ended inputs or a single
differential input
•Ratiometric reference input (fixed for WM0832)
•Serial I/O interface
•Input range 0 to Vcc with Vcc Reference
•8 pin package, SO or DIP
•5V and 3.3V variants
•Total Unadjusted Error: ± 1 LSB
•8-bit resolution
µµ
•32
µs conversion time at fclock = 250 kHz
µµ
Applications
•Embedding with remote sensors
•Equipment health monitoring
•Automotive
•Industrial control
WM0832
V
REF
Comparator
IN+
IN-
ND
Production Data data sheets contain final
specifications current on publication date. Supply
of products conforms to Wolfson Microelectronics
standard terms and conditions.
Differential
Input
WM0831
DAC
&
SAR
Logic
Output
Latch
Logic
Control
Wolfson Microelectronics
Lutton Court, Bernard Terrace, Edinburgh EH8 9NX, UK
WM0831CP0oC to 70oC8 pin plastic DIP
WM0831CD0oC to 70oC8 pin plastic SO
WM0831IP-40oC to 85oC8 pin plastic DIP
WM0831ID-40oC to 85oC8 pin plastic SO
WM0832CP0oC to 70oC8 pin plastic DIP
WM0832CD0oC to 70oC8 pin plastic SO
WM0832IP-40oC to 85oC8 pin plastic DIP
o
WM0832ID-40
3.3V devices
DEVICE TEMP . RANGE PACKAGE
WM0831LCP0oC to 70oC8 pin plastic DIP
WM0831LCD0oC to 70oC8 pin plastic SO
WM0831LIP-40oC to 85oC8 pin plastic DIP
WM0831LID-40oC to 85oC8 pin plastic SO
WM0832LCP0oC to 70oC8 pin plastic DIP
WM0832LCD0oC to 70oC8 pin plastic SO
WM0832LIP-40oC to 85oC8 pin plastic DIP
Low level output voltageVOLVCC = 5.25 V, IOH = 1.6 mA0.4V
High level input currentIIHVIH = 5 V0.0051µA
Low level input currentIILVIL = 0 V-0.005-1µA
High level output (source)IOHVOH = 0 V-6.5-24mA
current
Low level output (sink) current IOLVOL = VCC826 mA
High impedance-stateI OZVO = 5 V0.013µA
output current (DO)VO = 0 V-0.01-3µA
Input capacitanceCI5pF
Output capacitanceCo5pF
Converter and Multiplexer
T otal unadjusted errorTUEVREF = 5 V. (note 7)±1LSB
Differential Linearity(note 8)8Bits
Supply voltage variation errorVs(error) VCC = 4.75 V to 5.25 V±1/16±1/4LSB
Common mode errorDifferential mode±1/16±1/4LSB
Common mode input voltageVICR(note 9)GND-0.05V
rangeVCC+0.05
Standby input leakageII(stdby)On-channel VI = 5 V at ON ch.1µA
current (note 10)Off-channel VI = 0 V at OFF ch.-1µA
Input resistance toRi(REF) Can only be tested for WM0831 1.32.45.9kΩ
reference ladder
Total device
Supply current WM0831ICC0.61.25mA
Supply current WM0832ICC( note 11)2.54.7mA
Timing Parameters
Setup time, CS low ortsu350n s
WM0832 data valid before
clock
Hold time, WM0832 datath90ns
valid after clock
Propagation delay time,MSB data first. CL = 100 pF1500ns
output data after clock
Output disable time, DOtdisCL = 10 pF, RL = 10 kΩ125250ns
after CS
OHVCC = 4.75 V, IOH = -360 µA2.4V
VCC = 4.75 V, I OH = -10 µA4.5V
On-channel VI = 0 V at ON ch.-1µA
Off-channel VI = 5 V at OFF ch.1µA
periods
tpdLSB data first. CL = 100 pF600ns
CL = 100 pF, RL = 2 kΩ500ns
Wolfson Microelectronics
3
Page 4
WM0831, WM0832
Recommended Operating Conditions (3.3V)
SYMBOL MINNOMINAL MAXUNIT
Supply voltageVCC2.73.33.6V
High level input voltageVIH2V
Low level input voltageVIL0.8V
Clock frequency (Vcc = 3.3V)fclock10600KHz
Clock duty cycle (see Note 4)Dclk4060%
Pulse duration CS hightwH(CS)220n s
Operating free-air temperatureC suffixTA070
I SuffixT A-4085
o
C
Wolfson Microelectronics
4
Page 5
WM0831, WM0832
Electrical Characteristics (3.3V)
Vcc = 3.3V, fCLK = 250KHz, T A = TMIN to TMAX, tr = tf = 20 ns, unless otherwise stated.
PARAMETER SYMBOL TEST CONDITIONSMINTYPMAXUNIT
Digital Inputs
High level output voltageV
Low level output voltageVOLVCC = 3V, IOH = 1.6 mA0.4V
High level input currentIIHVIH = 3.6 V0.0051µA
Low level input currentIILVIL = 0 V-0.005-1µA
High level output (source)IOHVOH = 0 V, TA = 25oC6.515mA
current
Low level output (sink) current IOLVOL = 0V, TA = 25oC816 mA
High impedance-stateI OZVO = 3.3V, TA = 25oC0.013µA
output current (DO)VO = 0 V, TA = 25oC-0.01-3µA
Input capacitanceCI5pF
Output capacitanceCo5pF
Converter and Multiplexer
T otal unadjusted errorTUEVREF = 3.3 V. (note 7)±1LSB
Differential Linearity(note 8)8Bits
Supply voltage variation errorVs(error) VCC = 3 V to 3.6 V±1/16±1/4LSB
Common mode errorDifferential mode±1/16±1/4LSB
Common mode input voltageVICR(note 9)GND-0.05V
rangeVCC+0.05
Standby input leakageII(stdby)On-channel VI =3.3V at ON ch.1µA
current (note 10)Off-channel VI =0 V at OFF ch.-1µA
Input resistance toRi(REF) Can only be tested for WM0831 1.32.45.9kΩ
reference ladder
Total device
Supply current WM0831ICC0.20.75mA
Supply current WM0832ICC( note 11)1.52.5mA
Timing Parameters
Setup time, CS low ortsu350n s
WM0832 data valid before
clock
Hold time, WM0832 datath90ns
valid after clock
Propagation delay time,MSB data first. CL = 100 pF200500ns
output data after clock
Output disable time, DOtdisCL = 10 pF, RL = 10 kΩ80125ns
after CS
OHVCC = 3V, IOH = -360 µA2.4V
VCC = 3 V, IOH = -10 µA2.8V
On-channel VI =0 V at ON ch.-1µA
Off-channel VI =3.3V at OFF ch.1µA
periods
tpdLSB data first. CL = 100 pF80200ns
CL = 100 pF, RL = 2 kΩ250ns
Wolfson Microelectronics
5
Page 6
WM0831, WM0832
Electrical Characteristics (continued)
Notes:
1. Absolute Maximum Ratings are stress ratings only.
Permanent damage to the device may be caused by
continuously operating at or beyond these limits. Device functional operating range limits are given under
Recommended Operating Conditions. Guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified.
2. All voltage values, except differential voltages are with
respect to the ground.
3. When the input voltage V
power supply rails (GND > V
of current at that pin should be limited to 5 mA or less.
at any pin exceeds the
IN
> VCC) the absolute value
IN
The 20 mA package input current limits the number of
pins that can exceed the power supply boundaries
with a 5 mA supply current to four.
4. A clock duty cycle range of 40% to 60% ensures
correct operation at all clock frequencies. For a clock
with a duty cycle outside these limits, the minimum time
the clock is high or low must be at least 666 ns, with
the maximum time for clock high or low being 60 ms.
5. All typical values are at V
devices and V
= 3.3V, TA = 25oC.
CC
= 5 V, TA = 25oC for 5V
CC
6. All parameters are measured under open-loop
conditions with zero common mode input voltage
(unless otherwise stated).
7. Total Unadjusted Error (TUE) is the sum of integral
linearity error, zero code error and full scale error over
the output code range.
8. A Differential linearity of "n" bits ensures a code width
exists to "n" bits. Hence a Differential Linearity of 8
bits for an 8 bit ADC guarantees no missing codes.
9. For V
(-) greater than or equal to VIN(+) the digital out-
IN
put code will be 00 Hex. Connected to each analogue
input are two diodes which will forward conduct for a
diode drop outside the supply rails, V
analogue input voltage does not exceed the supply volt-
and GND. If an
CC
age by more than 50 mV, the output code will be correct. T o use an absolute input voltage range of 0 to V
a minimum VCC - 0.05 V is required for all variations of
temperature. Care should be exercised when testing at
levels with a maximum analogue voltage as
low V
CC
this can cause the input diode to conduct, especially at
high temperature, and cause errors for analogue inputs
near full scale.
10. Standby input leakage currents, are currents going in
or out of the on or off channels when the ADC is not
performing conversion and the clock input is in a high
or low steady-state condition.
11. For WM0832 the reference current is included in the
supply current as V
is internally connected to VCC.
REF
CC
Wolfson Microelectronics
6
Page 7
Test Circuits and Waveforms
Output Disable Time Voltage Waveforms and Test Circuits
WM0831 has two inputs IN+ and IN- configured for
differential operation, single ended operation is achieved
by grounding IN- to an analogue common or GND.
WM0832 uses an input multiplexer scheme with two input
channels, configurable for single-ended or differential
operation. The single ended input uses the GND pin as its
analogue ground reference.
WM0831/2 uses a successive approximation routine to
perform A/D conversion and employs a sample data
comparator structure which always performs conversion
on a differential voltage. Conversion takes place on the
voltage difference between assigned “+” and “-” inputs and
the converter expects the “+” input to be the most positive,
if the “+” input is more negative than “-” then the converter
gives an all zeros output. Assignment of WM0832 inputs
is made for a single-ended signal between an “+” input
and (analogue) ground (GND), or for a differential input
between CH0 and CH1 inputs of either polarity.
For WM0832 prior to the start of every conversion the input
configuration is assigned during the MUX addressing
sequence by serially shifting data into the Data Input (DI) on
the second and third rising edges of the clock input. The
MUX address selects which analogue inputs are enabled,
either single-ended or differential. For differential inputs the
polarity of the inputs are also assigned. The MUX
addressing table gives full details of input assignments.
Because WM0831 has only one differential input of fixed
polarity it does not require addressing.
WM0831 and WM0832 are controlled from a processor
via a Chip Select (CS) input and a serial interface
comprising Data Out (DO) and additionally for WM0832 a
Data In (DI) input.
For WM0831 conversion is initiated by pulling chip select
low and inputting a clock signal. On the clock's first falling
edge after CS is brought low, DO output comes out of
high impedance mode. On the second and subsequent
clock falling edges, to a total of nine, the conversion
result is output on DO in MSB to LSB order. WM0831 only
provides output data in MSB first order.
For WM0832 conversion is also initiated by pulling the chip
select (CS) line low and inputting a clock signal but MUX
addressing information has also to be input on DI. The
start bit and the MUX assignment bits on DI are clocked
in on the first three rising edges of the clock input which
may be generated by the processor or run continuously.
WM0832 uses two MUX assignment bits.
When the logic “1” start bit is clocked into the start
conversion location of the multiplexer input register the
analogue MUX inputs are selected. After 1/2 a clock
period delay to allow for the selected MUX output to settle
the conversion commences using the successive
approximation technique.
When conversion begins the A/D conversion result from
the output of the SARS comparator appears at the DO
output on each falling edge of the clock (see Functional
Timing Diagrams).
With the successive approximation A/D conversion
routine the analogue input is compared with the output of
a digital to analogue converter (DAC) for each bit by the
SARS comparator and a decision made on whether the
analogue input is higher or lower than the DAC output.
Successive bits, MSB to LSB, are input to the DAC and
remain in its input if the analogue comparison decides
the analogue input is higher than the DAC output, if not
the bit is removed from the DAC input. There is no sample
and hold. The input needs to be stable during T conv period
(see Functional Timing Diagrams).
For WM0832 the 8 bits of the conversion are stored in an
output shift register, after a conversion has completed and
MSB first data has been output WM0832 automatically
shifts out LSB first data on the DO output.
CS must be held low through an entire conversion, all
internal registers are cleared when CS is high. To initiate
another conversion CS must make a high to low transition
and for WM0832 MUX address assignments input to DI.
For WM0832 the DI input and DO output can be tied
together and controlled via a bidirectional processor I/O
bit line.
Reference Input
The analogue input voltage range, Vmax to Vmin for
differential inputs is defined by the voltage applied to the
reference input with respect to GND. WM0832 is fixed in a
ratiometric mode with VREF internally tied to Vcc, WM0832
has a separate VREF pin and can be used in either
ratiometric applications or those requiring absolute
accuracy.
A ratiometric reference input, typically the Vcc, is the same
supply used to power analogue input circuitry and
sensors. In such systems under a given input condition
the same code will be output with variations in supply
voltage because the same ratio change occurs in both the
analogue and reference input to the A/D. When used in
applications requiring absolute accuracy a suitable time
and temperature stable voltage reference source should
be used.
The voltage source used to drive the reference input should
be capable of driving the 2.4 kΩ typical of the SAR
resistor ladder. The maximum input voltage to the
reference input is the Vcc supply voltage. The minimum
for WM0832 can be at least as low as 1 V to allow for
direct conversion of sensor outputs with output voltage
ranges less than 5 V.
The output from the SARS comparator forms the
resulting input to the DAC and the A/D conversion output
on DO, and is read by the processor as conversion takes
place in MSB to LSB order. After 8 clock periods the
conversion is complete.
Wolfson Microelectronics
11
Page 12
WM0831, WM0832
Functional Description (continued)
Analogue Inputs.
While sampling the analogue inputs short spikes of
current enter a “+” input and flow out of the corresponding
“-” input at the clock edges during conversion. This
current does not cause errors as it decays rapidly and the
internal comparator is strobed at the end of a clock
period. Care should be exercised if bypass capacitors are
used at the inputs, as an apparent offset error can be
caused by the capacitor averaging the input current and
developing a voltage across the source resistance.
Bypass capacitors should not be used with a source
resistance greater than 1kΩ.
In considering error sources, input leakage current will also
cause a voltage drop across the source resistance and
hence high impedance sources should be buffered.
In differential mode there is a 1/2 clock period interval between sampling the “+” and the “-” inputs. If there is a change
in common mode voltage during this interval an error could
notionally result.
For a sinusoidal common mode signal the error is given
by :VERROR = VPEAK (2πfCM) (1/(2fCLK))
Where VPEAK = Peak common mode voltage
f
f
CM = Common mode signal frequency
CLK = Clock frequency.
12
Wolfson Microelectronics
Page 13
Package Descriptions
Plastic Small-Outline Package
D - 8 pins shown
WM0831, WM0832
4.00
3.80
6.20
5.80
1.75
1.35
0.25
0.10
A
58
14
Pin spacing
1.27 B.S.C.
Dimension 'A' Variations
NMinMax
84.805.00
148.558.75
169.8010.00
0.51
0.33
0.50
0.25
O
x 45 NOM
1.27
0.40
0.25
0.19
OO
0 to 8
Notes:
A. Dimensions in millimeters.
B. Complies with Jedec standard MS-012.
C. This drawing is subject to change without notice.
D. Body dimensions do not include mold flash or protrusion.
E. Dimension A, mould flash or protrusion shall not exceed 0.15mm. Body width, interlead flash or protrusions shall
A. Dimensions are in inches
B. Falls within JEDEC MS-001( 20 pin package is shorter than MS-001)
C. N is the maximum number of terminals
D. All end pins are partial width pins as shown, except the 14 pin package which is full width.
N/2
14
Rev. 1 November 96
Wolfson Microelectronics
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