Datasheet WF2M32U-150HI5A, WF2M32U-150HI5, WF2M32U-150HC5A, WF2M32U-150HC5, WF2M32U-150G2UM5A Datasheet (White Electronic Designs)

1

White Electronic Designs Corporation • Phoenix, AZ • [phone]

HI-RELIABILITY PRODUCT

WF2M32-XXX5

FIG. 1 PIN CONFIGURATION FOR WF2M32-XHX5

PIN DESCRIPTION

I/O0-31 Data Inputs/Outputs

A0-20 Address Inputs

WE1-4 Write Enables

CS1-4 Chip Selects

OE Output Enable

VCC Power Supply

GND Ground

I/O

8

I/O

9

I/O

10

A

14

A

16

A

11

A

0

A

18

I/O

0

I/O

1

I/O

2

WE

2

CS

2

GND

I/O

11

A

10

A

9

A

15

V

CC

CS

1

A

19

I/O

3

I/O

15

I/O

14

I/O

13

I/O

12

OE

A

17

WE

1

I/O

7

I/O

6

I/O

5

I/O

4

I/O

24

I/O

25

I/O

26

A

7

A

12

A

20

A

13

A

8

I/O

16

I/O

17

I/O

18

V

CC

CS

4

WE

4

I/O

27

A

4

A

5

A

6

WE

3

CS

3

GND

I/O

19

I/O

31

I/O

30

I/O

29

I/O

28

A

1

A

2

A

3

I/O

23

I/O

22

I/O

21

I/O

20

11 22 33 44 55 66

1 12 23 34 45 56

TOP VIEW

BLOCK DIAGRAM

2M x 8

8

I/O

0-7

WE CS

1

1

2M x 8

8

I/O

8-15

WE CS

2

2

2M x 8

8

I/O

16-23

WE CS

3

3

2M x 8

8

I/O

24-31

WE CS

4

4

A0-

20

OE

2Mx32 5V FLASH MODULE, SMD 5962-97531 (pending)

PRELIMINARY*

■ Commercial, Industrial, and Military Temperature Ranges

■ 5 Volt Read and Write. 5V ± 10% Supply.

■ Low Power CMOS

■ Data Polling and Toggle Bit feature for detection of program

or erase cycle completion.

■ Supports reading or programming data to a sector not being
erased.

■ RESET pin resets internal state machine to the read mode.

■ Built in Decoupling Caps and Multiple Ground Pins for Low

Noise Operation, Separate Power and Ground Planes to
improve noise immunity

* This data sheet describes a product under development, not fully

characterized, and is subject to change without notice.
Note: For programming information refer to Flash Programming 16M5

Application Note.

FEATURES

■ Access Time of 90, 120, 150ns

■ Packaging:

• 66 pin, PGA Type, 1.185" square, Hermetic Ceramic HIP
(Package 401).

• 68 lead, Hermetic CQFP (G2U), 22.4mm (0.880") square
(Package 510) 3.56mm (0.140") height. Designed to fit
JEDEC 68 lead 0.990" CQFJ footprint (Fig. 3)

■ Sector Architecture

• 32 equal size sectors of 64KBytes per each 2Mx8 chip

• Any combination of sectors can be erased. Also supports
full chip erase.

■ Minimum 100,000 Write/Erase Cycles Minimum

■ Organized as 2Mx32

RESET internally tied to Vcc in the HIP package for this pin configuration. See
Alternate Pin Configuration with RESET tied to pin 12 for system control of
reset (Fig. 10, page 11)

October 1999 Rev.3

2

White Electronic Designs Corporation • Phoenix, AZ • [phone]

WF2M32-XXX5

PIN DESCRIPTION

FIG. 2 PIN CONFIGURATION FOR WF2M32-XG2UX5

BLOCK DIAGRAM

TOP VIEW

The White 68 lead G2U CQFP
fills the same fit and function as
the JEDEC 68 lead CQFJ or 68
PLCC. But the G2U has the TCE
and lead inspection advantage
of the CQFP form.

2M x 8

8

I/O

0-7

2M x 8

8

I/O

8-15

2M x 8

8

I/O

16-23

2M x 8

8

I/O

24-31

A

0-20

OE

RESET

CS

1

CS

2

CS

3

CS

4

WE

3

WE

2

WE

1

WE

4

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

I/O

0

I/O

1

I/O

2

I/O

3

I/O

4

I/O

5

I/O

6

I/O

7

GND

I/O

8

I/O

9

I/O

10

I/O

11

I/O

12

I/O

13

I/O

14

I/O

15

V

CC

A11A12A13A14A15A

16

CS

1

OE

CS

2

A

17

WE2WE3WE

4

A

18

A19A

20

I/O

16

I/O

17

I/O

18

I/O

19

I/O

20

I/O

21

I/O

22

I/O

23

GND
I/O

24

I/O

25

I/O

26

I/O

27

I/O

28

I/O

29

I/O

30

I/O

31

RESET

A0A1A2A3A4A5CS3GND

CS4WE1A6A7A8A9A10V

CC

I/O0-31 Data Inputs/Outputs

A0-20 Address Inputs

WE1-4 Write Enables

CS1-4 Chip Selects

OE Output Enable

VCC Power Supply

GND Ground

RESET Reset

0.940"

3

White Electronic Designs Corporation • Phoenix, AZ • [phone]

WF2M32-XXX5

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Ratings Unit

Voltage on Any Pin Relative to VSS VT -2.0 to +7.0 V
Power Dissipation PT 8W
Storage Temperature Tstg -65 to +125 °C
Short Circuit Output Current IOS 100 mA

Endurance - Write/Erase Cycles 100,000 min cycles
(Mil Temp)

Data Retention (Mil Temp) 20 years

RECOMMENDED DC OPERATING CONDITIONS

Parameter Symbol Min Typ Max Unit

Supply Voltage VCC 4.5 5.0 5.5 V
Ground VSS 00 0V
Input High Voltage VIH 2.0 - VCC + 0.5 V
Input Low Voltage VIL -0.5 - +0.8 V
Operating Temperature (Mil.) TA -55 - +125 °C
Operating Temperature (Ind.) T

A -40 - +85 °C

DC CHARACTERISTICS - CMOS COMPATIBLE

(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)

NOTES:

1. The Icc current listed includes both the DC operating current and the frequency dependent component (@ 5MHz). The frequency component typically is less than
2mA/MHz, with OE at VIH.

2. Icc active while Embedded Algorithm (program or erase) is in progress.

3. DC test conditions V

IL = 0.3V, VIH = VCC - 0.3V

Parameter Symbol Conditions Min Max Unit

Input Leakage Current ILI VCC = 5.5, VIN = GND to VCC 10 µA
Output Leakage Current ILOx32 VCC = 5.5, V IN = GND to VCC 10 µA
VCC Active Current for Read (1) ICC1 CS = V IL, OE = VIH, f = 5MHz 160 mA
VCC Active Current for Program or Erase (2) I CC2 CS = VIL, OE = VIH 240 mA
VCC Standby Current ICC3 VCC = 5.5, CS = VIH, f = 5MHz, RESET = Vcc ± 0.3V 8.0 mA
Output Low Voltage VOL IOL = 12.0 mA, VCC = 4.5 0.45 V
Output High Voltage VOH IOH = -2.5 mA, VCC = 4.5 0.85xVcc V
Low VCC Lock-Out Voltage VLKO 3.2 4.2 V

CAPACITANCE

(TA = +25°C)

Parameter

Symbol

Conditions Max Unit

OE capacitance COE

VIN = 0 V, f = 1.0 MHz

50 pF

WE

1-4 capacitance CWEVIN

= 0 V, f = 1.0 MHz

pF
HIP (PGA) 20
HIP (Alternate pinout) 50
CQFP G4T 50
CQFP G2U 20
G2 (Alternate pinout) 50

CS1-4 capacitance CCS

VIN = 0 V, f = 1.0 MHz

20 pF

Data I/O capacitance CI/O

V

I/O

= 0 V, f = 1.0 MHz

20 pF

Address input capacitance C

ADVIN

= 0 V, f = 1.0 MHz

50 pF

This parameter is guaranteed by design but not tested.

4

White Electronic Designs Corporation • Phoenix, AZ • [phone]

WF2M32-XXX5

AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS - WE CONTROLLED

(V

CC = 5.0V, TA = -55°C to +125°C)

Parameter Symbol -90 -120 -150 Unit

Min Max Min Max Min Max

Write Cycle Time tAVAV tWC 90 120 150 ns
Chip Select Setup Time tELWL tCS 000ns
Write Enable Pulse Width tWLWH tWP 45 50 50 ns
Address Setup Time tAVWL tAS 000ns
Data Setup Time tDVWH tDS 45 50 50 ns
Data Hold Time tWHDX tDH 000ns
Address Hold Time tWLAX tAH 45 50 50 ns
Write Enable Pulse Width High tWHWL tWPH 20 20 20 ns
Duration of Byte Programming Operation (1) tWHWH1 300 300 300 µs
Sector Erase (2) tWHWH2 15 15 15 sec
Read Recovery Time before Write tGH

W

L 000µs

VCC Setup Time tVCS 50 50 50 µs
Chip Programming Time 44 44 44 sec
Chip Erase Time (3) 256 256 256 sec
Output Enable Hold Time (4) tOEH 10 10 10 ns
RESET Pulse Width (5) t

RP 500 500 500 ns

NOTES:

1. Typical value for t

WHWH1 is 7µs.

2. Typical value for t

WHWH2 is 1sec.

3. Typical value for Chip Erase Time is 32sec.

4. For Toggle and Data Polling.

5. RESET internally tied to Vcc for the default pin configuration in the HIP package.

AC CHARACTERISTICS – READ-ONLY OPERATIONS

(V

CC = 5.0V, TA = -55°C to +125°C)

Parameter Symbol -90 -120 -150 Unit

Min Max Min Max Min Max

Read Cycle Time tAVAV tRC 90 120 150 ns
Address Access Time tAVQV tACC 90 120 150 ns
Chip Select Access Time tELQV tCE 90 120 150 ns
Output Enable to Output Valid tGLQV tOE 40 50 55 ns
Chip Select High to Output High Z (1) tEHQZ tDF 20 30 35 ns
Output Enable High to Output High Z (1) tGHQZ tDF 20 30 35 ns
Output Hold from Addresses, CS or OE Change, t

AXQX tOH 000ns

whichever is First
RST Low to Read Mode (1,2) t

Ready 20 20 20 µs

1. Guaranteed by design, not tested.

2. RESET internally tied to Vcc for the default pin configuration in the HIP package.

5

White Electronic Designs Corporation • Phoenix, AZ • [phone]

WF2M32-XXX5

CS

WE

RY/BY

RESET

t

RP

The rising edge of the last WE signal

Entire programming
or erase operations

t

Ready

t

BUSY

AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS,CS CONTROLLED

(V

CC = 5.0V, VSS = 0V, TA = -55°C to +125°C)

FIG. 3

AC TEST CIRCUIT

AC TEST CONDITIONS

NOTES:

V

Z is programmable from -2V to +7V.

I

OL & IOH programmable from 0 to 16mA.

Tester Impedance Z

0 = 75 Ω.

V

Z is typically the midpoint of VOH and VOL.

I

OL & IOH

are adjusted to simulate a typical resistive load circuit.

ATE tester includes jig capacitance.

Parameter Typ Unit

Input Pulse Levels

VIL = 0, VIH = 3.0

V
Input Rise and Fall 5 ns
Input and Output Reference Level 1.5 V
Output Timing Reference Level 1.5 V

I

Current Source

D.U.T.

C = 50 pf

eff

I

OL

V ≈ 1.5V
(Bipolar Supply)

Z

Current Source

OH

Parameter Symbol -90 -120 -150 Unit

Min Max Min Max Min Max

Write Cycle Time tAVAV tWC 90 120 150 ns
Write Enable Setup Time tWLEL tWS 000ns
Chip Select Pulse Width tELEH tCP 45 50 50 ns
Address Setup Time tAVEL tAS 000ns
Data Setup Time tDVEH tDS 45 50 50 ns
Data Hold Time tEHDX tDH 000ns
Address Hold Time tELAX tAH 45 50 50 ns
Chip Select Pulse Width High tEHEL tCPH 20 20 20 ns
Duration of Byte Programming Operation (1) tWHWH1 300 300 300 µs
Sector Erase Time (2) tWHWH2 15 15 15 sec
Read Recovery Time tGHEL 000µs
Chip Programming Time 44 44 44 sec
Chip Erase Time (3) 256 256 256 sec
Output Enable Hold Time (4) t

OEH 10 10 10 ns

NOTES:

1. Typical value for t

WHWH1 is 7µs.

2. Typical value for t

WHWH2 is 1sec.

3. Typical value for Chip Erase Time is 32sec.

4. For Toggle and Data Polling.

FIG. 4

RESET TIMING DIAGRAM

6

White Electronic Designs Corporation • Phoenix, AZ • [phone]

WF2M32-XXX5

FIG. 5

AC WAVEFORMS FOR READ OPERATIONS

Addresses

CS

OE

WE

Outputs

High Z

Addresses Stable

t

OE

t

RC

Output Valid

t

CE

t

ACC

t

OH

High Z

t

DF

7

White Electronic Designs Corporation • Phoenix, AZ • [phone]

WF2M32-XXX5

NOTES:

1. PA is the address of the memory location to be programmed.

2. PD is the data to be programmed at byte address.

3. D

7 is the output of the complement of the data written to each chip.

4. D

OUT is the output of the data written to the device.

5. Figure indicates last two bus cycles of four bus cycle sequence.

FIG. 6

WRITE/ERASE/PROGRAM
OPERATION, WE CONTROLLED

Addresses

CS

OE

WE

Data

5.0 V

5555H PA PA

t

WC

tCS

PD

D7

DOUT

tAH

tWPH

tDH

tDS

Data Polling

tAS

tRC

tWP

A0H

tOE

tDF

tOH

tCE

tGHWL

tWHWH1

8

White Electronic Designs Corporation • Phoenix, AZ • [phone]

WF2M32-XXX5

FIG. 7

AC WAVEFORMS CHIP/SECTOR
ERASE OPERATIONS

NOTE:

1. SA is the sector address for Sector Erase.

Addresses

CS

OE

WE

Data

V

CC

5555H 2AAAH 2AAAH SA5555H 5555H

t

WP

t

CS

t

VCS

10H/30H55H80H55H AAHAAH

t

AH

t

GHWL

t

WPH

t

DH

t

DS

t

AS

9

White Electronic Designs Corporation • Phoenix, AZ • [phone]

WF2M32-XXX5

FIG. 8

AC WAVEFORMS FOR DATA POLLING
DURING EMBEDDED ALGORITHM OPERATIONS

CS

OE

WE

t

OE

t

CE

t

CH

t

OH

D7

D7 =

Valid Data

High Z

D0-D6 = Invalid

D0-D7

Valid Data

t

DF

D7

D0-D6

t

OEH

t

WHWH 1 or 2

Data

10

White Electronic Designs Corporation • Phoenix, AZ • [phone]

WF2M32-XXX5

NOTES:

1. PA represents the address of the memory location to be programmed.

2. PD represents the data to be programmed at byte address.

3. D

7 is the output of the complement of the data written to each chip.

4. D

OUT is the output of the data written to the device.

5. Figure indicates the last two bus cycles of a four bus cycle sequence.

Addresses

WE

OE

CS

Data

5.0 V

5555H PA PA

t

WC

t

WS

PD

D

7

D

OUT

t

AH

t

CPH

t

CP

t

DH

t

DS

Data Polling

t

AS

t

GHEL

A0H

t

WHWH1

FIG. 9

ALTERNATE CS CONTROLLED
PROGRAMMING OPERATION TIMINGS

11

White Electronic Designs Corporation • Phoenix, AZ • [phone]

WF2M32-XXX5

FIG. 10 ALTERNATE PIN CONFIGURATION FOR WF2M32I-XHX5

PIN DESCRIPTION

I/O0-31 Data Inputs/Outputs

A0-20 Address Inputs

WE Write Enable

CS1-4 Chip Selects

OE Output Enable

VCC Power Supply

GND Ground

RESET Reset

I/O

8

I/O

9

I/O

10

A

14

A

16

A

11

A

0

A

18

I/O

0

I/O

1

I/O

2

RESET

CS

2

GND

I/O

11

A

10

A

9

A

15

V

CC

CS

1

A

19

I/O

3

I/O

15

I/O

14

I/O

13

I/O

12

OE

A

17

WE

I/O

7

I/O

6

I/O

5

I/O

4

I/O

24

I/O

25

I/O

26

A

7

A

12

NC

A

13

A

8

I/O

16

I/O

17

I/O

18

V

CC

CS

4

NC

I/O

27

A

4

A

5

A

6

A

20

CS

3

GND

I/O

19

I/O

31

I/O

30

I/O

29

I/O

28

A

1

A

2

A

3

I/O

23

I/O

22

I/O

21

I/O

20

11 22 33 44 55 66

1 12 23 34 45 56

TOP VIEW

BLOCK DIAGRAM

2M x 8

8

I/O

0-7

CS

1

2M x 8

8

I/O

8-15

CS

2

2M x 8

8

I/O

16-23

CS

3

2M x 8

8

I/O

24-31

CS

4

A0-

20

OE

WE

RESET

PIN DESCRIPTION

FIG. 11 ALTERNATE PIN CONFIGURATION FOR WF2M32U-XG2UX5

BLOCK DIAGRAM

TOP VIEW

The White 68 lead G2U CQFP
fills the same fit and function as
the JEDEC 68 lead CQFJ or 68
PLCC. But the G2U has the TCE
and lead inspection advantage
of the CQFP form.

2M x 8

8

I/O

0-7

2M x 8

8

I/O

8-15

2M x 8

8

I/O

16-23

2M x 8

8

I/O

24-31

A

0-20

OE

RESET

CS

WE

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

I/O

0

I/O

1

I/O

2

I/O

3

I/O

4

I/O

5

I/O

6

I/O

7

GND

I/O

8

I/O

9

I/O

10

I/O

11

I/O

12

I/O

13

I/O

14

I/O

15

V

CC

A11A12A13A14A15A

16

CS

OE

NC

A

17

NCNCNC

A

18A19A20

I/O

16

I/O

17

I/O

18

I/O

19

I/O

20

I/O

21

I/O

22

I/O

23

GND
I/O

24

I/O

25

I/O

26

I/O

27

I/O

28

I/O

29

I/O

30

I/O

31

RESET

A0A1A2A3A4A5NC

GNDNCWE

A6A7A8A9A10V

CC

I/O0-31 Data Inputs/Outputs

A0-20 Address Inputs

WE Write Enable

CS Chip Select
OE Output Enable

VCC Power Supply

GND Ground

RESET Reset

0.940"

12

White Electronic Designs Corporation • Phoenix, AZ • [phone]

WF2M32-XXX5

PACKAGE 401: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H)

30.1 (1.185) ± 0.38 (0.015) SQ

25.4 (1.0) TYP

15.24 (0.600) TYP

0.76 (0.030) ± 0.1 (0.005)

6.22 (0.245)
MAX

3.81 (0.150)

± 0.1 (0.005)

2.54 (0.100)
TYP

25.4 (1.0) TYP

1.27 (0.050) ± 0.1 (0.005)

1.27 (0.050) TYP DIA

0.46 (0.018) ± 0.05 (0.002) DIA

PIN 1 IDENTIFIER

SQUARE PAD

ON BOTTOM

ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES

13

White Electronic Designs Corporation • Phoenix, AZ • [phone]

WF2M32-XXX5

PACKAGE 510: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2U)

0.38 (0.015) ± 0.05 (0.002)

0.25 (0.010) ± 0.10 (0.002)

25.15 (0.990) ± 0.25 (0.010) SQ

1.27 (0.050) TYP

24.0 (0.946)

± 0.25 (0.010)

22.36 (0.880) ± 0.25 (0.010) SQ

20.3 (0.800) REF

23.87

(0.940) REF

1.01 (0.040)

± 0.13 (0.005)

0.25 (0.010) REF

1° / 7°

R 0.25

(0.010)

DETAIL A

SEE DETAIL "A"

Pin 1

0.53 (0.021)
± 0.18 (0.007)

3.51 (0.140) MAX

ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES

0.940"
TYP

The White 68 lead G2U CQFP
fills the same fit and function as
the JEDEC 68 lead CQFJ or 68
PLCC. But the G2U has the TCE
and lead inspection advantage
of the CQFP form.

14

White Electronic Designs Corporation • Phoenix, AZ • [phone]

WF2M32-XXX5

ORDERING INFORMATION

LEAD FINISH:

Blank = Gold plated leads
A = Solder dip leads

V

PP PROGRAMMING VOLTAGE

5 = 5 V

DEVICE GRADE:

M= Military Screened -55°C to +125°C
I = Industrial -40°C to +85°C
C = Commercial 0°C to +70°C

PACKAGE TYPE:

H = Ceramic Hex In line Package, HIP (Package 401)
G2U = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 510)

ACCESS TIME (ns)

IMPROVEMENT MARK

• For HIP Package

Blank = 4CS and 4WE
I = 4CS and 1WE, RESET

• For G2U Package

Blank = 4CS and 4WE
U = 1CS and 1WE

ORGANIZATION, 2M x 32

User configurable as 4M x 16 or 8M x 8
(Except WF2M32U-XG2UX which is 32 bit wide only.)

Flash PROM

WHITE ELECTRONIC DESIGNS CORP.

W F 2M32 X - XXX X X 5 X

2M x 32 5V Flash Module 64KByte 150ns 66 pin HIP (H) 5962-97531 01HXX*
2M x 32 5V Flash Module 64KByte 120ns 66 pin HIP (H) 5962-97531 02HXX*
2M x 32 5V Flash Module 64KByte 90ns 66 pin HIP (H) 5962-97531 03HXX*

2M x 32 5V Flash Module 64KByte 150ns 68 lead CQFP/J (G2U) 5962-97531 01HXX*
2M x 32 5V Flash Module 64KByte 120ns 68 lead CQFP/J (G2U) 5962-97531 02HXX*
2M x 32 5V Flash Module 64KByte 90ns 68 lead CQFP/J (G2U) 5962-97531 03HXX*

DEVICE TYPE SECTOR SIZE SPEED PACKAGE SMD NO.

* Pending