Datasheet WF2M16W-90FLM5A, WF2M16W-90FLM5, WF2M16W-90FLI5A, WF2M16W-90FLI5, WF2M16W-90FLC5A Datasheet (White Electronic Designs)
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White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
HI-RELIABILITY PRODUCT
WF2M16-XXX5
November 1999 Rev. 3
2Mx16 FLASH MODULE, SMD 5962-97610 (pending)
PRELIMINARY*
FEATURES
■ Access Times of 90, 120, 150ns
■ Packaging:
• 56 lead, Hermetic Ceramic, 0.520" CSOP (Package 207).
Fits standard 56 SSOP footprint.
• 44 pin Ceramic SOJ (Package 102)**
• 44 lead Ceramic Flatpack (Package 208)**
■ Sector Architecture
• 32 equal size sectors of 64KBytes each
• Any combination of sectors can be erased. Also supports
full chip erase.
■ Minimum 100,000 Write/Erase Cycles Minimum
■ Organized as 2Mx16; User Configurable as 2 x 2Mx8
■ Commercial, Industrial, and Military Temperature Ranges
■ 5 Volt Read and Write. 5V ± 10% Supply.
■ Low Power CMOS
■ Data Polling and Toggle Bit feature for detection of program
or erase cycle completion.
■ Supports reading or programming data to a sector not being
erased.
■ Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation.
■ RESET pin resets internal state machine to the read mode.
■ Ready/Busy (RY/BY) output for detection of program or
erase cycle completion.
■ Multiple Ground Pins for Low Noise Operation
* This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
** Package to be developed.
Note: For programming information refer to Flash Programming 16M5
Application Notes.
FIG. 1 PIN CONFIGURATIONS
PIN DESCRIPTION
I/O0-15 Data Inputs/Outputs
A0-20 Address Inputs
WE Write Enable
CS1-2 Chip Select
OE Output Enable
VCC Power Supply
VSS Ground
RY/BY Ready/Busy
RESET Reset
BLOCK DIAGRAM
NOTE:
1. RY/BY is an open drain output and should be pulled up to Vcc
with an external resistor.
2. Address compatible with Intel 2M8 56 SSOP.
TOP VIEW
WF2M16-XDAX5
56 CSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CS1
A12
A13
A14
A15
NC
CS2
NC
A20
A19
A18
A17
A16
V
CC
GND
I/O6
I/O14
I/O7
I/O15
RY/BY
OE
WE
NC
I/O13
I/O5
I/O12
I/O4
V
CC
NC
RESET
A11
A10
A9
A1
A2
A3
A4
A5
A6
A7
GND
A8
V
CC
I/O9
I/O1
I/O8
I/O0
A0
NC
NC
NC
I/O2
I/O10
I/O3
I/O11
GND
2M x 8
2M x 8
A
0-20
OE
WE
CS
1
CS
2
I/O
0-7
I/O
8-15
RESET
RY/BY
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A15
A14
A13
A12
A11
A10
A9
A8
RESET
CS1
V
CC
V
SS
CS2
RY/BY
A7
A6
A5
A4
A3
A2
A1
A0
A16
A17
A18
A19
A20
OE
I/O7
I/O6
I/O5
I/O4
V
SS
VCC
I/O3
I/O2
I/O1
I/O0
WE
NC
NC
NC
NC
NC
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
WF2M16-XXX5
44 CSOJ (DL)**
44 FLATPACK (FL)**
** Package to be developed.
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WF2M16-XXX5
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Ratings Unit
Voltage on Any Pin Relative to VSS VT -2.0 to +7.0 V
Power Dissipation PT 8W
Storage Temperature Tstg -65 to +125 °C
Short Circuit Output Current IOS 100 mA
Data Retention (Mil Temp) 20 years
Endurance - write/erase cycles 100,000 min. cycles
(Mil Temp)
RECOMMENDED DC OPERATING CONDITIONS
Parameter Symbol Min Typ Max Unit
Supply Voltage VCC 4.5 5.0 5.5 V
Ground VSS 00 0V
Input High Voltage VIH 2.0 - VCC + 0.5 V
Input Low Voltage VIL -0.5 - +0.8 V
Operating Temperature (Mil.) TA -55 - +125 °C
Operating Temperature (Ind.) T
A -40 - +85 °C
DC CHARACTERISTICS - CMOS COMPATIBLE
(V
CC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
NOTES:
1. The Icc current listed includes both the DC operating current and the frequency dependent component (@ 5MHz). The frequency component typically is less than
2mA/MHz, with OE at VIH.
2. Icc active while Embedded Algorithm (program or erase) is in progress.
3. DC test conditions V
IL = 0.3V, VIH = VCC - 0.3V
Parameter Symbol Conditions Min Max Unit
Input Leakage Current ILI VCC = 5.5, VIN = GND to VCC 10 µA
Output Leakage Current ILO VCC = 5.5, VIN = GND to VCC 10 µA
VCC Active Current for Read (1) ICC1 CS = VIL, OE = VIH, f = 5MHz 80 mA
VCC Active Current for Program or Erase (2) ICC2 CS = VIL, OE = VIH 120 mA
VCC Standby Current ICC3 VCC = 5.5, CS = VIH, f = 5MHz, RESET = Vcc ± 0.3V 4.0 mA
Output Low Voltage VOL IOL = 12.0 mA, VCC = 4.5 0.45 V
Output High Voltage VOH IOH = -2.5 mA, VCC = 4.5 0.85xVcc V
Low VCC Lock-Out Voltage VLKO 3.2 4.2 V
CAPACITANCE
(TA = +25°C)
Parameter
Symbol
Conditions Max Unit
OE capacitance COE
VIN = 0 V, f = 1.0 MHz
25 pF
WE capacitance CWE
VIN = 0 V, f = 1.0 MHz
25 pF
CS capacitance CCS
VIN = 0 V, f = 1.0 MHz
15 pF
Data I/O capacitance CI/O
V
I/O
= 0 V, f = 1.0 MHz
15 pF
Address input capacitance C
ADVIN
= 0 V, f = 1.0 MHz
25 pF
This parameter is guaranteed by design but not tested.
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WF2M16-XXX5
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS - WE CONTROLLED
(V
CC = 5.0V, TA = -55°C to +125°C)
Parameter Symbol -90 -120 -150 Unit
Min Max Min Max Min Max
Write Cycle Time tAVAV tWC 90 120 150 ns
Chip Select Setup Time tELWL tCS 000ns
Write Enable Pulse Width tWLWH tWP 45 50 50 ns
Address Setup Time tAVWL tAS 000ns
Data Setup Time tDVWH tDS 45 50 50 ns
Data Hold Time tWHDX tDH 000ns
Address Hold Time tWLAX tAH 45 50 50 ns
Write Enable Pulse Width High tWHWL tWPH 20 20 20 ns
Duration of Byte Programming Operation (1) tWHWH1 300 300 300 µs
Sector Erase (2) tWHWH2 15 15 15 sec
Read Recovery Time before Write tGH
W
L 000µs
VCC Setup Time tVCS 50 50 50 µs
Chip Programming Time 44 44 44 sec
Chip Erase Time (3) 256 256 256 sec
Output Enable Hold Time (4) tOEH 10 10 10 ns
RESET Pulse Width t
RP 500 500 500 ns
NOTES:
1. Typical value for t
WHWH1 is 7µs.
2. Typical value for tWHWH2 is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
AC CHARACTERISTICS – READ-ONLY OPERATIONS
(V
CC = 5.0V, TA = -55°C to +125°C)
Parameter Symbol -90 -120 -150 Unit
Min Max Min Max Min Max
Read Cycle Time tAVAV tRC 90 120 150 ns
Address Access Time tAVQV tACC 90 120 150 ns
Chip Select Access Time tELQV tCE 90 120 150 ns
Output Enable to Output Valid tGLQV tOE 40 50 55 ns
Chip Select High to Output High Z (1) tEHQZ tDF 20 30 35 ns
Output Enable High to Output High Z (1) tGHQZ tDF 20 30 35 ns
Output Hold from Addresses, CS or OE Change, t
AXQX tOH 000ns
whichever is First
RESET Low to Read Mode (1) t
Ready 20 20 20 µs
1. Guaranteed by design, not tested.
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WF2M16-XXX5
CS
WE
RY/BY
RESET
t
RP
The rising edge of the last WE signal
Entire programming
or erase operations
t
Ready
t
BUSY
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS,CS CONTROLLED
(V
CC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
FIG. 2
AC TEST CIRCUIT
AC TEST CONDITIONS
NOTES:
V
Z is programmable from -2V to +7V.
I
OL & IOH programmable from 0 to 16mA.
Tester Impedance Z
0 = 75 Ω.
V
Z is typically the midpoint of VOH and VOL.
I
OL & IOH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
Parameter Typ Unit
Input Pulse Levels
VIL = 0, VIH = 3.0
V
Input Rise and Fall 5 ns
Input and Output Reference Level 1.5 V
Output Timing Reference Level 1.5 V
I
Current Source
D.U.T.
C = 50 pf
eff
I
OL
V ≈ 1.5V
(Bipolar Supply)
Z
Current Source
OH
Parameter Symbol -90 -120 -150 Unit
Min Max Min Max Min Max
Write Cycle Time tAVAV tWC 90 120 150 ns
Write Enable Setup Time tWLEL tWS 000ns
Chip Select Pulse Width tELEH tCP 45 50 50 ns
Address Setup Time tAVEL tAS 000ns
Data Setup Time tDVEH tDS 45 50 50 ns
Data Hold Time tEHDX tDH 000ns
Address Hold Time tELAX tAH 45 50 50 ns
Chip Select Pulse Width High tEHEL tCPH 2 0 20 20 ns
Duration of Byte Programming Operation (1) tWHWH1 300 300 300 µs
Sector Erase Time (2) tWHWH2 15 15 15 sec
Read Recovery Time tGHEL 000µs
Chip Programming Time 44 44 44 sec
Chip Erase Time (3) 256 256 256 sec
Output Enable Hold Time (4) t
OEH 10 10 10 ns
NOTES:
1. Typical value for tWHWH1 is 7µs.
2. Typical value for t
WHWH2 is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
FIG. 3
RESET TIMING DIAGRAM
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WF2M16-XXX5
FIG. 3
AC WAVEFORMS FOR READ OPERATIONS
Addresses
CS
OE
WE
Outputs
High Z
Addresses Stable
t
OE
t
RC
Output Valid
t
CE
t
ACC
t
OH
High Z
t
DF
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WF2M16-XXX5
NOTES:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. D
7 is the output of the complement of the data written to the device.
4. D
OUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
FIG. 4
WRITE/ERASE/PROGRAM
OPERATION, WE CONTROLLED
Addresses
CS
OE
WE
Data
5.0 V
5555H PA PA
t
WC
tCS
PD
D7
DOUT
tAH
tWPH
tDH
tDS
Data Polling
tAS
tRC
tWP
A0H
tOE
tDF
tOH
tCE
tGHWL
tWHWH1
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WF2M16-XXX5
FIG. 5
AC WAVEFORMS CHIP/SECTOR
ERASE OPERATIONS
NOTE:
1. SA is the sector address for Sector Erase.
Addresses
CS
OE
WE
Data
V
CC
5555H 2AAAH 2AAAH SA5555H 5555H
t
WP
t
CS
t
VCS
10H/30H55H80H55H AAHAAH
t
AH
t
GHWL
t
WPH
t
DH
t
DS
t
AS
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WF2M16-XXX5
FIG. 6
AC WAVEFORMS FOR DATA POLLING
DURING EMBEDDED ALGORITHM OPERATIONS
CS
OE
WE
t
OE
t
CE
t
CH
t
OH
D7
D7 =
Valid Data
High Z
D0-D6 = Invalid
D0-D7
Valid Data
t
DF
D7
D0-D6
t
OEH
t
WHWH 1 or 2
Data
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White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF2M16-XXX5
NOTES:
1. PA represents the address of the memory location to be programmed.
2. PD represents the data to be programmed at byte address.
3. D
7 is the output of the complement of the data written to the device.
4. D
OUT is the output of the data written to the device.
5. Figure indicates the last two bus cycles of a four bus cycle sequence.
Addresses
WE
OE
CS
Data
5.0 V
5555H PA PA
t
WC
t
WS
PD
D
7
D
OUT
t
AH
t
CPH
t
CP
t
DH
t
DS
Data Polling
t
AS
t
GHEL
A0H
t
WHWH1
FIG. 7
ALTERNATE CS CONTROLLED
PROGRAMMING OPERATION TIMINGS
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WF2M16-XXX5
PACKAGE 208: 44 LEAD, CERAMIC FLAT PACK**
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
28.45 (1.120)
± 0.26 (0.010)
32.64 (1.285) TYP
12.95 (0.510)
± 0.13 (0.005)
3.81 (0.150)
TYP
3.18 (0.125)
MAX
0.13 (0.005)
± 0.05 (0.002)
PIN 1
IDENTIFIER
1.27 (0.050) TYP
9.90 (0.390)
± 0.13 (0.005)
26.67 (1.050) TYP
43.17 (1.699) ± 0.39 (0.015)
12.70 (0.500)
± 0.51 (0.020)
5.08 (0.200)
± 0.25 (0.010)
0.43 (0.017)
± 0.05 (0.002)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
PACKAGE 102: 44 LEAD, CERAMIC SOJ**
1.27 (0.050) TYP
28.70 (1.13) ± 0.25 (0.010)
PIN 1 IDENTIFIER
26.7 (1.050) TYP
11.3 (0.446)
± 0.2 (0.009)
3.96 (0.156) MAX
0.2 (0.008)
± 0.05 (0.002)
9.55 (0.376) ± 0.25 (0.010)
1.27 (0.050) ± 0.25 (0.010)
0.89 (0.035)
Radius TYP
** Package to be developed.
** Package to be developed.
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White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF2M16-XXX5
FIG. 8 ALTERNATE PIN CONFIGURATION FOR WF2M16W-XDAX5
PIN DESCRIPTION
I/O0-15 Data Inputs/Outputs
A1-21 Address Inputs
WE Write Enable
CS1-2 Chip Select
OE Output Enable
VCC Power Supply
VSS Ground
RY/BY Ready/Busy
RESET Reset
BLOCK DIAGRAM
NOTE:
1. RY/BY is an open drain output and should be pulled up to Vcc with
an external resistor.
2. Address compatible with Intel 1M16 56 SSOP.
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CS1
A12
A13
A14
A15
NC
CS2
A21
A20
A19
A18
A17
A16
V
CC
GND
I/O6
I/O14
I/O7
I/O15
RY/BY
OE
WE
NC
I/O13
I/O5
I/O12
I/O4
V
CC
NC
RESET
A11
A10
A9
A1
A2
A3
A4
A5
A6
A7
GND
A8
V
CC
I/O9
I/O1
I/O8
I/O0
NC
NC
NC
NC
I/O2
I/O10
I/O3
I/O11
GND
56 CSOP
2M x 8
2M x 8
A
1-21
OE
WE
CS
1
CS
2
I/O
0-7
I/O
8-15
RESET
RY/BY
PACKAGE 207: 56 LEAD, CERAMIC SOP*
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
* Package Dimensions subject to change
23.63 (0.930) ± 0.25 (0.010)
12.96 (0.510)
± 0.15 (0.006)
0.18 (0.007)
± 0.05 (0.002)
21.59 (0.850) TYP
16.13 (0.635)
± 0.13 (0.005)
0.25 (0.010)
± 0.05 (0.002)
0.80 (0.031) TYP
4.06 (0.160)
MAX
PIN 1 IDENTIFIER
0° / -4°
0.51 (0.020) TYP
DETAIL "A"
SEE DETAIL "A"
+
1.02 (0.040)
± 0.18 (0.007)
+
1.60 (0.063) TYP
2.87 (0.113)
MAX
R = 0.18 (0.007) TYP
Page 12
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WF2M16-XXX5
W F 2M16 X - XXX X X 5 X
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
VPP PROGRAMMING VOLTAGE
5 = 5V
DEVICE GRADE:
M = Military, 883 Screened -55°C to +125°C
I = Industrial -40°C to +85°C
C = Commercial 0°C to +70°C
PACKAGE TYPE:
DA = 56 Lead CSOP (Package 207)
fits standard 56 SSOP footprint
DL = 44 Lead Ceramic SOJ (Package 102)*
FL = 44 Lead Ceramic Flatpack (Package 208)*
ACCESS TIME (ns)
IMPROVEMENT MARK:
• Address Pinout for 56 CSOP Package
W = Word Wide Applications
ORGANIZATION of 2 M x 1 6
User configurable as 2 x 2M x 8
Flash
WHITE ELECTRONIC DESIGNS CORP.
ORDERING INFORMATION
* Package to be developed.
DEVICE TYPE SECTOR SIZE SPEED PACKAGE SMD NO.
2M x 16 5V Flash Module 64KByte 150ns 56 lead CSOP (DA) 5962-97610 01HXX*
2M x 16 5V Flash Module 64KByte 120ns 56 lead CSOP (DA) 5962-97610 02HXX*
2M x 16 5V Flash Module 64KByte 90ns 56 lead CSOP (DA) 5962-97610 03HXX*
* Pending
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