Datasheet W.A.R.P.2.0 Datasheet (ST)

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Digital Fuzzy Co-processor8-bit I/O
HighSpeed Rules Processing

4 Input, 2 Output,32 Rules in 33.1µs
Upto 256Rules(4 Antecedents,1 Consequent)
Up to 8 Input ConfigurableVariables
Up to 16 MembershipFunctions for an Input

Variable
AntecedentMembershipFunctions with

Triangular and TrapezoidalShape
Up to 4 Output Variables
Up to 256 MembershipFunctionsfor all

Consequents
SingletonConsequentMembership Functions
Defuzzification on chip
MaximumClock Frequency40MHz
A/D Start Convertion Pulse presettable
Direct Interfaceto all popular microprocessor
HandshakingSignal Polarity presettable
Operates”STANDALONE” (without µP) if

desired
Standard+5V Supply Voltage
SoftwareTools and EmulatorsAvailability
Pinnumber: 52
68-leadPlastic Leaded Chip Carrierpackage.

W.A.R.P.2.0

8-BIT FUZZY CO-PROCESSOR

PRELIMINARYDATA

PLCC68

Figure1. Logic Diagram.

MCLK WAIT

VSS VDD

I0-I7

SIS0-SIS2

LASTIN

OE

AUTO

RD

READY

8

3

ERR

W.A.R. P .

2.0

PRESET

12

O0-O11

2

OC0-OC1

DS

ENDOFL

BUSYOFL

Figure2. SimplifiedBlock Diagram.

8

Input Port

with

HANDSHAKE

ANTECEDENT

MEMORY

March 1996

This isadvance informationon a new product now in development or undergoing evaluation. Details are subject to changewithoutnotice.

ALPHA

CALCULATOR

PROGRAM &

CONSEQUENT

MEMORY

INFERENCE

UNIT

INTERNALBUS

DEFUZZIFIER

PROGRAMMABLEA/D

OUTPUT PULSE

8

Ouput Port

with

HANDSHAKE

1/28

W.A.R.P.2.0

Figure3. Pin Connections

ncncI7I6I5I4I3I2VSSI1I0

VSS

VDD

MCLK

PRESET

OFL

AUTO

LASTIN

TEST

ENDOFL

ERR

BUSY

READY

VSS

VDD

Note:nc = Not Connected.

9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61

16 15 14 13 12 1110

OE
RD

DS

26 25 24 23 22 21 20 19 18 17

2728 29 30 31 32 33 34 35 36 37 3839 40 41 42 43

ncncnc

W.A.R.P. 2.0

VSS

OC1

VDD

GENERAL DESCRIPTION

W.A.R.P.2.0is a memberof the W.A.R.P. family of
fuzzy microprocessors, completelydevelopedand
producedbySGS-THOMSONMicroelectronicsus­ing the high performance, reliable HCMOS4T

(O.7µm)process.
W.A.R.P.2.0can beused bothas a Fuzzy Co-proc-

essor or as a stand-alone microcontroller. In the
former case, it can work together with standard
micros which shall perform normal control tasks
whileW.A.R.P.2.0 willbeindipendentlyresponsible
for all the fuzzy related computing.

W.A.R.P.2.0 core includes the fuzzifier (ALPHA
calculator),the inference unit, and the defuzzifier.
The I/O capabilities demandedby microprocessor
applicationsarefulfilledbyW.A.R.P.2.0with 8Input
and 4 Output lines which can be supported by
handshakingsignals.

The capability of preset the polarity of the hand­shaking signals simplifies the interface with the
host processor.

An internal Start Conversion pulse is provided to
allow simple use for waveform generation which
canbe directly applied to drivean A/D converter.

The output 3-STATE buffer can be temporarily
frozen in order to synchronize W.A.R.P.2.0 with
slower devices.

WAIT

SIS0

SIS1

SIS2ncnc

nc
nc
nc
VDD
VSS
O0
O1
O2
O3
O4
O5
O6
VDD
VSS
nc
nc
nc

44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

OC0

O11

O9O8O7

O10

VSS

VDD

ncncnc

Running W.A.R.P.2.0 involves a downloading
phase and an On-Line phase. The downloading
phase allows thesetting of the processor,in terms
of I/O number,universeof discourse,Membership
Functions (MFs) and rules. During this phase
W.A.R.P.2.0 preparesits internal memoriesfor the
On-Line elaboration phase and loads the micro­codeinitsprogrammemory.Thismicrocode,which
drives the On-Line phase, is generated by the
Compiler (see FUZZYSTUDIO2.0 User Man­ual).AfterthatW.A.R.P.2.0isreadytorun (On-Line
phase) processing inputs and producing the re­lated outputsaccordingto theconfigurationloaded
in the downloading phase. It is also possible to
provide the processor with inputs in any order by
specifyingtheir identificationnumbers.

Two basic memories are available in W.A.R.P.2.0 :
the Anteced ent Memory (AM) and the Pro­gram/Consequent Memory (PCM). The antece­dentMFs,portrayedbyaresolutionof 2
are stored in the AM (256 bytes). W.A.R.P.2.0
exploits a SGS-THOMSON patented strategy to
store the MFs in the AM.

The informationaboutRules andConsequentMFs
are stored in the PCM (1.4 Kbyte).

FUZZYSTUDIO2.0 is a powerful development
environment consisting of board and software al­lowsan easyconfigurationanduse ofW.A.R.P.2.0.

8

elements,

2/28

Table 1. Pin Description

Pin Assignment Name Pins Type Function

11,26,31,40,48,57 VDD - Power Supply

1,10,25,30,39,47,56 VSS - Ground

19 TEST I Testing(It must be connected to VSS)
12 MCLK I Master Clock (up to 40 MHz)
13 PRESET I Preset
15 AUTO I Auto/Manual-Boot

65 SIS0 I

64 SIS1 I

63 SIS2 I
67 I0 I Data Input bit 0

68 I1 I Data Input bit 1

2 I2 I Data Input bit 2
3 I3 I Data Input bit 3
4 I4 I Data Input bit 4
5 I5 I Data Input bit 5
6 I6 I Data Input bit 6

7 I7 I Data Input bit 7
14 OFL I Off-Line/On-Line Switch
18 RD I Handshaking Read Ready
16 LASTIN I Last Input (Start Elaboration) bit
17 OE I Output Enable/3-STATEbit
66 WAIT I Temporary Output Processing Stop
24 READY O Handshaking Output Signal
21 ENDOFL O Offline Phase (external memory downloading) End
23 BUSY O Elaboration Phase Indicator
20 DS O Data Strobe (Output Ready Signal)
22 ERR O ErrorFlag
33 OC0 O Output Identifier bit 0
32 OC1 O Output Identifier bit 1
55 O0 O External Memory Address/Defuzzified Output bit 0
54 O1 O External Memory Address/Defuzzified Output bit 1
53 O2 O External Memory Address/Defuzzified Output bit 2
52 O3 O External Memory Address/Defuzzified Output bit 3
51 O4 O External Memory Address/Defuzzified Output bit 4
50 O5 O External Memory Address/Defuzzified Output bit 5
49 O6 O External Memory Address/Defuzzified Output bit 6
38 O7 O External Memory Address/Defuzzified Output bit 7

37 O8 O

36 O9 O

35 O10 O

34 O11 O

Auto-Boot Speed (Ext. Memory Support AccessTime) /

Input Selection bit 0

Auto-Boot Speed (Ext. Memory Support Access Time) /

Input Selection bit 1

Auto-Boot Speed (Ext. Memory Support Access Time) /

Input Selection bit 2

ExternalMemory Address bit 8 /

Next Input Progressive Number bit 0

ExternalMemory Address bit 9 /

Next Input Progressive Number bit 1

External Memory Address bit 10 /

Next Input Progressive Number bit 2

External Memory Address bit 11 /

Start Conversion for the externalA/D

W.A.R.P.2.0

3/28

W.A.R.P.2.0

PINDESCRIPTION

Signals READY, RD, WAIT, DS, BUSY, LASTIN
and O11 ( external A/D Start Conversion) have
programmable polarity, see table 6 for default
values.

V

,VSS. Power is supplied to W.A.R.P. using

DD

these pins.V

isthe powerconnectionand VSSis

DD

the ground connection;multi-connectionsare nec­essary.

MCLK.

Master Clock

(Input): This is the input
master clock whose frequency can reach up to
40MHz(MAX).
During the Off-Line phase with AUTO High, the
MCLKis internallydividedto utilize boot memories
workingwitha slowerfrequency.Theaccessspeed
is presettableby means of SIS0-SIS2pins.

PRESET.

Preset

(Input, active Low) : This is the
restart pin of W.A.R.P.. It is possible to restart the
work during the computation (On-Line phase) or
before the writing of internal memories (Off-Line
phase). In both cases it must be put Low at least
for a clock period. After PRESET Low the proces­sor remainsin the resetstatus 3 MCLK pulses.

AUTO.

Auto-Boot:

(Input,activeHigh): During the
Off-Linephase AUTOHigh enables the automatic
bootof W.A.R.P.2.0 whereas AUTO Lowvalidates
the manual downloading.The manualboot has to
be performed using the handshaking signals
RD/READY.
During the On-Line phase AUTO High disables
the generation of the Start A/D conversion (O11)
signal.

SIS0-SIS2.

Speed& Input Selection

(Inputs): Dur­ingtheOff-Linephase withAUTOHigh(Auto-Boot)
SISbus allowstochoosethespeedofdownloading
fromthe externalmemorywhich containsthestart­upconfigurationof W.A.R.P.2.0.In thatcase (Auto­Boot)MCLKisinternallydividedtoprovideaslower
sinchronizationsignal which is automaticallyused
asRDfor thereadingof theexternalmemory.Table
2 shows how to preset the frequency of thissyn­chronizationsignal.
During the On-Line phase in Slave mode (see
RegisterBench description,Tab.5)SIS bus allows
to provide W.A.R.P.2.0with inputs in any order by
specifying their identification number. The input
and its identification number (SIS0-SIS2) will be
acquired at the next active RD so they must be
already stable when RD is given.

Table2. DownloadingSpeed

SIS0 SIS1 SIS2

Low Low Low MCLK/32

High Low Low MCLK/16

Internal Synchronization

Signal Frequency

I0-I7.

Input bus

(Input): During the Off-Linephase
these 8 data inputpins acceptaddresses anddata
from the e xte rna l boot memory cont aining
W.A.R.P.2.0 configuration. This start-up memory
(which can be a ZERO-POWER,the host proces­sor memory, an EPROM, a Flash,the PC Memory,
etc.) contains the fuzzy project built by means of
FUZZYSTUDIO2.0.
In On-Linemodethisbuscarriestheinputvariables
accordingto the prefixedorder.

OFL.

Offline

(Input, active High): When this pin is
High,the chipisenabledtoloaddataintheinternal
RAMs (Off-Linephase). It must be Low when the
fuzzy controller is waiting for input values and
during the processingphase (On-Linephase).
When OFL changes its status the processor re­mains presettedfor 3 clockpulses.

LASTIN.

Last Input

(Input, default active High):
During the On-Line phase in slave mode (see
RegisterBench description,table 5) LASTINHigh
indicates no other inputs have to be provided so
W.A.R.P.2.0 canstart the processing phase.
W.A.R.P.2.0 inputs are those in the input interface
so if some variables do not need to be acquired
again (because they change slower than others)
they remainstored and no extra time isrequired to
acquire them again.

OE.

Output Enable

(Input, active Low): OE Low
enables O0-011output bus or (if High) put it in
3-STATE.

Wait

WAIT.

(Input, default active High): This pin
High stops the output processing. When WAIT is
enabled W.A.R.P.2.0 finishes to compute the cur­rent output variable but it does not give it on the
output bus until WAIT becomes Low. This signal
allows to synchronize W.A.R.P.2.0with slower de­vices.

RD.

Read

(Input, default active High): Both in
Off-Line and in On-Line mode RD indicates data
are ready tobe acquired from the input bus I0-I7.

READY.

Ready

(Output,default active High): Both
in Off-Lineand in On-Linemode RDindicates data
have been acquired from the input bus I0-I7 and
are now stored in W.A.R.P.2.0 internal registers.

ENDOFL.

End of Off-Line phase

(Output, active
High): This pin indicates the end of the download­ing phase (Off-Line) so the content of the boot
memory is already stored in W.A.R.P.2.0 internal
memories.After ENDOFLis activetheusercan put
OFL Low so the On-Linephase canstart.

BUSY.

BusySignal

(Output, defaultactive High):
When the elaborationphase is running this pin is
active. When W.A.R.P.2.0finishesto compute the
last output variable, it puts BUSY Low and waits
for new inputs.

4/28

W.A.R.P.2.0

DS.

DataStrobe

strobe pin enables the user to utilize the output.
Whenthispin is High itindicatesthat a new output
variablehas beencalculatedand it is ready on the
output bus (O0-O7). This signal synchronizes the
external devices and in particular the interfaces
with the controlledprocesses (On-Line mode).

Error

ERR.

active,W.A.R.P.2.0has incurredin an internalerror
condition.

OC0-OC1.

output bus provides the output variables with a
progressivenumber during the On-Line phase.As
a consequence it is possible to know to which
variablecorrespond thedata thatare onthe output
data bus (O0-O7). The dimension of OC bus is
connected with the maximum number of output
variables(4).

(Output, defaultactive High): The

(Output, activeLow): When this pin is

Output Counter

(Output): This 2 bit

O0-O11.

phasethese pins providethe addresses (12bit) for
its internalmemories and send those addresses to
theexternalmemorysupportwheredatatoloadare
located. These addresses sent on O0-O11 bus
allow to identify the data that have to be loaded in
W.A.R.P.2.0internal memories.
In the On-Line phase O0-O7 carrie out the output
values. When the DS is High, one output variable
can be read by external devices. The resolution
of output variables is 256 points (8 bit). If there is
more than one output, the output variables are
calculated one by one and they are provided in
the sequence stabilized during the editing phase
(see FUZZYSTUDIO 2.0 User Manual).

In On-Line mode O8-O10 provide the progressive
numberof the next variable to be acquired. These
pinscan beused to select the next input to provide
on I0-I7 bus.

Stillinon-line modeO11allows toprovideapreset­tablesignal whichcan beusedasStart-Conversion
for an A/D converter after (about 400 ns) OFL or
BUSY fall.

Output Bus

(Output): In the Off-Line

5/28

W.A.R.P.2.0

FUNCTIONAL DESCRIPTION

W.A.R.P.2.0 works in two modedependingon the
OFL controlsignal level (see table 3) :

Off-line MODE (OFL High)
On-line MODE(OFL Low)

OFF-LINE MODE

All W.A.R.P. memories are loadedduring the Off­Line phase. The membershipfunctions are written
insidetheir relatedmemories andthe processcon­trol rules are loaded inside the PCM.
The addresses of the words to be written in the
memories, are internally generated while the ad­dresses of the external memory locations to be
readaredirectlyprovidedbyW.A.R.P.2.0bymeans
of O0-O11output pins.
Data must be loaded 8 bit a time in the data bus
and can be read from an external non volatile
memoryor loaded by an host processor.

Figure 4. Off-Linephase:Auto-Boot

Auto-Boot Enable

AUTO=HIGH

Off-linePhase Enable

OFL=HIGH

External Memory

Access Time SETTING

SIS0-SIS2=LowLow...

DownloadingFrom

External Memory

OFFLINEPHASE ENDS

ENDOFL=HIGH

The Off-Line phase can be performed automat­ically (see figure4) or manually(see figure 5).
When the auto-boot is chosen (AUTO = High)it is
possibleto configurethereadingaccesstimeof the
externalmemory. Theauto-bootendis indicatedby
the ENDOFLsignal.
The downloadingphase requires:

F*NWordsDatabaseclock pulses,
where F is 16 or 32 (see table 2).
NWordsDatabaseis the number of wordsstoredin

the boot-memory (see register bench description,
table 5).

When the manual-boot is chosen (AUTO = Low)
datahave to beprovidedby usingthe handshaking
signals (RD/READY). In this way it is possible to
updateonly aportionofthe databaseorchangethe
processorconfiguration.

The time required from the manual boot depends
on the efficiency of the communication handled
with the handshakingsignals.

OFLAUTO

HH

I0-I7

BOOT

MEMORY

O0-O11

W.A.R.P.2.0

SIS0-SIS2

ENDOFL

Figure 5. Off-LinePhase: Slave Downloading

Manual-Boot Enable

AUTO=LOW

Off-linePhase Enable

OFL=HIGH

Downloading with

Handshaking Signals

RD/READY

6/28

OFFLINE PHASE ENDS

BOOT

MEMORY

I0-I7

O0-O11

OFLAUTO

LH

W.A.R.P.2.0

READY

RD

W.A.R.P.2.0

ON-LINEMODE

In On-line mode (see figure 7) W.A.R.P.2.0 is en­abled to elaborate input values and calculate out­puts according to the fuzzy rules stored into the
microprogram. W.A.R.P.2.0 reads the inputvalues
one a time in the input data bus using the
RD/READY signals. If the processor is workingin
SLAVE mode (see register bench description in
table5) the user has toprovidethe inputswith their
identificationnumbers(bymeansofSIS0-SIS2),so
it is possible to provide inputs in any order. In
SLAVE mode it is also po ssible to force
W.A.R.P.2.0 to start the elaboration phase (by
means of LASTIN) without providing all inputs, for
instancewhen inputvariableschangewithdifferent
speed. In this case the outputs that have not be
providedin this cycle,but sampled in the previous
ones, are recoveredfrom the internalbuffers.

When all inputs are given or a LASTIN signal is
given, the elaboration phase starts. The elabora­tion phase is divided in two main parts. During the
first one the input values are read and the corre­spondingALPHAvalues(activationlevels)are cal­culated.In thesecond part the computation of the
fuzzy rules and the defuzzification are imple­mented.

W.A.R.P.2.0 acquires each input in 8 clock pulses
(min). Sincethe acquisition phase is performedby
the user by means of the handshaking signals, 8
clock pulses per input are referred to the most
efficient case. In figure 6 are shown the perform-

Figure6. W.A.R.P.2.0 performances

Numbe r of Clock Pu ls e s

8.000

6.000

4.000

2.000

0

0 64 128 192 256

Numbe r of Rule s

Numb er of I np u t s = 8

ances in case of 8 inputs. If you are using less
inputs you have to subtract 8 clock pulsesfor each
of them. The elaboration time for rule requires 32
clockpulses.

For instance if W.A.R.P.2.0 is working at a fre­quency of 40 MHz (25ns period)with 8 inputs and
128 rules globally(forall outputs) thetime required

to provide all outputs is 4000clkp*25ns= 100µs.

Figure7. On-Linephase

On-line Phase Master

(”MASTER”se t in the register ben ch)

CHIP PRESET

On-line Phase Enable

OFL=LOW

Inputs Acquisition with

Handshaking Signals

(RD/READY)

Elaboration P ha se

Outputs Gen eration

DS=HIGH

End of Acquisition Phase

Start Elaboration Pha se

On-line Pha se Slave

(”SLAVE” set in the register bench)

CHIP PRESET

On-line Phase Enable

OFL=LOW

Acquisition with

Hands haking by

specifying which inputs

is on the input bus by

means of SIS0-SIS2

Last Input has been

given

LASTIN=HIGH

Elaboration P hase

Outputs Ge neration

DS=HIGH

End of Acquisition Phase

Start Elaboration Pha se

7/28

W.A.R.P.2.0

Table 3. OperatingModes (1)

Mode PRESET OFL AUTO OE I0-I7 RD SIS0-SIS2 O0-O7 O8-O10 O11 OC0-OC1

Off-Line

Slave

Off-Line

Autoboot

On-Line
Master

On-Line

(3)

Slave

Output
Disable

Reset

Notes: 1. This table uses default active handshaking signal polarity (see table 6), X = don’t care.

2. If AUTO is High pulse in O11 is absent.

3. LASTIN and WAIT pulses are optional.

4. Same operation is obtained whenpositive and negative OFL transactions occour.

INTERNAL STRUCTURE

The blockdiagram shown in figure 2 describesthe
structure of W.A.R.P.2.0 (a more detailed block
diagramis shown in fig. 11).

Input Port. This internal block performs the input
datarouting.Dataareread onebytea timefrom the
input data bus, internally stored, and sent to the
ALPHA calculator following the rules loaded in the
ProgramMemory. Input data resolution is 8 bit.
The cycle starts when all inputs or a LASTIN High
have been provided and continues until BUSY is
active or a PRESET signal is given. When BUSY
becomesinactiveanewacquisitionphasecanstart.

V

IH

V

IH

V

(2)

(4)

IH

V

IH

V

IH

V

V

V

V

XXVILX X X Hi-Z X

XXXX X XVOLV

V

IH

V

IH

X

IL

X

IL

X Data In X X X X X

IL

Clock

V

IH

(2)

(2)

Data In X

IH

V

Data In X

IH

V

Data In

IH

Rate

Selection

Code

Input

Selection

rules can be only joined with the OR connective.
InferenceUnit structure is shown in figure9.

Defuzzifier. It generates the output crisp values
implementingthe consequentpart of the rules.

In thismethod consequentMFs are multiplied by a
weight value Ω (OMEGA), which is calculated on

the basis of antecedentMFsand logicaloperators.
The processing of fuzzy rules produces, for each

output variable, a resulting membership function.
Each MF related to the processed output variable
is firstly modifiedby arule weight.

Outputvalue (Y)isdeduced fromthe centroids(X
and the modified MFs (Ω

Alpha Calculator. This block calculates the inter­section (ALPHA weight) between an Antecedent
MembershipFunction and the correspondingcrisp
input (see figure 8).

InferenceUnit. Thanksto the Theta Operator,the
InferenceUnitgenerates theTHETA weightswhich
are used to manipulate the consequentMFs.

n

Ωi∗

∑

1

Y

=

n

Ω

∑

1

This is a calculation of the maximum and/or mini­mumperformed onALPHA values accordingto the
logical connectivesof fuzzy rules. It is possible to
utilize the AND/OR connectivesand to directly ex­ploit ALPHA weights or the negated values. The
numberof THETA weights depends onthe number
of rules.

The rules can have at maximum four ALPHA
weights(howevertheyareconnected).Twoormore

n = number of MFs of the Output Variable.
X

=absciss ofthe MFicentroid.

i

Ω

=membership degree of the output MFi.

i

Two parallel blocks calculate the numerator and
denominator values to implement the centroids
formula.A finaldivision blockcalculatestheoutput
values (see figure10).

External Memory

Addresses

Data

Out

Data

Out

X

i

i

X

(2)

(2)

OL

Output

Selection

Output

Selection

V

OL

Next
Input

X

V

OL

) byusing the formula:

i

)

i

8/28

W.A.R.P.2.0

Output Port. This block provides the output data

supported by handshaking signals. Ouput data
resolutionis 8 bit.
An output ready on the bus O0-O7 is indicated by
a DS pulse and by its identificationnumber (OC0­OC1). WAIT active temporarily stops the elabora­tionphaseallowingthesynchronizationwithslower
devices.

Programmable A/D output pulse. This block al­lowsto programthe widthof the pulse providedon
O11(only in On-Line mode)that can beused as a
StartConversion foran externalA/D. Thewidth of
this pulse can be configured by means of the
related register (see register bench description)
followingthe table 4.

Table 4. Start ConversionPulse (O11) Width
Setting.

Start conversion

Pulse Register

Low,Low, Low 128xT

Low,Low, High 256xT

Low,High, Low 2040xT

Low,High, High 4080xT

High, Low, Low 8160xT
High, Low, High 16320xT
High, High, Low 32000xT

High, High, High 65520xT

Pulse Width

(T

= MCLK Period)

CLK

CLK
CLK

CLK
CLK
CLK

CLK
CLK
CLK

9/28

W.A.R.P.2.0

Figure 8. ALPHACalculator Structure

INP UT ANTECEDENT MF

COMPAR ATOR

Figure 9. InferenceUnit Structure

44

Register Re gis te r

MIC RO

CODE

8

COMPARATOR

12 3 4

Register

8

MAX

TRUT H

LE VE L

ALP HAALP HAALPH A

44

Register

M AX/M IN

1212

M AX/M IN

M u lt ip li e rSu btractor

Adder

MUX
4

MUXMUX MUX

α

ALPH A

Selector

M AX/M IN

MAX/MIN

THETA

4

Figure 10.DefuzzifierStructure.

PROGRAM

ME MORY

10/28

X

i

8

Multip lie r

Ad de r

OMEGA

4

Divider

8

OUTPUT

Register

Ad de r

OMEGA

4

Figure11. DetailedBlock Diagram

L
F

Y
D

O

Y
BUS

END

A
RE

O7O6O5O4O3O2O1O0OC1OC0

O8O9

0
O1

1
O1

W.A.R.P.2.0

R

S
D

ER

COMP

2
1

D

S

ER

OA

OF

ORD

UMB

OL

W

N

T

OL

C

NTR

LOGI

O
C

T

D

I
A

NTR

I

NTW

I

Q
D

D

LK

NTR

C

I

3

MU X

Q
D

2
1

2

TU2

TU0

6
TI
4T I

2
TI
0
TI

M

16
K/

CL

ER
ST
GI

FROMRE

Q0Q1

PR

COUNTER

K
CL

M
PC

I
M

AD
T

TU3

TU1

7
TI
5

3TI
TI
1
TI

UX

32
K/

CL

NCH
BE

Q2

R

UNTE
O
C

PR

6

6

1

0

2

6

6

6

6

4
4

COUNTER

PR

2

DM
A

4

T

2

MUX

6

MUX

2

M
AD

T

M

4

4

PC

8

21

1

4

444

M
PC

I

Q
D

2

3

2
3

DM
A

Q
D

8

DE FUZ

0
1

I

NF UNIT

4

CALCULATOR

α

3

4

6

OFL

MUX

2

1

4

4

Q

D

88888888

Q
D

TU3TU0 TU1 TU2

8

UX

M

T

I
A

NTW

I

K
CL

Q0Q1Q2

D0D1D2

N

I
ST
LA

SIS2SIS1SIS0

O
UT

A

8

1

TI0TI

Q

PR

D

D
NTR

I

UX

M

OFL

MU X

RD

2
TI

Q

PR

D

I0I1I2I3I4I5I

ST
TE

3
TI

Q

PR

D

I

NP UT RE GISTER

Q

PR

D

8

4
TI

8888888
5
TI

Q

PR

D

Q

PR

D

6

TI6TI

7

I

7

Q

PR

D

Q

ST

R

D

S
S
V

OFL

OFL

Q

PR

D

Q

T
RS

D

S
S
V

COUNTER

PR

D

S
S

D

ET

V

V

ES
PR

LK
MC

T

I
A

W

O

11/28

W.A.R.P.2.0

MEMORY

There are three memories in W.A.R.P.2.0, the
Antecedent Memory (AM), The Program/Conse­quent Memory (PCM) and the Register Bench
(RB).
The AM is divided in 4 spaces, each having a
maximumof 64 bytes. It is also possible to divide
the AM in 8 parts, each having a maximum of 32
bytes.

It is possible to configure the AM in the following
modes (see fig.12):

a) up to 4 inputs, each with 16 Antecedent MFs
(MAX);

b) up to 8 inputs, each with 8 Antecedent MFs
(MAX);

Eachword (4 byte) of the AMcontains the data of
a single MF related to an input.If W.A.R.P.2.0has
been configured to accept up to 4 inputs it is

Figure12. AntecedentMemory Spaces.

64

Member ship

Functions
related to

INPUT 4

48

Member ship

Functions
related to

INPUT 3

32

Member ship

Functions
related to

INPUT 2

16

00

Member ship

Functions
related to

INPUT 1

16

0

possible to have up to 16 MFs for each input. If
W.A.R.P.2.0 hasbeen configuredtoaccept upto 8
inputs it is possible to haveup to 8 MFs for each
input. Each MF of the AM contains 3 (or 2) bit
indicating to which input variable the MF is corre­lated.

ThePCM is composed by 256 words (seefig. 13).
Each row (word) is related to a single rule and

contains36bitof microcodeand 8bit indicatingthe
consequent MF (crisp) related to this rule.

The RB contains data for the configuration of the
processorthat canbe set by software.
It is possible to fix:
the number of inputs, the number of outputs, the
address of the last word to load from the external
memory, the numberof MF per input, the width of
the start A/D conversion pulse, the handshaking
signals polarity and the functioning mode of the
processor(Master/Slave).

64

MFs related

to INPUT8

MFs related

to INPUT7

MFs related

to INPUT6

MFs related

to INPUT5

MFs related

to INPUT4

MFs related

to INPUT3

MFs related

to INPUT2

8

0

MFs related

to INPUT1

8

0

Figure13. Program/ConsequentMemory and Register Bench.

256

Microcod e Co nse que nt MFs

rela te d to RULE 256

4

Handshaking signals polarity

3

Antece dent Me mory Con figuration

2

A/D Sta rt Conversion Pulse width

On-Line ph ase Master/Slave

1

Numbe r of Words to lo ad from th e external

0

12/28

2

Microcod e Co nse que nt MFs

rela te d to RULE 2

1

Microcod e Co nse que nt MFs

rela te d to RULE 1

0

Numberof Inputs -1

Numbe r of Outputs - 1

Memory

Table 5. RegisterBench Description.

Register Name Resolution Function

Handshaking Signal Polarity

(ONLYduring the On-Line Phase)

Number of Inputs - 1 3 000-111 = 1 to 8 Inputs

Number of Outputs - 1 2 00 - 11= 1 to 4 Outputs

Antecedent Memory Configuration 1

A/D Conversion Pulse Width 3 see table 4

On-Line Phase Master/Slave 1

Number of Wordsto load from

theExternal Memory

Note: These Registers are configurable by means of the FUZZYSTUDIO 2.0.

8

12

W.A.R.P.2.0

0 active Low, 1 active High (default)
bit 0 READY
bit 1 RD
bit 2 WAIT
bit 3 DS
bit 4 BUSY
bit 5 LASTIN
bit 6 not connected
bit 7 START CONVERSION

0 = 8 Inputs, 8 MFs per Input
1 = 4 Inputs, 16 MFs per Input

0 = Slave Functioning
1 = Master Functioning

0000000000000-100110000100
from 0 to 2436 words to read

Table 6. DefaultActive HandshakingSignal Polarity

READY RD WAIT DS BUSY LASTIN START C ONVERSION (O11)

High High High High High High High

Note: Default polarities are used in the following timing diagrams

13/28

W.A.R.P.2.0

ABSOLUTEMAXIMUMRATINGS

Symbol Parameter Value Unit

V

DD

I

DD

I

OL

I

OH

T

OPT

Note: Stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating
sectionsof this specification is not implied. Exposure to Absolute Maximum Rating conditions forextended periods may affect
device reliability. Referalso to the SGS-THOMSON SURE Programand other relevant quality documents.

Table 7. RecommendedOperationConditions (1)

Symbol Parameter Min Typ Max Unit

V

DD

V

I

V

O

(2)

t

IR

(2)

t

IF

Notes: 1. Operating Condition: VDD=5V±5%-TA=0 °Cto70°C, unless otherwise specified.

2. See fig. 22.

Supply Voltage 4.75 5.0 5.25 V
Input Voltage 0 V
Ouput Voltage 0 V
Input Rise Time 40 ns
Input FallTime 40 ns

Supply Voltage -0.5 to 7 V
Supply Current 50 mA
Output Sink Peak Current +24 mA
Output Source Peak Current -12 mA
Operating Temperature 0 to +70 °C

DD
DD

V
V

DC ELECTRICAL CHARACTERISTICS

V

=5V±5% TA= 0 to +70 °C unless otherwisespecified.

DD

Symbol Parameter Condition Min Typ Max Unit

V

IL

V

IH

V

OL

V

OH

V

T+

V

T­(1)

I

IL

(1)

I

IH

(2)

I

IL

(2)

I

IH

I

OL

Notes: 1. All inputs with the except of OE and TEST.

2. Only OE and TEST inputs.

3. I

= -400µA,IOL= +16mA, T = +25°C.

OH

Low Level Input Voltage 0.8 V

High Level Input Voltage 2.0 V
Low Level Output Voltage 0.2 0.4 V
High Level Output Voltage 2.4 3.4 V

Schmitt trig. +ve Threshold see fig. 14 0.8 V
Schmitt trig. - ve Threshold see fig. 14 2.0 V

Low Level Leakage Input Current VI=V

High Level Leakage Input Current VI=V

Low Level Input Current VI=V

High Level Input Current VI=V

Tri-StateOutput Leakage Current VO=VSSor V

SS
DD
SS
DD

(3)
(3)
(3)
(3)

DD

-1 -2 nA

+4 nA

100 nA
160

±10 µA

µA

14/28

Figure14. TTL-levelinput Schmitt trigger characteristic.

5

4

3

V (V)

0

2

1

0.5 0.8 1.0 1.5 2.0 2.50

V (V)

I

V=5V

DD

T=25°C

A

(TYPICAL)

W.A.R.P.2.0

Figure15.

Input Pin Equivalent Circuit (1)

Figure 16. InputPin EquivalentCircuit (2)

Pull Down

V

DD

DEVICE
INPUT

R

S

R

PD

V

SS

V

SS

V

IN

C

IN

V

SS

V

0

DEVICE
INPUT

Note: 1. Only OE and TEST pins. Note: 1. All input pins except for OE and TEST.

V

DD

R

S

V

SS

V

IN

C

IN

V

SS

V

0

15/28

W.A.R.P.2.0

Figure17. EquivalentTristateOutput Circuit(1)

CONTROLSIGNAL

DEVICE
OUTPUT

C

OUT

V

SS

Figure 18. Equivalent Output Circuit (1)

DEVICE
OUTPUT

C

OUT

V

SS

Note: 1. Only O0-O11pins. Note: 1. All output pins except for O0-O11.

Table 8. EquivalentCircuit Parameters

Symbol Parameters Test Conditions Min Typ Max Unit

C

IN

C

OUT

R

S

R

PD

Input

Capacitance

Output

Capacitance

Stray Resistor 20 Ohm

Pull Down

Resistor

VI=0V

f = 1.0 MHz

VO = 0V

f = 1.0 MHz

VI=2V,VDD=5V

= 0.8V,VDD=5V

V

I

15 pF

15 pF

16K

13.6K

Ohm

Figure19. AC TestCircuit (1)

V

DD

DEVICE

VDD

D.U.T.

OUT PUT

VSS

V

DD

R

L2

R

L1

C

L

INCLUDING
PRO BE
CA PACITANCE

Figure 20. AC Test Circuit (1)

DEVICE
OUTPUT

D.U.T.

VSS

R

L

C

Note: 1. Only O0-O11pins. Note: 1. All output pins except for O0-O11.

16/28

INCLUDING
PROBE

L

CAPACITANCE

AC ELECTRICAL CHARACTERISTICS

=5V±5% TA=0 to +70°C unless otherwisespecified.

V

DD

W.A.R.P.2.0

Figure21. Data Input Timing

Data

Clock

t

50%

50%

t

CLL

t

CLH

SETtHLD

50%

t

CP

Table 9. Timing Parameters

Symbol Parameters

t

CLH

t

CLL

t

SET

t

HLD

t

t

OR
OF

Clock High 10 ns

Clock Low 15 ns

Setup 15 ns

Hold 15 ns

Output Rise seefig.22 3 ns

Output Fall seefig.22 3 ns

Test

Conditions

V
V

V
V

V
V

Figure 22. Input/OutputRise & Fall Times

DD

INPUT

SS

DD

OUTPUT

10% 10%

t

IF IR

90%90%

t

SS
DD

OR OF

SS

Min Typ Max Unit

90%90%

5V

0V

3.2V

10%10%

0.1V

tt

Test ConditionsMCLK frequency= 40MHz, T = +25°C.

17/28

W.A.R.P.2.0

OFF-LINE SLAVE DOWNLOADINGPHASE TIMING

AUTO

OFL

I0-I7

INP0 INP 1 INP 2 INP N

RD

READY

T

T

2

1

T

T

3

2

T

T

3

2

T

2

Table 10. Off-LineSlave Timing Parameters

Symbol Mode Parameter Min Typ Max Unit

T

1

T

2

T

3

Off-Line

Slave

Off-Line

Slave

Off-Line

Slave

OFL High to first RD

High

RD High to

READY High

READY Low to

RD High

3

4

3

Figure 23. Off-LineSlave Typical Application

Clock

Pulses

Clock

Pulses

Clock

Pulses

18/28

A9-A16

RD/WR

micro

READY

AD0-AD7

AS

ADDRESS

DECODE

ADDRESS BUS

HIGH

8

DATABUS

MCLK
OE
OFL

AUTO

PRESET

RD

READY

W.A.R.P. 2.0

BUSY

I0-I7

8

DS

8

OFF-LINE AUTO-BOOT PHASE TIMING

AUTO

OFL

W.A.R.P.2.0

I0-I7

O0-O11

INP 0 INP 1

ADDR 0

ADDR 1 ADDR N

INP N

READY

ENDOFL

T

1T2

T

3

T

3

Table 11. Off-LineAuto-Boot Timing Parameters

Symbol Mode Parameter Min Typ Max Unit

T

1

T

2

(1)

T

3

Note: 1. see Table 2.

Off-Line

Auto-Boot

Off-Line

Auto-Boot

Off-Line

Auto-Boot

OFL High

to Address Valid

Address Valid

to Input Sampling

Address Valid

to next Address Valid

3

8

16 32

Clock

Pulses

Clock

Pulses

Clock

Pulses

Figure24. Off-LineAuto-Boot typicalApplication

HIGH

LOW

HIGH

8

DATA

OE

OUT

ADDRESS
INPUT

MEMORY

se e table 2

12

MCLK
OFL

AUTO
OE
PRE SET

I0-I7

W.A.R.P. 2.0

SIS0-SIS 2

READY
ENDOFL

O0-O11

19/28

W.A.R.P.2.0

ON-LINESLAVEPHASE TIMING

OFL

I0-I7

SIS0-SIS2

LASTIN

RD

READY

WAIT

BUSY

DS

O0-O7

INP 0 INP 1

ADDR 0 ADDR 1 ADDR N-1 ADDR N

T

1

T2T

3

INP N-1

INP N

T4T

T

6

5

T

8

OUT 0 OUT 1 OUT N-1

T

8

T

7

T

9

OUT N

Table 12. On-LineSlave Timing Parameters

Symbol Mode Parameter Min Typ Max Unit

T

1

T

2

T

3

T

4

(1)

T

5

T

6

T

7

T

8

T

9

On-Line

Slave

On-Line

Slave

On-Line

Slave

On-Line

Slave

On-Line

Slave

On-Line

Slave

On-Line

Slave

On-Line

Slave

On-Line

Slave

Note 1.T7 depends on the number of rules related to the current output variable. Each output variable needs at least
two rules and each rule requires 32 clock pulses.

20/28

OFL Low

to first RD High

3

RD High

to READY High

READY High

to next RD High

5

Last RD High

to BUSY High

BUSY High

to first Output Ready

Elaboration

Time

64

see fig.6

WaitLow

to nextOutput Valid

DS Pulse Width 5

LAST DS Pulse Width 1

10

Clock

Pulses

2

Clock

Pulses

Clock

Pulses

Clock

Pulses

Clock

Pulses

Clock

Pulses

32

Clock

Pulses

Clock

Pulses

Clock

Pulses

ON-LINE SLAVETYPICAL APPLICATION

A9-A16

AS

RD/WR

ADDRESS

DECODE

micro

READY

AD0-AD7

ADDRESSBUS

OE

3

DATA

REGISTER

DATA BUS

MCLK

OE
OFL
AUTO

PRESETHIGH
RD

W.A.R.P. 2.0

WAIT

LASTIN

3

SIS0-SIS2

8

I0-I7

W.A.R.P.2.0

8

READY

DS

8

O0-O7

BUSY

21/28

W.A.R.P.2.0

ON-LINEMASTER PHASE TIMING

OFL

I0-I7

INP 0 INP 1

INPN

RD

READY

T

4

T

5

WAIT

BUSY

DS

O0-O10

T

6

T

10

T

7

OUT 0 OUT 1 OUT N

T

9

T

10

OUT N-1

T

8

T

11

T

3

O11

OC0-OC1

ADDR0

T

T

2

1

T

3

ADDR 1 ADDRN

ADDRN-1

Table 13. On-LineMaster TimingParameters

Symbol Mode Parameter Min Typ Max Unit

T

1

T

2

T

3

T

4

T

5

(1)

T

6

(1)

T

7

T

8

T

9

T

10

T

11

On-Line

Master

On-Line

Master

On-Line

Master

On-Line

Master

On-Line

Master

On-Line

Master

On-Line

Master

On-Line

Master

On-Line

Master

On-Line

Master

On-Line

Master

OFL Low

to first RD High

3

RD High

to READY High

OFL/BUSY Low

to O11 Pulse

RD High

to next RD High

READY High

to BUSY High

BUSY High

to first Output Ready

DS High

to next DS High

64

64

WAIT Low

to nextOutput Valid

Elaboration

Time

see fig.6

DS Pulse Width 5

LAST DS Pulse Width 1

2

10

10

1

32

Clock

Pulses

Clock

Pulses

Clock

Pulses

Clock

Pulses

Clock

Pulses

Clock

Pulses

Clock

Pulses

Clock

Pulses

Clock

Pulses

Clock

Pulses

Clock

Pulses

Note 1.It depends on the number of rules related to the current output variable. Each output variable needs at least two
rules and each rulerequires 32 clock pulses.

22/28

ON-LINE MASTER TYPICAL APPLICATION

CS

ANALOG
INPUTS

DATA

INPUT
SELECT

RD

MULTIPLE A/D

ANALOG
OUTPUTS

MULTIPLE D/A

CONVERTER

OUT

CONVERTER

CS

DATA

IN
WR

OUT SELECT

INT

W.A.R.P.2.0

MCLK
OFL

LOW
LOW
HIGH

8

3

128

2

AUTO
OE
PRES ET

I0-I7

W.A.R.P . 2. 0

RD

READY
ENDOFL

OC0-OC1

DS

O0-O11

23/28

W.A.R.P.2.0

PROGRAMMING TOOLS

Figure 25. FUZZYSTUDIO2.0 Block Diagram

BASICTOOLS

EDITORS

SUPPORT
TOOLS

IMPORTER

EXPORTER

HIGHLEVEL

SUPPORT TOOLS

AFM

AdaptiveFuzzy Modeller

EMULATORS

ANSI C

MATLAB

COMPILER

FUZZYSTUDIO2.0

BOARD

MANAGER

RS232

DEBUGGER

FUZZYSTUDIO2.0

SGS-THOMSON has developed a software tools
to support the use of W.A.R.P.2.0 allowing easy
configurating and loading of the memories and
functionalsimulations.
It has been designed in order to be used with the
followinghardware/softwarerequirements:

80386 (or higher) processor
VGA / SVGA screen
WindowsVersion3.0 or Higher

The constituting blocks are:
Editors

it is a tool to define the fuzzy controller with a
User-Friendly Interface.
It is composed by:

– VariablesEditor: to define the I/O variables,

and to draw relatedmembershipfunctions.

– Rule Editor (to definethe base of knowledge)

Compiler

it generatesthe code to be loaded in W.A.R.P.2.0
memories according to the data defined through
the editor. It also generates the data base for
Debugger,Exporterand Simulator.

FUZZYSTUDIOADB2.0

ApplicationDevelopment Board

W.A.R.P.

Debugger

it allowsthe user toexaminestep-by-stepthe fuzzy
computationfor a definedapplication.It also allows
to checkthe results of theentire controlprocess by
using a list of patterns stored into a file.

Exporter

it generatesfilesto beimported indifferentenviron­mentsinorderto developW.A.R.P.2.0basedsimu­lations exploitinguser-developedmodels.
It addresses the followingenvironments:
Standard C: the exporter generates C functions
that can be recalled by an user program
MATLAB:the exportergeneratesa’.M’ filethat can
be used to perform simulations in MATLAB envi­ronments

Importer

It allowsto usea fuzzy projecteditedby adevelop­ment system of a different hardware device, i.e.
W.A.R.P.3 family, or by the AFM.

Board Manager

It allows the W.A.R.P.2.0 and ZEROPOWER pro­gramming, board testing and project debugging
directly on the silicon.

24/28

W.A.R.P.2.0

FUZZYSTUDIOADB2.0 DESCRIPTION

The board has been designed to be connected to
the RS232 port of an IBM PC 386 (or higher), but
it can also work stand alone.

It can manage up to 8 digital inputs and 4
digital outputs.

Inputs and outputs are provided at TTL com­patible level. The board allows the user to
charge the rules and the membership functions
(see FUZZYSTUDIO 2.0 User Manual) into
the W.A.R.P.2.0 memories.

Figure26. FUZZYSTUDIOADB2.0 BoardLayout

The clockgenerator frequencyon board is 8 MHz.
An automatic trigger is used to synchronize
W.A.R.P.2.0 with the external environment
(working connected with a PC).

Whenthe boardis used deconnectedfroma PC all
the fuzzy data (membership functions and rules)
are stored in a ZEROPOWERSRAM.

Tab. 14 OrderingInformation

Order Code Device

STFLSTUDIO2/KIT STFLWARP20/PL

Development Tools

FUZZYSTUDIOADB2.0 SW Tools

W.A.R.P.2.0
W.A.R.P.2.0programmer
ZEROPOWER programmer
RS-232 communication handler
Internal Clock

Variables and Rules Editor
W.A.R.P.2.0Compiler/Debugger
Exporter for ANSI C andMATLAB
Importer from AFM



25/28

W.A.R.P.2.0

AdaptiveFuzzy Modeller

AdaptiveFuzzy Modeller(AFM)is a tool thateasily
allows to obtain a model of a system based on
FuzzyLogic data structure, starting from the sam­pling of a process/function expressed in terms of
Input\Outputvalues pairs (patterns).

Its primary capabilityis theautomaticgenerationof
a database containing the inference rules and the
parametersdescribing the membership functions.
The generated Fuzzy Logic knowledge base rep­resents an optimized approximation of the proc­ess/functionprovidedas input.

The AFM has the capabilityto translate its project
files to FUZZYSTUDIO project files, MAT­LAB and C code, in orderto use thisenvironment
as a support for simulationand control .

The blockdiagram illustrates the AFMdesign flow.

SUPPORTED TARGETS

The supportedenvironmentare:

- W.A.R.P. 1.1 using FUZZYSTUDIO1.0

- W.A.R.P.2.0 using FUZZYSTUDIO 2.0

- MATLAB

- C Language

- Fu.L.L. (FuzzyLogic Language).

SYSTEM REQUIREMENTS

MS-DOSversion 3.1or higher
Microsoft Windows 3.0 or compatiblelater version
486, PENTIUMcompatibleprocessor chip
8 MBytes RAM (16 Mbytes recommended)
Hard Disk with at least 1MBytes free space

Figure 27. AFM Design Flow

patternfile

Fuzzy Logic

Learning

Phases

Rules

extractor

MFs

tuning

knowledge base

Simulation

and Manual

Tuning

rules

minimizer

exporterto

processor

W.A.R.P.1.1
W.A.R.P.2.0

ANSIC

MATLAB

Table 15. OrderingInformation

Order Code Description Supported Target Functionalities System Requirement

Rules Minimizer
Step-by-Step Simulation
Simulation from File
Local Tuning

MS-DOS 3.1or higher
Windows 3.0 or later
486, PENTIUM compatible
8 MB RAM

STFLAFM10/SW

26/28

WTA-FAMfor Building Rules
BACK-FAMfor Building MFs

STFLWARP11/PG
STFLWARP11/PL
STFLWARP20/PL
ANSI C
MATLAB



PACKAGEDIMENSIONS

W.A.R.P.2.0

Dim.

A 25.02 25.27 0.985 0.995
B 24.13 24.33 0.950 0.958

D 4.20 5.08 0.165 0.200
d1 2.54 0.100
d2 0.56 0.022

E 22.61 23.62 0.890 0.930
e 1.27 0.050

F 0.38 0.015
G 0.10 0.004
M 1.27 0.050

M1 1.14 0.044

Min. Typ. Max. Min. Typ. Max.

mm inches

Figure28. W.A.R.P.2.0 PLCC68 Package

Table 16. OrderingInformation

PartNumber Maximum Frequency Supply Voltage Temperature Range Package

STFLWARP20/PL 40 MHz

5±5%

0 °Cto70°C PLCC68

27/28

W.A.R.P.2.0

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from itsuse. No
license is granted by implication or otherwise under any patentor patent rights of SGS-THOMSON Microelectronics. Specification mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products arenotauthorized foruse as critical componentsin life support devices orsystems without express
written approval of SGS-THOMSON Microelectronics.

 1996 SGS-THOMSON Microelectronics – Printed in Italy– All Rights Reserved

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