Datasheet W9864G6DB Datasheet (Winbond Electronics)

W9864G6DB

1M × 4 BANKS × 16 BITS SDRAM

Table of Contents-

1. GENERAL DESCRIPTION.................................................................................................................. 3

2. FEATURES ......................................................................................................................................... 3

3. AVAILABLE PART NUMBER.............................................................................................................. 3

4. PIN CONFIGURATION ....................................................................................................................... 4

5. PIN DESCRIPTION............................................................................................................................. 5

6. BLOCK DIAGRAM .............................................................................................................................. 6

7. FUNCTIONAL DESCRIPTION............................................................................................................ 7

Power Up and Initialization................................................................................................................ 7

Programming Mode Register ............................................................................................................ 7

Bank Activate Command................................................................................................................... 7

Read and Write Access Modes......................................................................................................... 7

Burst Read Command....................................................................................................................... 8

Burst Command ................................................................................................................................ 8

Read Interrupted by a Read.............................................................................................................. 8

Read Interrupted by a Write .............................................................................................................. 8

Write Interrupted by a Write .............................................................................................................. 8

Write Interrupted by a Read .............................................................................................................. 8

Burst Stop Command........................................................................................................................ 8

Addressing Sequence of Sequential Mode....................................................................................... 9

Addressing Sequence of Interleave Mode ........................................................................................ 9

Auto Precharge Command.............................................................................................................. 10

Precharge Command ...................................................................................................................... 10

Self Refresh Command................................................................................................................... 10

Power Down Mode.......................................................................................................................... 10

No Operation Command ................................................................................................................. 11

Deselect Command......................................................................................................................... 11

Clock Suspend Mode ...................................................................................................................... 11

Table of Operating Modes............................................................................................................... 12

Simplified State Diagram................................................................................................................. 13

8. DC CHARACTERISTICS .................................................................................................................. 14

Absolute Maximum Rating .............................................................................................................. 14

Recommended DC Operating Conditions....................................................................................... 14

Capacitance .................................................................................................................................... 14

Publication Release Date: January 27, 2003

- 1 - Revision A1

W9864G6DB

DC Characteristics .......................................................................................................................... 15

9. AC CHARACTERISTICS .................................................................................................................. 16

10. TIMING WAVEFORMS ................................................................................................................... 19

Command Input Timing................................................................................................................... 19

Read Timing .................................................................................................................................... 20

Control Timing of Input Data ........................................................................................................... 21

Control Timing of Output Data ........................................................................................................ 22

Mode Register Set Cycle ................................................................................................................ 23

11. OPERATING TIMING EXAMPLE....................................................................................................24

Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) ........................................................ 24

Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto Precharge) ............................. 25

Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) ........................................................ 26

Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto Precharge) ............................. 27

Interleaved Bank Write (Burst Length = 8)...................................................................................... 28

Interleaved Bank Write (Burst Length = 8, Auto Precharge) .......................................................... 29

Page Mode Read (Burst Length = 4, CAS Latency = 3)................................................................. 30

Page Mode Read/Write (Burst Length = 8, CAS Latency = 3) ....................................................... 31

Auto Precharge Read (Burst Length = 4, CAS Latency = 3) .......................................................... 32

Auto Precharge Write (Burst Length = 4)........................................................................................ 33

Auto Refresh Cycle ......................................................................................................................... 34

Self Refresh Cycle........................................................................................................................... 35

Bust Read and Single Write (Burst Length = 4, CAS Latency = 3)................................................. 36

Power Down Mode.......................................................................................................................... 37

Auto Precharge Timing (Write Cycle) .............................................................................................38

Auto Precharge Timing (Read Cycle) ............................................................................................. 39

Timing Chart of Read to Write Cycle............................................................................................... 40

Timing Chart of Write to Read Cycle............................................................................................... 41

Timing Chart of Burst Stop Cycle (Burst Stop Command).............................................................. 42

Timing Chart of Burst Stop Cycle (Precharge Command).............................................................. 43

CKE/DQM Input Timing (Write Cycle)............................................................................................. 44

CKE/DQM Input Timing (Read Cycle) ............................................................................................ 45

Self Refresh/Power Down Mode Exit Timing .................................................................................. 46

12. PACKAGE DIMENSIONS ............................................................................................................... 47

BGA 60 Balls Pitch = 0.65 mm........................................................................................................ 47

13. VERSION HISTORY ....................................................................................................................... 48

- 2 -

W9864G6DB

1. GENERAL DESCRIPTION

W9864G6DB is a high-speed synchronous dynamic random access memory (SDRAM), organized as
1M words × 4 banks × 16 bits. Using pipelined architecture and 0.175 µm process technology,
W9864G6DB delivers a data bandwidth of up to 286M bytes per second (-7).

W9864G6DB -7.

Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.

By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9864G6DB is ideal for main memory in
high performance applications.

2. FEATURES

• 2.7V − 3.6V power supply

• 1048576 words × 4 banks × 16 bits organization

• Self refresh current: Standard and low power

• CAS latency: 2 and 3

• Burst Length: 1, 2, 4, 8, and full page

• Sequential and Interleave burst

• Burst read, single write operation

• Byte data controlled by DQM

• Power-down Mode

• Auto-precharge and controlled precharge

• 4K refresh cycles/ 64 mS

• Interface: LVTTL

• Packaged in BGA 60 balls pitch = 0.65 mm, using PB free materials

3. AVAILABLE PART NUMBER

PART NUMBER SPEED (CL = 3) SELF REFRESH CURRENT (MAX.)

W9864G6DB-7 143 MHz 1 mA

Publication Release Date: January 27, 2003

- 3 - Revision A1

4. PIN CONFIGURATION

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A8A

A

A

A

A

A

A

A

A0A

W9864G6DB

1

VSS

DQ14

DQ13

DQ12

DQ10

DQ9

DQ8

NC

NC

NC

CKE

11

8

B

C

D

E

F

G

H

J

K

L

M

N

Top View

DQ15

VSSQ

VDDQ

DQ11

VSSQ

VDDQ

NC

VSS

UDQM

CLK

NC

VDDQ

VSSQ

VDDQ

VSSQ

LDQM

RAS#

9

7

DQ0

DQ4

NC

VDD

NC

BS1

0

762

VDD

DQ1

DQ2

DQ3

DQ5

DQ6

DQ7

NC

WE#

CAS#

CS#

BS0

10

VDD

DQ1

DQ2

DQ3

DQ5

DQ6

DQ7

NC

WE#

CAS#

CS#

BS0

10

Bottom View

7 6 2 1

DQ0

VDDQ

VSSQ

DQ4

VDDQ

VSSQ

NC

VDD

LDQM

RAS#

NC

BS1

DQ15

VSSQ

VDDQ

DQ11

VSSQ

VDDQ

NC

VSS

UDQM

CLK

NC

9

7

VSS

DQ14

DQ13

DQ12

DQ10

DQ9

DQ8

NC

NC

NC

CKE

11

P

R

6

VSS

5

4

2

3

1

VDD

- 4 -

1

VDD

2

3

5

4

6

VSS

5. PIN DESCRIPTION

BALL LOCATION PIN NAME FUNCTION DESCRIPTION

Multiplexed pins for row and column address. Row

M1, M2, N1, N2,

N6, N7, P1, P2,

P6, P7, R6,

M6, M7 BS0, BS1 Bank Select

A2, A6, B1, B7,
C1, C7, D1, D2,
D6, D7, E1, E7,

F1, F7, G1, G7

L7

K6

K7

A0 − A11

DQ0 −

DQ15

CS

RAS

CAS

Data Input/

Chip Select

Row Address

Address

Output

Strobe

Column

Address

Strobe

address: A0 − A11. Column address: A0 − A7.
A10 is sampled during a precharge command to
determine if all banks are to be precharged or bank
selected by BS0, BS1.

Select bank to activate during row address latch time,
or bank to read/write during address latch time.

Multiplexed pins for data output and input.

Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.

Command input. When sampled at the rising edge of
the clock

operation to be executed.

Referred to

RAS , CAS and WE define the

RAS

W9864G6DB

J7

J6, J5

K2 CLK Clock Inputs

L1 CKE Clock Enable

A7, H6, R7 VDD Power (+3.3V) Power for input buffers and logic circuit inside DRAM.

A1, H2, R1 VSS Ground

B6, C2, E6, F2 VDDQ

B2, C6, E2, F6 VSSQ

G2, G6, H1, H7,

J1, K1, L2, L6

- 5 - Revision A1

WE

UDQM

LDQM

NC No Connection No connection

Write Enable

Input/Output

Mask

Power (+3.3V)

for I/O Buffer

Ground for I/O

Buffer

Referred to

The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.

System clock used to sample inputs on the rising
edge of clock.

CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.

Ground for input buffers and logic circuit inside
DRAM.

Separated power from V
immunity.

Separated ground from V
immunity.

RAS

DD, to improve DQ noise

SS, to improve DQ noise

Publication Release Date: January 27, 2003

6. BLOCK DIAGRAM

W9864G6DB

CLK

CKE

RAS

CAS

WE

A10

BS0

BS1

CLOCK

BUFFER

CS

COMMAND

DECODER

A0

A9

ADDRESS

REFRESH

COUNTER

BUFFER

CONTROL

GENERATOR

MODE
REGISTER

COLUMN

COUNTER

SIGNAL

COLUMN DECODER

CELL ARRAY

BANK #0

ROW DECODER

SENSE AMPLIFIER

DATA CONTROL

CIRCUIT

COLUMN DECODER

CELL ARRAY

BANK #1

ROW DECODERROW DECODER

SENSE AMPLIFIER

DQ
BUFFER

DQ0

DQ15

UDQM
LDQM

COLUMN DECODER

CELL ARRAY

BANK #2

ROW DECODER

SENSE AMPLIFIER

NOTE:

The cell array configuration is 2048 * 256 * 32

- 6 -

COLUMN DECODER

CELL ARRAY

BANK #3

SENSE AMPLIFIER

W9864G6DB

7. FUNCTIONAL DESCRIPTION

Power Up and Initialization

The default power up state of the mode register is unspecified. The following power up and
initialization sequence need to be followed to guarantee the device being preconditioned to each user
specific needs.

During power up, all V
when the input signals are held in the "NOP" state. The power up voltage must not exceed VDD +0.3V
on any of the input pins or V
followed by a precharge of all banks using the precharge command. To prevent data contention on
the DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial
pause period. Once all banks have been precharged, the Mode Register Set Command must be
issued to initialize the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required
before or after programming the Mode Register to ensure proper subsequent operation.

Programming Mode Register

After initial power up, the Mode Register Set Command must be issued for proper device operation.
All banks must be in a precharged state and CKE must be high at least one cycle before the Mode
Register Set Command can be issued. The Mode Register Set Command is activated by the low

signals of
during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A
new command may be issued following the mode register set command once a delay equal to t
elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.

RAS , CAS , CS and WE at the positive edge of the clock. The address input data

DD and VDDQ pins must be ramp up simultaneously to the specified voltage

DD supplies. After power up, an initial pause of 200 µS is required

RSC has

Bank Activate Command

The Bank Activate command must be applied before any Read or Write operation can be executed.
The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate
command is applied to when the first read or write operation can begin must not be less than the RAS
to CAS delay time (t
Activate command can be issued to the same bank. The minimum time interval between successive
Bank Activate commands to the same bank is determined by the RAS cycle time of the device (t
The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice
versa) is the Bank to Bank delay time (t
specified as TRAS (max.).

RCD). Once a bank has been activated it must be precharged before another Bank

RC).

RRD). The maximum time that each bank can be held active is

Read and Write Access Modes

After a bank has been activated, a read or write cycle can be followed. This is accomplished by setting

RAS high and CAS low at the clock rising edge after minimum of tRCD delay. WE pin voltage level

defines whether the access cycle is a read operation (
address inputs determine the starting column address. Reading or writing to a different row within an
activated bank requires the bank be precharged and a new Bank Activate command be issued. When
more than one bank is activated, interleaved bank Read or Write operations are possible. By using the
programmed burst length and alternating the access and precharge operations between multiple
banks, seamless data access operation among many different pages can be realized. Read or Write
Commands can also be issued to the same bank or between active banks on every clock cycle.

- 7 - Revision A1

WE high), or a write operation ( WE low). The

Publication Release Date: January 27, 2003

W9864G6DB

Burst Read Command

The Burst Read command is initiated by applying logic low level to CS and CAS while holding

RAS and WE high at the rising edge of the clock. The address inputs determine the starting column

address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst
length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page
explain the address sequence of interleave mode and sequence mode.

Burst Command

The Burst Write command is initiated by applying logic low level to CS , CAS and WE while
holding

address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle
that the Write Command is issued. The remaining data inputs must be supplied on each subsequent
rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes
will be ignored.

Read Interrupted by a Read

A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted,
the remaining addresses are overridden by the new read address with the full burst length. The data
from the first Read Command continues to appear on the outputs until the CAS latency from the
interrupting Read Command the is satisfied.

RAS high at the rising edge of the clock. The address inputs determine the starting column

Read Interrupted by a Write

To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output
drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will
issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the
DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM
masking is no longer needed.

Write Interrupted by a Write

A burst write may be interrupted before completion of the burst by another Write Command. When the
previous burst is interrupted, the remaining addresses are overridden by the new address and data
will be written into the device until the programmed burst length is satisfied.

Write Interrupted by a Read

A Read Command will interrupt a burst write operation on the same clock cycle that the Read
Command is activated. The DQs must be in the high impedance state at least one cycle before the
new read data appears on the outputs to avoid data contention. When the Read Command is
activated, any residual data from the burst write cycle will be ignored.

Burst Stop Command

A Burst Stop Command may be used to terminate the existing burst operation but leave the bank
open for future Read or Write Commands to the same page of the active bank, if the burst length is full
page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop

- 8 -

W9864G6DB

Command is defined by having
the clock. The data DQs go to a high impedance state after a delay, which is equal to the CAS
Latency in a burst read cycle, interrupted by Burst Stop. If a Burst Stop Command is issued during a
full page burst write operation, then any residual data from the burst write cycle will be ignored.

RAS and CAS high with CS and WE low at the rising edge of

Addressing Sequence of Sequential Mode

A column access is performed by increasing the address from the column address which is input to
the device. The disturb address is varied by the Burst Length as shown in Table 2.

Table 2 Address Sequence of Sequential Mode

DATA ACCESS ADDRESS BURST LENGTH

Data 0 n BL = 2 (disturb address is A0)

Data 1 n + 1 No address carry from A0 to A1

Data 2 n + 2 BL = 4 (disturb addresses are A0 and A1)

Data 3 n + 3 No address carry from A1 to A2

Data 4 n + 4

Data 5 n + 5 BL = 8 (disturb addresses are A0, A1 and A2)

Data 6 n + 6 No address carry from A2 to A3

Data 7 n + 7

Addressing Sequence of Interleave Mode

A column access is started in the input column address and is performed by inverting the address bit
in the sequence shown in Table 3.

Table 3 Address Sequence of Interleave Mode

DATA ACCESS ADDRESS BUST LENGTH

Data 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 BL = 2

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6

Data 7

- 9 - Revision A1

A8 A7 A6 A5 A4 A3 A2 A1

A8 A7 A6 A5 A4 A3 A2

A8 A7 A6 A5 A4 A3 A2

A8 A7 A6 A5 A4 A3

A8 A7 A6 A5 A4 A3

A8 A7 A6 A5 A4 A3

A8 A7 A6 A5 A4 A3

A2 A1 A0

A2 A1 A0

A2 A1 A0

A2 A1 A0

A0

A1 A0

A1 A0

Publication Release Date: January 27, 2003

BL = 4

BL = 8

W9864G6DB

Auto Precharge Command

If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is
entered. During auto-precharge, a Read Command will execute as normal with the exception that the
active bank will begin to precharge automatically before all burst read cycles have been completed.
Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled
burst cycle. The number of clocks is determined by CAS latency.

A Read or Write Command with auto-precharge cannot be interrupted before the entire burst
operation is completed for the same bank. Therefore, use of a Read, Write, or Precharge Command is
prohibited during a read or write cycle with auto-precharge. Once the precharge operation has started,
the bank cannot be reactivated until the Precharge time (t
Precharge command is illegal if the burst is set to full page length. If A10 is high when a Write
Command is issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically
enters the precharge operation one clock delay from the last burst write cycle. This delay is referred to
as write t

DPL. The bank undergoing auto-precharge cannot be reactivated until tDPL and tRP are satisfied.

This is referred to as tDAL, Data-in to Active delay (tDAL = tDPL + tRP). When using the Auto-precharge
Command, the interval between the Bank Activate Command and the beginning of the internal
precharge operation must satisfy t

RAS (min).

Precharge Command

RP) has been satisfied. Issue of Auto-

The Precharge Command is used to precharge or close a bank that has been activated. The
Precharge Command is entered when

CS , RAS and WE are low and CAS is high at the rising

edge of the clock. The Precharge Command can be used to precharge each bank separately or all
banks simultaneously. Three address bits, A10, BS0, and BS1 are used to define which bank(s) is to
be precharged when the command is issued. After the Precharge Command is issued, the precharged
bank must be reactivated before a new read or write access can be executed. The delay between the
Precharge Command and the Activate Command must be greater than or equal to the Precharge time
(t

RP).

Self Refresh Command

The Self Refresh Command is defined by having CS , RAS , CAS and CKE held low with WE
high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command.
Once the command is registered, CKE must be held low to keep the device in Self Refresh mode.
When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are
disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will
exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the
device exits Self Refresh Operation and before the next command can be issued. This delay is equal
to the t

AC cycle time plus the Self Refresh exit time.

If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly
distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and
just after exiting the self refresh mode.

Power Down Mode

The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are
gated off to reduce the power. The Power Down mode does not perform any refresh operations,
therefore the device can not remain in Power Down mode longer than the Refresh period (t

REF) of the

device.

- 10 -

W9864G6DB

The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation
Command is required on the next rising clock edge, depending on t
enabled with CKE held high for a period equal to t

CES (min.) + tCK (min.).

No Operation Command

The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to
prevent the SDRAM from registering any unwanted commands between operations. A No Operation

Command is registered when
the clock. A No Operation Command will not terminate a previous operation that is still executing,
such as a burst read or write cycle.

CS is low with RAS , CAS , and WE held high at the rising edge of

Deselect Command

The Deselect Command performs the same function as a No Operation Command. Deselect
Command occurs when

cares.

CS is brought high, the RAS , CAS , and WE signals become don't

Clock Suspend Mode

During normal access mode, CKE must be held high enabling the clock. When CKE is registered low
while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode
deactivates the internal clock and suspends any clocked operation that was currently being executed.
There is a one clock delay between the registration of CKE low and the time at which the SDRAM
operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are
issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay
from when CKE returns high to when Clock Suspend mode is exited.

CK. The input buffers need to be

Publication Release Date: January 27, 2003

- 11 - Revision A1

W9864G6DB

Table of Operating Modes

Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 1 shows the truth table for the operation commands.

TABLE 1 TRUTH TABLE (Note (1), (2))

COMMAND

Bank Active Idle H x x v v V L L H H

Bank Precharge Any H x x v L x L L H L

Precharge All Any H x x x H x L L H L

Write Active (3) H x x v L v L H L L

Write with Auto Precharge Active (3) H x x v H v L H L L

Read Active (3) H x x v L v L H L H

Read with Auto Precharge Active (3) H x x v H v L H L H

Mode Register Set Idle H x x v v v L L L L

No-Operation Any H x x x x x L H H H

Burst Stop Active (4) H x x x x x L H H L

Device Deselect Any H x x x x x H x x x

Auto Refresh Idle H H x x x x L L L H

Self Refresh Entry Idle H L x x x x L L L H

Self Refresh Exit

Clock Suspend Mode
Entry

Power Down Mode Entry

Clock Suspend Mode Exit Active L H x x x x x x x X

Power Down Mode Exit

Data Write/Output Enable Active H x L x x x x x x x

Data Write/Output Disable Active H x H x x x x x x x

Notes:

(1) v = valid, x = Don't care, L = Low Level, H = High Level

(2) CKEn signal is input leve l when commands are provided.

(3) These are state of bank designated by BS0, BS1 signals.

(4) Device state is full page burst operation.

(5) Power Down Mode can not be entered in the burst cycle.

When this command asserts in the burst cycle, device state is clock suspend mode.

DEVICE

STATE

idle

(S.R)

Active H L x x x x x x x x

Idle

Active (5)

Any

(power

down)

CKEn-1 CKEn DQM BS0, 1 A10

L

L

H

H

L

L

H

H

L

L

H

H

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

A0−A9

x

x

x

x

x

x

CS RAS CAS WE

H

x

x

L

H

H x x

H

x

x

L

H

H X H

H

x

x

L

H

H X H

- 12 -

Simplified State Diagram

Mode

Register

Set

F

L

E

S

x

e

F

L

E

ACT

S

C

K

E

C

K

E

MRS REF

IDLE

Refresh

t

i

Self

Power

Down

CBR

Refresh

W9864G6DB

Write

POWER

ON

CKE

CKE

CKE

CKE

WRITE

SUSPEND

WRITEA

SUSPEND

MRS = Mode Register Set
REF = Refresh
ACT = Active
PRE = Precharge
WRITEA = Write with Auto precharge
READA = Read with Auto precharge

S

B

WRITE

WRITEA

Precharge

ROW

ACTIVE

T

e

t

i

r

h

P

R

E

W

(

p

r

e

c
h

t

i

c

e

w

r

e

p

t

i

r

o

t

u

A

Read

a

r

g

e

t

e

r

m

i

n

a

t

i

Precharge

h

o

W

CKE

CKE

A

R

e

u

t

o

p

PRE

R

P

r

e

c

h

a

rg

Write

e

r

p

(

E

e

a

R

e

a

d

w

i

t

h

e

)

n

o

i

t

a

n

i

m

r

e

t

e

g

r

a

h

c

g

r

a

n

)

d

B

S

T

READ

READA

Active
Power

Down

Read

CKE

CKE

CKE

CKE

READ

SUSPEND

READA

SUSPEND

Automatic sequence

Manual input

Publication Release Date: January 27, 2003

- 13 - Revision A1

W9864G6DB

8. DC CHARACTERISTICS

Absolute Maximum Rating

PARAMETER SYM. RATING UNIT NOTES

Input, Column Output Voltage VIN, VOUT

Power Supply Voltage VDD, VDDQ

Operating Temperature TOPR

Storage Temperature TSTG

-0.3 − V

-0.3 − 4.6

0 − 70

-55 − 150

DD +0.3

Soldering Temperature (10s) TSOLDER 260 °C 1

Power Dissipation PD 1 W 1

Short Circuit Output Current IOUT 50 mA 1

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.

Recommended DC Operating Conditions

(TA = 0 to 70°C)

V 1

V 1

°C 1

°C 1

PARAMETER SYM. MIN. TYP. MAX. UNIT NOTES

Power Supply Voltage VDD 2.7 3.3 3.6 V 2

Power Supply Voltage (for I/O Buffer) VDDQ 2.7 3.3 3.6 V 2

Input High Voltage VIH 2.0 - VDD +0.3 V 2

Input Low Voltage VIL -0.3 - 0.8 V 2

Note: VIH (max.) = VDD/VDDQ +1.2V for pulse width < 5 nS

V

IL (min.) = VSS/VSSQ -1.2V for pulse width < 5 nS

Capacitance

(VDD

= 3.3V, T

Input Capacitance

(A0 to A11, BS0, BS1,

Input Capacitance (CLK) CCLK 2.5 4 pF

Input/Output capacitance (DQ0 − DQ15)

Note: These parameters are periodically sampled and not 100% tested

A = 25 °C, f = 1 MHz)

PARAMETER SYM. MIN. MAX. UNIT

CS , RAS , CAS , WE , DQM, CKE)

C

i 2.5 4 pF

o 4 6.5 pF

C

- 14 -

DC Characteristics

(VDD = 3.6V ~2.7V, TA = 0°~70°C)

PARAMETER SYM.

Operating Current

CK = min., tRC = min.

t

Active precharge command cycling without
burst operation

Standby Current

CK = min., CS = VIH

t
VIH/L = VIH (min.)/ VIL (max.)

Bank: Inactive State

Standby Current

CLK = V
VIH/L=VIH (min.)/VIL (max.)

BANK: Inactive State

No Operating Current

t

BANK: active state (4 banks)

Burst Operating Current (tCK = min.)

Read/Write command cycling

Auto Refresh Current (tCK = min.)

Auto refresh command cycling

Self Refresh Current (CKE = 0.2V)

Self refresh mode

IL, CS = VIH

CK = min., CS = VIH (min.)

1 bank operation I

CKE = V

CKE = V

IH ICC2 30 3

IL (Power

Down mode)

CKE = V

CKE = V

IH ICC2S 8

IL (Power

Down mode)

CKE = V

CKE = V

IH ICC3 55

IL (Power

Down mode)

W9864G6DB

-7

MAX.

CC1 80 3

CC2P 1 3

I

CC2PS 1

I

CC3P 5

I

CC4 145 3, 4

I

CC5 110

I

ICC6 1 mA

CC6L 400

I

UNIT NOTES

mA

3

µA

PARAMETER SYMBOL MIN. MAX. UNIT NOTES

Input Leakage Current

(0V

≤ VIN ≤ VDD, all other pins not under test = 0V)

Output Leakage Current

(Output disable, 0V

≤ VOUT ≤ VDDQ)

LVTTL Output ″H″ Level Voltage

OUT = -2 mA)

(I

LVTTL Output

OUT = 2 mA)

(I

"

L″ Level Voltage

I(L) -5 5

I

O(L) -5 5

V

V

OH 2.4 - V

V

OL - 0.4 V

µA

µA

Publication Release Date: January 27, 2003

- 15 - Revision A1

W9864G6DB

9. AC CHARACTERISTICS

(VDD = 3.6V − 2.7V, V

Ref/Active to Ref/Active Command Period tRC 65

Active to Precharge Command Period tRAS 45 100000

Active to Read/Write Command Delay Time tRCD 20

Read/Write(a) to Read/Write(b)Command Period tCCD 1 Cycle

Precharge to Active(b) Command Period tRP 20

Active(a) to Active(b) Command Period tRRD 14

CLK High Level tCH 2

CLK Low Level tCL 2

Output Data Hold Time tOH 3

Output Data High Impedance Time tHZ 3 7

Output Data Low Impedance Time tLZ 0

Power Down Mode Entry Time tSB 0 7

Transition Time of CLK (Rise and Fall) tT 0.5 10

Data-in-Set-up Time tDS 1.5

Data-in Hold Time tDH 1

Address Set-up Time tAS 1.5

Address Hold Time tAH 1

CKE Set-up Time tCKS 1.5

CKE Hold Time tCKH 1

Command Set-up Time tCMS 1.5

Command Hold Time tCMH 1

Refresh Time tREF 64 mS

Mode Register Set Cycle Time tRSC 14 nS

= 0V, TA = 0 to 70 °C) (Notes: 5, 6.)

SS

PARAMETER SYMBOL

-7

MIN. MAX.

8 Write Recovery Time CL* = 2

7

8 1000 CLK Cycle Time CL* = 2

7 1000

6 Access Time from CLK CL* = 2

5.5

CL* = 3

CL* = 3

CL* = 3

tWR

tCK

tAC

UNIT

nS

nS

- 16 -

W9864G6DB

Notes:

1. Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the

devices.

2. All voltages are referenced to V

3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the

minimum values of t

CK and tRC.

4. These parameters depend on the output loading conditions. Specified values are obtained with

output open.

5. Power up Sequence

(1) Power up must be performed in the following sequence.

(2) Power must be applied to V

signals must be started at the same time.

(3) After power-up a pause of at least 200 µseconds is required. It is required that DQM and CKE signals then be held ‘
high‘ (VDD levels) to ensure that the DQ output is impedance.
(4) All banks must be precharged.
(5) The Mode Register Set command must be asserted to initialize the Mode Register.

(6) A minimum of eight Auto Refresh dummy cycles is required to stabilize the internal circuitry of the device.

6. AC Testing Conditions

PARAMETER CONDITIONS

Output Reference Level 1.4V

Output Load See diagram below

Input Signal Levels (VIH/VIL) 2.4V/0.4V

Transition Time (Rise and Fall) of Input Signal 1 nS

Input Reference Level 1.4V

SS

DD and VDDQ (simultaneously) while all input signals are held in the “NOP” state. The CLK

1.4 V

50 ohms

Z = 50 ohmsoutput

AC TEST LOAD

1. Transition times are measured between VIH and VIL.

2. t

HZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level.

3. These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as
follows the number of clock cycles = specified value of timing/ clock period

(count fractions as whole number)

(1) t

CH is the pulse width of CLK measured from the positive edge to the negative edge referenced to VIH (min.).

t

CL is the pulse width of CLK measured from the negative edge to the positive edge referenced to VIL (max.).

50pF

Publication Release Date: January 27, 2003

- 17 - Revision A1

W9864G6DB

(2) A.C Latency Characteristics

CKE to Clock Disable (CKE Latency) 1 Cycle

DQM to Output to HI-Z (Read DQM Latency) 2

DQM to Output to HI-Z (Write DQM Latency) 0

Write Command to Input Data (Write Data Latency) 0

CS to Command Input ( CS Latency)

Precharge to DQ Hi-Z Lead Time

Precharge to Last Valid Data Out

Bust Stop Command to DQ Hi-Z Lead Time

Bust Stop Command to Last Valid Data Out

Read with Auto Precharge Command to Active/Ref
Command

Write with Auto Precharge Command to Active/Ref
Command

CL = 2 2

CL = 3 3

CL = 2 1

CL = 3 2

CL = 2 2

CL = 3 3

CL = 2 1

CL = 3 2

CL = 2 BL + tRP Cycle + nS

CL = 3 BL + t

CL = 2 BL + tRP

CL = 3 BL + t

0

RP

RP

- 18 -

10. TIMING WAVEFORMS

Command Input Timing

IH

V

CLK

V

IL

CS

RAS

CAS

t

C

K

t

CMStCMH

t

CMStCMH

t

CMStCMH

t

CMH

W9864G6DB

t

t

CH

CL

t

T

t

T

t

CMS

t

CMStCMH

WE

t

AS

t

AH

A0-A10

BS0, 1

t

CKS

t

CKH

t

CKH

t

CKS

t

CKS

t

CKH

CKE

Publication Release Date: January 27, 2003

- 19 - Revision A1

Timing Waveforms, continued

Read Timing

CLK

CS

RAS

CAS

W9864G6DB

Read CAS Latency

WE

A0-A10

BS0, 1

t

t

Valid

Data-Out

AC

OH

Burst Length

t

OH

Valid

Data-Out

t

HZ

DQ

Read Command

t

AC

t

LZ

- 20 -

Timing Waveforms, continued

Control Timing of Input Data

(Word Mask)

CLK

DQM0

DQM1

DQ0 -DQ7

DQ8-DQ15

DQ16 -DQ23

DQ24-DQ31

t

CMH

t

DS

t

DH

Valid

Data-in

t

DH

t

DS

Valid

Data-in

t

DH

t

DS

Valid

Data-in

t

DH

t

DS

Valid

Data-in

t

CMStCMH

t

t

DS

Valid

Data-in

t

t

DS

Valid

Data-in

t

t

DS

Valid

Data-in

W9864G6DB

t

CMS

t

t

CMH

t

DStDH

Valid

Data-in

t

DH

DH

DH

DStDH

Valid

Data-in

t

DS

Valid

Data-in

t

DS

Valid

Data-in

t

DH

t

DH

CMStCMH

t

DStDH

Valid

Data-in

t

DS

Valid

Data-in

t

DS

Valid

Data-in

t

DH

t

DH

t

CMS

t

DStDH

t

DStDH

t

DS

t

DS

Valid

Data-in

Valid

Data-in

Valid

Data-in

Valid

Data-in

t

DH

t

DH

*DQM2,3="L"

(Clock Mask)

CLK

t

CKH

t

CKStCKH

t

CKS

CKE

t

DQ0 -DQ7

DQ8 -DQ15

DQ16 -DQ23

DQ24 -DQ31

DStDH

Valid

Data-in

t

DStDH

Valid

Data-in

t

DStDH

Valid

Data-in

t

DStDH

Valid

Data-in

t

DStDH

Valid

Data-in

t

DStDH

Valid

Data-in

t

DStDH

Valid

Data-in

t

DStDH

Valid

Data-in

t

DH

t

DS

Valid

Data-in

t

DH

t

DS

Valid

Data-in

t

DH

t

DS

Valid

Data-in

t

DH

t

DS

Valid

Data-in

t

DStDH

Valid

Data-in

t

DStDH

Valid

Data-in

t

DStDH

Valid

Data-in

t

DStDH

Valid

Data-in

Publication Release Date: January 27, 2003

- 21 - Revision A1

Timing Waveforms, continued

Control Timing of Output Data

(Output Enable)

CLK

t

DQM0

DQM1

DQ0 -DQ7

DQ8 -DQ15

DQ16 -DQ23

DQ24 -DQ31

CMH

t

OH

t

OH

t

OH

t

OH

t

AC

t

AC

t

AC

t

AC

t

CMStCMH

t

CMH

Valid

Data-Out

Valid

Data-Out

Valid

Data-Out

Valid

Data-Out

W9864G6DB

t

CMS

t

t

CMStCMH

t

AC

t

OH

t

AC

t

OH

t

AC

t

OH

t

AC

t

OH

Valid

Data-Out

Valid

Data-Out

Valid

Data-Out

Valid

Data-Out

t

t

OH

t

t

OH

t

OH

t

OH

CMS

HZ

AC

t

HZ

t

HZ

OPEN

Valid

Data-Out

Valid

Data-Out

Valid

Data-Out

t

AC

t

LZ

t

HZ

t

OH

Valid

Data-Out

t

AC

t

OH

t

AC

t

LZ

OPEN

t

Valid

Data-Out

Valid

Data-Out

AC

t

OH

t

AC

t

OH

t

AC

t

LZ

t

AC

t

OH

*DQM2,3="L"

(Clock Mask)

CLK

t

CKH

t

CKStCKH

t

CKS

CKE

t

DQ0 -DQ7

DQ8 -DQ15

DQ16 -DQ23

DQ24 -DQ31

AC

t

OH

t

AC

t

OH

t

AC

t

OH

t

AC

t

OH

Valid

Data-Out

Valid

Data-Out

Valid

Data-Out

Valid

Data-Out

t

AC

t

OH

t

AC

t

OH

t

AC

t

OH

t

AC

t

OH

- 22 -

Valid

Data-Out

Valid

Data-Out

Valid

Data-Out

Valid

Data-Out

t

AC

t

OH

t

AC

t

OH

t

AC

t

OH

t

AC

t

OH

Valid

Data-Out

Valid

Data-Out

Valid

Data-Out

Valid

Data-Out

t

AC

t

OH

t

AC

t

OH

t

AC

t

OH

t

AC

t

OH

Timing Waveforms, continued

Mode Register Set Cycle

CLK

t

CMH

t

CMS

CS

t

CMH

t

CMS

RAS

t

CMStCMH

CAS

t

CMH

t

CMS

WE

W9864G6DB

t

RSC

A0-A10

BS0,1

t

AS

t

AH

Register

set data

A0

A1

Burst Length

A2

A3

Addressing Mode

A4

A5

CAS Latency

A6

A0

A7

A8 Reserved

A0

A9

A10

A0A11

BS0

A0BS1

(Test Mode)

"0"

"0"

Write Mode

"0"

"0"

"0"

"0"

A0

A0

Reserved

command

A0
A0A2 A1 A0
A00 0 0
A0

0 0 1

A00 1 0
A00 1 1

A0Burst Length

A0Sequential A0Interleave

1 A01

A0

2
A04 A04
A08 A08

A01 0 0
A0

1 0 1

A0

1 1 0

A01 1 1

A0

A3

A0

Reserved

A0Full Page

A0

Addressing Mode

Reserved

A00 A0Sequential
A01 A0Interleave

A0A6 A5 A4
A00 0 0
A00 0 1
A0

0 1 0

A00 1 1
A01 0 0

A0CAS Latency
A0Reserved
A0Reserved

2

A03

Reserved

A0A9 Single Write Mode
A00 A0Burst read and Burst write
A01 A0Burst read and single write

next

A0

2

A0

Publication Release Date: January 27, 2003

- 23 - Revision A1

11. OPERATING TIMING EXAMPLE

Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)

(CLK = 100 MHz)

6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

CLK

1 2 3 4 5

0

W9864G6DB

CS

RAS

CAS

WE

BS0

BS1

A10

A0-A9

DQM

CKE

DQ

t

RC

t

RC

t

RAS

t

RCD

RAa RBb RAc RBd

RAa

CAw

t

RRD

t

AC

RBb

aw0

aw1

t

RCD

t

RP

t

RAS

CBx

aw2 aw3 bx0

t

RRD

RAc CAy

t

AC

t

RCD

bx1

t

bx2

RRD

bx3

t

t

RAS

t

RP

RBd CBz

t

AC

RC

t

RC

t

RP

t

RAS

t

RCD

RAe

RAe

t

AC

cy2

cy0

cy1

t

cy3

RRD

Bank #0

Bank #1

Bank #2

Bank #3

Active

Idle

Read

Precharge

Active Read

Active

- 24 -

Precharge

Read

Active

Precharge

Active

Read

W9864G6DB

Operating Timing Example, continued

Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto Precharge)

(CLK = 100 MHz)

11 12 13 14 15 16 17 18 19 20 21 22 23

CLK

1 2 3 4 5 6 7 8 9 10

0

CS

RAS

CAS

WE

BS0

BS1

A10

A0-A9

DQM

CKE

DQ

t

RC

t

RC

t

RAS

t

RCD

RAa RAc

RAa CAw

RBb

RBb

t

RCD

t

AC

aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2

t

RP

t

RAS

CBx

RAc

t

AC

t

RC

t

RC

t

RAS

t

RP

t

RCD

CAy

t

AC

RBd

RBd

t

RCD

CBz

t

RP

t

RAS

RAe

RAe

t

AC

cy3

dz0

t

Bank #0

Bank #1

Bank #2

Bank #3

Idle

Active

t

RRD

Read

Active

t

AP*

RRD

Read

Active

AP*

RRD

Read

Active

AP*

t

RRD

Active

Read

* AP is the internal precharge start timing

Publication Release Date: January 27, 2003

- 25 - Revision A1

Operating Timing Example, continued

Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)

(CLK = 100 MHz)

8 9 10 11 12 13 14 15 16 17 18

t

RC

CLK

CS

1 2 3 4 5 6 7

0

W9864G6DB

19 20 21 22 23

RAS

CAS

WE

BS0

BS1

A10

A0-A9

DQM

CKE

DQ

t

RCD

RAa

RAa CAx

t

RRD

t

RAS

t

RP

t

RCD

RBb

RBb CBy

t

AC

ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 by4 by5 by6 by7 CZ0

t

RRD

t

RP

t

RAS

t

AC

RAc

RAc

t

t

RAS

RCD

CAz

t

AC

Bank #0

Bank #1

Bank #2

Bank #3

Active

Idle

Read

Precharge

Active

Read

- 26 -

Precharge Active

Read

Precharge

W9864G6DB

Operating Timing Example, continued

Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto Precharge)

(CLK = 100 MHz)

6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

t

RC

21 22 23

CLK

CS

1 2 3 4 5

0

RAS

CAS

WE

BS0

BS1

A10

A0-A9

DQM

CKE

DQ

RAa

RAa

t

RAS

t

RCD

CAx

t

CAC

ax0

ax1

t

RRD

t

RCD

RBb

RBb CBy

ax3 ax4

ax2

ax5 ax6 ax7 by0 by1 by4 by5 by6

t

RRD

t

RP

t

RAS

t

RCD

RAc

RAc

t

CAC

CAz

t

CAC

CZ0

Bank #0

Bank #1

Bank #2

Bank #3

Active

Idle

Read

Active

* AP is the internal precharge start timing

AP*

Read

Active

Read

AP*

Publication Release Date: January 27, 2003

- 27 - Revision A1

Operating Timing Example, continued

Interleaved Bank Write (Burst Length = 8)

(CLK = 100 MHz)

CLK

CS

RAS

CAS

WE

1 2 3 4 5

0

t

RCD

6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

t

RC

t

RAS

t

RCD

W9864G6DB

t

RP

t

RAS

t

RCD

BS0

BS1

A10

A0-A9

RAa

RAa

CAx

RBb

RBb CBy

RAc

RAc CAz

DQM

CKE

DQ

Bank #0

Bank #1

Bank #2

Bank #3

ax0 ax1 by4 by5 by6 by7 CZ0 CZ1 CZ2

Active Write

Idle

t

RRD

ax4 ax5 ax6 ax7 by0 by1 by2 by3

t

RRD

Precharge

Active Write

Active

Write

Precharge

- 28 -

Operating Timing Example, continued

Interleaved Bank Write (Burst Length = 8, Auto Precharge)

(CLK = 100 MHz)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

CLK

CS

t

RC

RAS

t

RP

t

RAS

CAS

WE

t

RAS

W9864G6DB

BS0

BS1

t

A10

A0-A9

RAa

RAa

RCD

CAx

RBb

RBb

t

RCD

CBy

RAb

RAc

t

RCD

CAz

DQM

CKE

DQ

Bank #0

Bank #1

Bank #2

Bank #3

ax0 ax1

Active Write

Idle

t

RRD

ax4

ax5 ax6 ax7 by0 by1

Active

* AP is the internal precharge start timing

AP*

Write

by2

by3 by4

t

RRD

by5

by6 by7 CZ0 CZ1 CZ2

Active

Write

AP*

Publication Release Date: January 27, 2003

- 29 - Revision A1

Operating Timing Example, continued

Page Mode Read (Burst Length = 4, CAS Latency = 3)

(CLK = 100 MHz)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

CLK

t

CS

RAS

CAS

WE

BS0

CCD

t

RAS

t

CCD

t

RAS

t

CCD

W9864G6DB

BS1

t

A10

A0-A9

RAa

RAa

RCD

CAI

t

RCD

RBb

RBb CBx CAy CAm CBz

DQM

CKE

DQ

Bank #0

Bank #1

Bank #2

Bank #3

Active

Idle

t

RRD

Read

Active Read

t

AC

t

a0 a1

a3 bx0

a2

Read Read

* AP is the internal precharge start timing

t

AC

AC

Ay0 Ay1 Ay2 am0

bx1

t

AC

Read

t

AC

am1 am2 bz0 bz1 bz2 bz3

Precharge

AP*

- 30 -

Operating Timing Example, continued

Page Mode Read/Write (Burst Length = 8, CAS Latency = 3)

W9864G6DB

CLK

CS

RAS

CAS

WE

BS0

BS1

A10

A0-A9

DQM

0

RAa

RAa

1 2 3

t

RCD

CAx

6 7 8

5

4

9 10

t

RAS

11 12 13

CAy

14 15

16 17 18

19

21

20

22 23

(CLK = 100 MHz)

CKE

DQ

Bank #0

Bank #1

Bank #2

Bank #3

Active Read

Idle

t

AC

ax0 ax1

ax2

QQ Q Q Q Q

ax3

ax5 ay1

ax4

ay0 ay2 ay4

D

D

Write

ay3

DDD

t

WR

Precharge

Publication Release Date: January 27, 2003

- 31 - Revision A1

Operating Timing Example, continued

Auto Precharge Read (Burst Length = 4, CAS Latency = 3)

(CLK = 100 MHz)

CLK

0

1 2 3

6 7 8

5

4

9 10

11 12 13

14 15

16 17 18

W9864G6DB

19

21

20

22 23

CS

RAS

CAS

WE

BS0

BS1

A10

A0-A9

DQM

CKE

DQ

t

RCD

RAa

RAa CAw

t

RC

t

RAS

t

AC

aw0 aw1 aw2 aw3

t

RP

t

RCD

RAb

RAb

CAx

t

RAS

t

AC

bx2bx1

bx0

bx3

Bank #0

Active

Read

AP*

Bank #1

Bank #2

Bank #3

Idle

* AP is the internal precharge start timing

- 32 -

Active Read

AP*

Operating Timing Example, continued

Auto Precharge Write (Burst Length = 4)

(CLK = 100 MHz)

CLK

CS

RAS

CAS

WE

BS0

0

1 2 3

4

t

RAS

5

t

RC

6 7 8

9 10

t

RP

11 12 13

14 15

t

RAS

16 17 18

t

RC

W9864G6DB

19

21

20

t

22 23

RP

BS1

t

A10

A0-A9

t

RCD

RAa

RAa RAb CAx

CAw

RAb

RCD

RAc

RAc

DQM

CKE

DQ

Bank #0

Bank #1

Bank #2

Bank #3

Active

Idle

aw0 aw1 aw2 aw3

Write

AP*

Active Write

* AP is the internal precharge start timing

bx0

bx1

bx2

bx3

AP*

Active

Publication Release Date: January 27, 2003

- 33 - Revision A1

Operating Timing Example, continued

Auto Refresh Cycle

1 2 3

CLK

CS

RAS

CAS

WE

0

t

RP

4

5

6 7 8

t

W9864G6DB

(CLK = 100 MHz)

9 10

RC

11 12 13

14 15

16 17 18

t

19

RC

21

20

22 23

BS0,1

A10

A0-A9

DQM

CKE

DQ

All Banks
Prechage

Auto

Refresh

Auto Refresh (Arbitrary Cycle)

- 34 -

Operating Timing Example, continued

Self Refresh Cycle

W9864G6DB

CLK

CS

RAS

CAS

WE

BS0,1

A10

A0-A9

DQM

0

1 2 3

6 7 8

5

4

t

RP

9 10

11 12 13

14 15

16 17 18

19

21

20

22 23

(CLK = 100 MHz)

t

t

t

SB

CKS

CKS

CKE

t

CKS

DQ

t

RC

Arbitrary Cycle

All Banks

Precharge

Self Refresh

Entry

Self Refresh Cycle

No Operation Cycle

Publication Release Date: January 27, 2003

- 35 - Revision A1

Operating Timing Example, continued

Bust Read and Single Write (Burst Length = 4, CAS Latency = 3)

(CLK = 100 MHz)

CLK

CS

RAS

CAS

WE

BS0

0

1 2 3

t

RCD

6 7 8

5

4

9 10

11 12 13

14 15

16 17 18

W9864G6DB

19

21

20

22 23

BS1

A10

RBa

A0-A9

RBa

CBv CBw CBx CBy

CBz

DQM

CKE

t

DQ

Bank #0
Bank #1

Bank #2

Bank #3

Idle

Read

AC

av0 av1

QQ Q Q D DDQQQQ

av3 aw0 ax0 ay0

av2

Single WriteActive

Read

t

AC

az1 az2 az3

az0

- 36 -

Operating Timing Example, continued

Power Down Mode

1 2 3

0

CLK

CS

RAS

CAS

WE

4

5

6 7 8

(CLK = 100 MHz)

9 10

11 12 13

14 15

16 17 18

W9864G6DB

19

21

20

22 23

BS

A10

A0-A9

DQM

CKE

DQ

RAa RAa

RAa CAa RAa CAx

t

t

CKS

Active

SB

t

CKS

Active Standby

Power Down mode

NOP

Read

ax0

ax1

ax2 ax3

t

SB

t

t

CKS

Precharge NOPActive

CKS

Precharge Standby

Power Down mode

Note: The PowerDown Mode is entered by asserting CKE "low".
All Input/Output buffers (except CKE buffers) are turned off in the PowerDown mode.
When CKE goes high, command input must be No operation at next CLK rising edge.

Publication Release Date: January 27, 2003

- 37 - Revision A1

Operating Timing Example, continued

Auto Precharge Timing (Write Cycle)

0 1110987654321

(1) CAS

Latency=2

( a ) burst length = 1

Command

( b ) burst length = 2

Command

( c ) burst length = 4

Command

( d ) burst length = 8

Command

(2) CAS

Latency=3

( a ) burst length = 1

Command

( b ) burst length = 2

Command

( c ) burst length = 4

Command

( d ) burst length = 8

Command

Write ActAP

t

DQ

WR

D0

Write

DQ

D0

D1

Write

DQ

D0

D1D1D2D2D3

Write

DQ

D0

Write

DQ

AP Act

t

WR

D0

Write

DQ

D0

D1

Write

DQ

D0

D1 D2 D3

Write

DQ

D0 D1 D2 D3

t

RP

AP Act

t

t

WR

RP

D3 D4 D5 D6 D7

t

RP

AP Act

t

WR

AP Act

t

t

WR

t

RP

RP

AP Act

t

t

WR

D4

RP

D5 D6 D7

W9864G6DB

AP Act

t

t

WR

AP Act

t

WR

RP

t

RP

Note:

Write

AP

Act

When the Auto precharge command is asserted, the period from Bank Activate

command to the start of internal precgarging must be at least tRAS (min.)

represents the Write with Auto precharge command.

represents the start of internal precharging.

represents the Bank Activate command.

- 38 -

Operating Timing Example, continued

Auto Precharge Timing (Read Cycle)

W9864G6DB

(1) CAS

Latency=2

( a ) burst length = 1

Command

DQ

( b ) burst length = 2

Command

DQ

( c ) burst length = 4

Command

DQ

( d ) burst length = 8

Command

DQ

(2) CAS

Latency=3

( a ) burst length = 1

Command

DQ

( b ) burst length = 2

Command

DQ

( c ) burst length = 4

Command

DQ

( d ) burst length = 8

Command

DQ

0 1110987654321

Read AP

Read AP Act

Read AP Act

Read AP Act

Read AP Act

Read AP Act

Read AP Act

Act

t

RP

Q0

t

RP

Q0

Q1

t

RP

Q0

Q1 Q2

Q3

AP ActRead

Q0 Q1

t

RP

Q2 Q3 Q4 Q5 Q6 Q7

Q0

t

RP

Q0

Q1

t

Q0

Q1 Q2 Q3

RP

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

t

RP

t

RP

Note:

Read

AP

Act

represents the Read with Auto precharge command.

represents the start of internal precharging.

represents the Bank Activate command.

When the Auto precharge command is asserted, the period from Bank Activate command to

RAS

the start of internal precgarging must be at least t

(min).

Publication Release Date: January 27, 2003

- 39 - Revision A1

Operating Timing Example, continued

Timing Chart of Read to Write Cycle

In the case of Burst Length = 4

W9864G6DB

0

(1) CAS Latency=2

( a ) Command

DQM

DQ

( b ) Command

DQM

DQ

(2) CAS Latency=3

( a ) Command

DQM

DQ

( b ) Command

DQM

DQ

Note: The Output data must be masked by DQM to avoid I/O conflict.

Read Write

D0 D1 D2 D3

Read Write

D0 D1 D2 D3

Read

Write

D0 D1 D2 D3

Read

Write

D0 D1 D2 D3

1110987654321

- 40 -

Operating Timing Example, continued

Timing Chart of Write to Read Cycle

In the case of Burst Length = 4

W9864G6DB

(1) CAS Latency = 2

( a ) Command

DQM

DQ

( b ) Command

DQM

DQ

(2) CAS Latency = 3

( a ) Command

DQM

DQ

( b ) Command

DQM

DQ

0

D0

Write

D0 D1

Write

Write

D0 D1

ReadWrite

Read

Read

Read

Q0 Q1 Q2 Q3

Q0 Q1 Q2 Q3

Q0 Q1 Q2 Q3D0

Q0

Q1

1110987654321

Q2 Q3

Publication Release Date: January 27, 2003

- 41 - Revision A1

Operating Timing Example, continued

Timing Chart of Burst Stop Cycle (Burst Stop Command)

0 1110987654321

(3) Read cycle

( a ) CAS latency =2

Command

Read BST

W9864G6DB

( b ) CAS latency = 3

(2) Write cycle

DQ

Command

DQ

Command

DQ

Read

Write

D0 D1

Note:

Q0 Q1 Q2 Q3

Q0 Q1 Q2 Q3

D2 D3

BST

represents the Burst stop command

Q4

BST

Q4

BST

D4

- 42 -

Operating Timing Example, continued

Timing Chart of Burst Stop Cycle (Precharge Command)

In the case of Burst Lenght = 8

0 1110987654321

(1) Read cycle

( a )CAS latency =2

Commad

Read

PRCG

W9864G6DB

( b )CAS latency = 3

(2) Write cycle

( a ) CAS latency =2

( b ) CAS latency = 3

DQ

Commad

DQ

Commad

DQM

DQ

Commad

DQM

DQ

Q0 Q1 Q2 Q3

Read

PRCG

Q0 Q1 Q2 Q3

D4

D4

PRCG

t

WR

PRCG

t

WR

Write

D0 D1 D2 D3

Write

D0 D1 D2 D3

PRCG

Note: represents the Precharge command

Q4

Q4

Publication Release Date: January 27, 2003

- 43 - Revision A1

Operating Timing Example, continued

CKE/DQM Input Timing (Write Cycle)

W9864G6DB

CLK cycle No.

External

CLK

Internal

CKE

DQM

DQ

CLK cycle No.

External

CLK

Internal

CKE

DQM

DQ

1

D1 D6D5D3D2

1

D1

5432

DQM MASK

( 1 )

5432

D3D2

6

CKE MASK

6

D5

7

7

D6

DQM MASK

CLK cycle No.

External

CLK

Internal

CKE

DQM

DQ

1

D1

D3D2

- 44 -

( 2 )

CKE MASK

( 3 )

CKE MASK

5432

76

D6D5D4

Operating Timing Example, continued

CKE/DQM Input Timing (Read Cycle)

W9864G6DB

CLK cycle No.

External

CLK

Internal

CKE
DQM

CLK cycle No.

External

CLK

Internal

DQ

CKE

DQM

DQ

1

Q1

1

Q1

Q2

Q3

Q4Q3Q2

( 1 )

5432

5432

Q4

6

Open Open

6

Open

7

Q6

7

Q6

( 2 )

CLK cycle No.

External

CLK

Internal

CKE

DQM

DQ

1

Q1

Q2

Q3

( 3 )

765432

Q5Q4

Q6

Publication Release Date: January 27, 2003

- 45 - Revision A1

Operating Timing Example, continued

Self Refresh/Power Down Mode Exit Timing

Asynchronous Control
Input Buffer turn on time (Power down mode exit time) is specified by t

CKS

W9864G6DB

(min.) + t

CK

(min.)

A ) tCK < t

CLK

CKE

Command

CLK

CKE

B) t

CK

>= t

CKS

CKS

(min.) + t

(min.) + t

CK

(min.)

t

CKS

(min)+tCK(min)

NOP

CK

t

CK

(min.)

t

CK

t

Command

Input Buffer Enable

CKS

(min)+tCK(min)

Command

Command

Input Buffer Enable

Note:

All Input Buffer (Include CLK Buffer) are turned off in the Power Down mode
and Self Refresh mode

NOP

Command

Represents the No-Operation command

Represents one command

- 46 -

12. PACKAGE DIMENSIONS

BGA 60 Balls Pitch = 0.65 mm

W9864G6DB

Publication Release Date: January 27, 2003

- 47 - Revision A1

W9864G6DB

13. VERSION HISTORY

VERSION DATE PAGE DESCRIPTION

A1 January 27, 2003 - Formal Version

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: [phone]
FAX: [phone]
http://www.winbond.com.tw/

Taipei Office

9F, No.480, Rueiguang Rd.,

Neihu District, Taipei, 114,

Taiwan, R.O.C.
TEL: [phone]
FAX: [phone]

Please note that all data and specifications are subject to change without notice.

All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

Winbond Electronics Corporation America

2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: [phone]

FAX: [phone]

Winbond Electronics Corporation Japan

7F Daini-ueno BLDG, 3-7-18

Shinyokohama Kohoku-ku,

Yokohama, 222-0033
TEL: [phone]
FAX: [phone]

- 48 -

Winbond Electronics (Shanghai) Ltd.

27F, 2299 Yan An W. Rd. Shanghai,
200336 China
TEL: [phone]
FAX: [phone]

Winbond Electronics (H.K.) Ltd.

Unit 9-15, 22F, Millennium City,

No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
TEL: [phone]
FAX: [phone]