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W986416CH
1M x 16 bit x 4 Banks SDRAM
Features
• 3.3V±0.3V power supply
• Up to 166 MHz clock frequency
• 1,048,576 words x 4 banks x 16 bits organization
• Auto Refresh and Self Refresh
• CAS latency: 2 and 3
• Burst Length: 1, 2, 4, 8 , and full page
• Burst read, Single Writes Mode
• Byte data controlled by UDQM and LDQM
• Power-Down Mode
• Auto-Precharge and controlled precharge
• 4k refresh cycles / 64ms
• Interface: LVTTL
• Package: TSOP II 54 pin, 400 mil - 0.80
General Description
W986416CH is a high speed synchronous dynamic random access memory (SDRAM), organized as 1M words x 4 banks x
16 bits. Using pipelined architecture and 0.20um process technology, W986416CH delivers a data bandwidth of up to 332M
bytes per second (-6). For different application, W986416CH is sorted into four speed grades: -6, -7, -75 and -8H. The -6 parts
can run up to 166Mhz/CL3. The -7 parts can run up to 143Mhz/CL3 specification. The -75 parts can run up to PC133/CL3
specification. The -8H parts can run up to 125Mhz/CL3 or PC100/CL2 specification.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of
1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated
by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock
cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst
to maximize its performance. W986416CH is ideal for main memory in high performance applications.
Key Parameters
Symbol Description min/max -6 -7 -75(PC133) -8H(PC100)
tCK Clock Cycle Time min 6ns 7ns 7.5ns 8ns
tAC Access Time from CLK max 5ns 5.4ns 5.4ns 6ns
tRP Precharge to Active Command min 18ns 20ns 20ns 20ns
tRCD Active to Read/Write Command min 18ns 20ns 20ns 20ns
ICC1 Operation Current ( Single bank ) max 80mA 65mA 65mA 60mA
ICC4 Burst Operation Current max 130mA 115mA 115mA 110mA
ICC6 Self-Refresh Current max 1mA 1mA 1mA 1mA
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BLOCK DIAGRAM
W986416CH
1M x 16 bit x 4 Banks SDRAM
A10
A0
A9
A11
BS0
BS1
CLK
CKE
CS
RAS
CAS
WE
CLOCK
BUFFER
COMMAND
DECODER
ADDRESS
BUFFER
REFRESH
COUNTER
CONTROL
SIGNAL
GENERATOR
MODE
REGISTER
COLUMN
COUNTER
COLUMN DECODER
CELL ARRAY
BANK #0
ROW DECODER
SENSE AMPLIFIER
DATA CONTROL
CIRCUIT
COLUMN DECODER
CELL ARRAY
BANK #1
ROW DECODERROW DECODER
SENSE AMPLIFIER
DMn
DQ
BUFFER
DQ0
DQ15
UDQM
LDQM
COLUMN DECODER
CELL ARRAY
BANK #2
ROW DECODER
SENSE AMPLIFIER
COLUMN DECODER
CELL ARRAY
BANK #3
SENSE AMPLIFIER
NOTE:
The cell array configuration is 4096 * 256 * 16.
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W986416CH
1M x 16 bit x 4 Banks SDRAM
Pin Assignment
Pin Number Pin Name Function Description
23 ~ 26, 22,
29 ~35
20, 21 BS0, BS1 Bank Select Select bank to activate during row address latch time, or bank to
2, 4, 5, 7, 8,
10, 11, 13,
42, 44, 45,
47, 48, 50,
51, 53
19 CS# Chip Select Disable or enable the command decoder. When command
18 RAS# Row Address
17 CAS# Column
16 WE# Write Enable Referred to RAS#
39, 15 UDQM/
38 CLK Clock Inputs System clock used to sample inputs on the rising edge of clock.
37 CKE Clock Enable CKE controls the clock activation and deactivation. When CKE
1, 14, 27 VCC Power ( +3.3 V ) Power for input buffers and logic circuit inside DRAM.
28, 41, 54 VSS Ground Ground for input buffers and logic circuit inside DRAM.
3, 9, 43, 49 VCCQ Power ( + 3.3 V
6, 12, 46, 52 VSSQ Ground for I/O
36, 40 NC No Connection No connection
A0~ A11 Address Multiplexed pins for row and column address.
Row address: A0 ~ A11. Column address: A0 ~ A7.
read/write during address latch time.
DQ0 ~
DQ15
LDQM
Data Input/
Output
Strobe
Address Strobe
input/output
mask
) for I/O buffer
buffer
Multiplexed pins for data output and input.
decoder is disabled, new command is ignored and previous
operation continues.
Command input. When sampled at the rising edge of the clock,
RAS#, CAS# and WE# define the operation to be executed.
Referred to RAS#
The output buffer is placed at Hi-Z (with latency of 2) when DQM
is sampled high in read cycle. In write cycle, sampling DQM
high will block the write operation with zero latency.
is low, Power Down mode, Suspend mode, or Self Refresh
mode is entered.
Separated power from VCC, used for output buffers to improve
noise.
Separated ground from VSS, used for output buffers to improve
noise.
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Pin Assignment (Top View)
W986416CH
1M x 16 bit x 4 Banks SDRAM
VCC
DQ0
VCCQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VCCQ
DQ5
DQ6
VSSQ
DQ7
VCC
LDQM
WE
CAS
RAS
CS
BS0
BS1
A10/AP
A0
A1
A2
A3
VCC
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
DQ15
53
VSSQ
52
DQ14
51
DQ13
50
VCCQ
49
DQ12
48
DQ11
47
VSSQ
46
DQ10
45
DQ9
44
VCCQ
43
DQ8
42
VSS
41
NC
40
UDQM
39
CLK
38
CKE
37
NC
36
A11
35
A9
34
A8
33
A7
32
A6
31
A5
30
A4
29
VSS
28
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W986416CH
1M x 16 bit x 4 Banks SDRAM
ABSOLUTE MAXIMUM RATINGS
SYMBOL ITEM RATING UNIT NOTES
VIN,VOUT Input, Output Voltage -0.3~VCC+0.3 V 1
VCC,VCCQ Power Supply Voltage -0.3~4.6 V 1
TOPR Operating Temperature 0~70 °C 1
TSTG Storage Temperature -55~150 °C 1
TSOLDER Soldering Temperature(10s) 260 °C 1
PD Power Dissipation 1 W 1
IOUT Short Circuit Output Current 50 mA 1
RECOMMENDED DC OPERATING CONDITIONS ( Ta = 0 to 70°C )
SYMBOL PARAMETER MIN TYP MAX UNIT NOTES
VCC Power Supply Voltage 3.0 3.3 3.6 V 2
VCCQ Power Supply Voltage (for I/O Buffer) 3.0 3.3 3.6 V 2
VIH Input High Voltage 2.0 - VCC+0.3 V 2
VIL Input Low Voltage -0.3 - 0.8 V 2
Note: VIH(max) = VCC/VCCQ+1.2V for pulse width < 5ns
VIL(min) = VSS/VSSQ-1.2V for pulse width < 5ns
CAPACITANCE (VCC=3.3V, Af = 1MHz, Ta=25°C)
SYMBOL PARAMETER MIN MAX UNIT
CI
CO Input/Output capacitance - 6.5 pf
Note: These parameters are periodically sampled and not 100% tested.
Input Capacitance (A0 to A11, BS0 ,BS1, CS, RAS, CAS, WE, DQM, CKE) - 4 pf
Input Capacitance (CLK) - 4 pf
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1M x 16 bit x 4 Banks SDRAM
AC CHARACTERISTICS AND OPERATING CONDITION
(Vcc=3.3V±0.3V, Ta=0° to 70°C Notes:5, 6, 7, 8)
W986416CH
SYMBOL PARAMETER
t
t
t
t
t
t
t
t
t
t
t
t
t
RC
RAS
RCD
CCD
t
RP
RRD
WR
t
CK
t
CH
t
CL
t
AC
OH
t
HZ
t
LZ
t
SB
t
t
DS
t
DH
t
AS
t
AH
CKS
CKH
CMS
CMH
REF
RSC
T
Ref/Active to Ref/Active Command Period 60 63 65 68
Active to precharge Command Period 42 10000 42 10000 45 10000 48 10000 Ns
Active to Read/Write Command Delay Time 18 20 20 20
Read/Write(a) to Read/Write(b)Command 1 1 1 1 Cycle
Precharge to Active Command Period 18 20 20 20
Active(a) to Active(b) Command Period 12 14 15 20
Write Recovery Time CL*=2 10 10 10 10
CLK Cycle Time CL*=2 10 1000 10 1000 10 1000 10 1000
CLK High Level width 2.5 2.5 2.5 3
CLK Low Level width 2.5 2.5 2.5 3
Access Time from CLK CL*=2 6 6 6 6
Output Data Hold Time 2 2.5 2.7 3
Output Data High Impedance Time 2 6 2.5 7 2.7 7.5 3 8
Output Data Low Impedance Time 0 0 0 0
Power Down Mode Entry Time 0 6 0 7 0 7.5 0 8
Transition Time of CLK (Rise and Fall) 0.3 10 0.3 10 0.3 10 0.5 10
Data-in Set-up Time 1.5 1.5 1.5 2
Data-in Hold Time 0.8 0.8 0.8 1
Address Set-up Time 1.5 1.5 1.5 2
Address Hold Time 0.8 0.8 0.8 1
CKE Set-up Time 1.5 1.5 1.5 2
CKE Hold Time 0.8 0.8 0.8 1
Command Set-up Time 1.5 1.5 1.5 2
Command Hold Time 0.8 0.8 0.8 1
Refresh Time 64 64 64 64 ms
Mode register Set Cycle Time 12 14 15 16 ns
-6 -7 -75(PC133) -8H(PC100) UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
CL*=3 6 7 7.5 8
CL*=3 6 1000 7 1000 7.5 1000 8 1000
CL*=3 5 5.4 5.4 6 ns
* CL=CAS Latency
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1M x 16 bit x 4 Banks SDRAM
DC CHARACTERISTICS (VCC = 3.3V ± 0.3V, Ta=0°~70°C)
ITEMS SYMBOL
OPERATING CURRENT
tCK=min , tRC=min
Active Precharge command cycling
without Burst operation
STANDBY CURRENT
tCK=min , CS#=VIH
VIH/L=VIH(min)/VIL(max)
Bank : inactive state
STANDBY CURRENT
CLK=VIL , CS#=VIH
VIH/L=VIH(min)/VIL(max)
BANK : inactive state
NO OPERATING CURRENT
tCK=min
CS#=VIH(min)
BANK : active state (4 banks)
BURST OPERATING CURRENT
tCK = min
Read / Write command cycling
AUTO REFRESH CURRENT
tCK = min
Auto Refresh command cycling
SELF REFRESH CURRENT
Self Refresh mode
CKE = 0.2V
1 bank operation ICC1 80 65 60 3
CKE = VIH ICC2 60 45 40 3
CKE = VIL (Power Down mode) ICC2P 1 1 1 3
CKE = VIH ICC2S 7 6 6
CKE = VIL (Power Down mode) ICC2PS 1 1 1
CKE = VIH ICC3 65 50 45
CKE= VIL (Power Down mode) ICC3P 3 3 3
ICC4 130 115 110 3.4
ICC5 155 110 100 3
ICC6 1 1 1
W986416CH
-6 -7/-75(PC133) -8H(PC100)
MAX. MAX. MAX.
UNIT NOTES
mA
ITEM SYMBOL
INPUT LEAKAGE CURRENT
( 0V ≤ VIN ≤ VCC , all other pins not under test = 0V )
OUTPUT LEAKAGE CURRENT
( Output disable , 0V ≤ VOUT ≤ VCCQ )
LVTTL OUTPUT ″H″ LEVEL VOLTAGE
( IOUT = -2mA )
LVTTL OUTPUT ″L″ LEVEL VOLTAGE
( IOUT = 2mA )
MIN. MAX.
II(L)
IO(L) -5 5 µA
VOH 2.4 - V
VOL - 0.4 V
-5 5 µA
UNIT NOTES
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NOTES:
W986416CH
1M x 16 bit x 4 Banks SDRAM
1. Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the devices.
2. All voltages are referenced to VSS
3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of
tCK and tRC.
4. These parameters depend on the output loading conditions. Specified values are obtained with output open. The
W986416CH-6/-7/-75/-8H is tested with 50pF output load.
5. Power up sequence is further described in the "Functional Description" section.
6. AC TESTING CONDITIONS
Output Reference Level 1.4V/1.4V
Output Load The W986416CH-6/-7/-75/-8H is tested with
50pF output load. (See diagram below)
Input Signal Levels 2.4V/0.4V
Transition Time (Rise and Fall) of Input Signal 2ns
Input Reference Level 1.4V
1.4 V
50 ohms
Z = 50 ohmsoutput
50pF
AC TEST LOAD
7 Transition times are measured between VIH and VIL.
8. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level.
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W986416CH
LHHxxxxxxxxHLxHxHxx
HLLxxxxxxxxHLxHxHxx
LHHxxxxxxxxHLxHxHxx
1M x 16 bit x 4 Banks SDRAM
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth
table for the operation commands.
Table 1 Truth Table ( note (1) , (2) )
command
Bank Active Idle
Bank Precharge Any
Precharge All Any
Write Active (3)
Write with Autoprecharge Active (3)
Read Active (3)
Read with Autoprecharge Active (3)
Mode Register Set Idle
No - Operation Any
Burst Stop Active (4)
Device Deselect Any
Auto - Refresh Idle
Self - Refresh Entry Idle
Self Refresh Exit idle
Clock suspend Mode Entry Active
Power Down Mode Entry Idle
Clock Suspend Mode Exit Active
Power Down Mode Exit Any
Data write/Output Enable Active
Data Write/Output Disable Active
Device state
(S.R.)
Active (5)
(power down)
CKEn-1 CKEn DQM BS0,1 A10
A11,
A9-0
CS RAS CAS WE
H x x v v v L L H H
H x x v L x L L H L
H x x x H x L L H L
H x x v L v L H L L
H x x v H v L H L L
H x x v L v L H L H
H x x v H v L H L H
H x x v v v L L L L
H x x x x x L H H H
H x x x x x L H H L
H x x x x x H x x x
H H x x x x L L L H
H L x x x x L L L H
L
H L x x x x x x x x
H
L H x x x x x x x x
L
H x L x x x x x x x
H x H x x x x x x x
Notes: (1) v= valid x = Don't care L= Low Level H= High Level
(2) CKEn signal is input level when commands are provided.
(3) These are state of bank designated by BS0, BS1 signals.
(4) Device state is full page burst operation.
(5) Power Down Mode can not be entered in the burst cycle.
When this command asserts in the burst cycle, device state is clock suspend mode.
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W986416CH
1M x 16 bit x 4 Banks SDRAM
Functional Description
Power Up and Initialization
The default power up state of the mode register is unspecified. The following power up and initialization sequence need to be
followed to guarantee the device being preconditioned to each user specific needs.
During power up, all VCC and VCCQ pins must be ramp up simultaneously to the specified voltage when the input signals are held
in the "NOP" state. The power up voltage must not exceed VCC+0.3V on any of the input pins or VCC supplies. After power up,
an initial pause of 200us is required followed by a precharge of all banks using the precharge command. To prevent data
contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial pause
period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register.
An additional eight Auto Refresh cycles (CBR) are also required before or after programming the Mode Register to ensure
proper subsequent operation.
Programming Mode Register
After initial power up, the Mode Register Set Command must be issued for proper device operation. All banks must be in a
precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode
Register Set Command is activated by the low signals of RAS, CAS, CS and WE at the positive edge of the clock. The address
input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command
may be issued following the mode register set command once a delay equal to tRSC has elapsed. Please refer to the next page for
Mode Register Set Cycle and Operation Table.
Bank Activate Command
The Bank Activate command must be applied before any Read or Write operation can be executed. The operation is similar to
RAS# activate in EDO DRAM. The delay from when the Bank Activate command is applied to when the first read or write
operation can begin must not be less than the RAS to CAS delay time (tRCD). Once a bank has been activated it must be
precharged before another Bank Activate command can be issued to the same bank. The minimum time interval between
successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum
time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time
(tRRD). The maximum time that each bank can be held active is specified as tRAS(max).
Read and Write Access Modes
After a bank has been activated , a read or write cycle can be followed. This is accomplished by setting RAS high and CAS low
at the clock rising edge after minimum of tRCD delay. WE pin voltage level defines whether the access cycle is a read operation
(WE high), or a write operation (WE low). The address inputs determine the starting column address.
Reading or writing to a different row within an activated bank requires the bank be precharged and a new Bank Activate
command be issued. When more than one bank is activated, interleaved bank Read or Write operations are possible. By using
the programmed burst length and alternating the access and precharge operations between multiple banks, seamless data access
operation among many different pages can be realized. Read or Write Commands can also be issued to the same bank or
between active banks on every clock cycle.
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W986416CH
1M x 16 bit x 4 Banks SDRAM
Burst Read Command
The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS and WE high at the rising
edge of the clock. The address inputs determine the starting column address for the burst. The Mode Register sets type of burst
(sequential or interleave) and the burst length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the
next page explain the address sequence of interleave mode and sequence mode.
Burst Command
The Burst Write command is initiated by applying logic low level to CS, CAS and WE while holding RAS high at the rising
edge of the clock. The address inputs determine the starting column address. Data for the first burst write cycle must be applied
on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each
subsequent rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be
ignored.
Read Interrupted by a Read
A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted, the remaining addresses
are overridden by the new read address with the full burst length. The data from the first Read Command continues to appear on
the outputs until the CAS latency from the interrupting Read Command the is satisfied.
Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance
state to avoid data contention on the DQ bus. If a Read Command will issue data on the first and second clocks cycles of the
write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the
DQ bus and DQM masking is no longer needed.
Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is
interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the
programmed burst length is satisfied.
Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is activated. The DQs
must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention.
When the Read Command is activated, any residual data from the burst write cycle will be ignored.
Burst Stop Command
A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open for future Read or Write
Commands to the same page of the active bank, if the burst length is full page. Use of the Burst Stop Command during other
burst length operations is illegal. The Burst Stop Command is defined by having RAS and CAS high with CS and WE low at the
rising edge of the clock. The data DQs go to a high impedance state after a delay which is equal to the CAS Latency in a burst
read cycle interrupted by Burst Stop. If a Burst Stop Command is issued during a full page burst write operation, then any
residual data from the burst write cycle will be ignored.
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W986416CH
Access Address
Burst Length
A8 A7 A6 A5 A4 A3 A2 A1 A0
BL = 2
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
BL = 4
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
BL = 8
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
1M x 16 bit x 4 Banks SDRAM
Table 2 Address Sequence of Sequential Mode
DATA Access Address Burst Length
Data 0 n BL= 2 (disturb address is A0)
Data 1 n + 1 No address carry from A0 to A1
Data 2 n + 2 BL= 4 (disturb addresses are A0 and A1)
Data 3 n + 3 No address carry from A1 to A2
Data 4 n + 4
Data 5 n + 5 BL= 8 (disturb addresses are A0, A1 and A2)
Data 6 n + 6 No address carry from A2 to A3
Data 7 n + 7
. Addressing Sequence of Sequential Mode
A column access is performed by increasing the address from the column address which is input to the
device. The disturb address is varied by the Burst Length as shown in Table 2.
. Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address bit in the
sequence shown in Table 3.
Table 3 Address Sequence of Interleave Mode
DATA
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
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W986416CH
1M x 16 bit x 4 Banks SDRAM
Auto-Precharge Command
If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is entered. During autoprecharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge automatically
before all burst read cycles have been completed. Regardless of burst length, it will begin a certain number of clocks prior to the
end of the scheduled burst cycle. The number of clocks is determined by CAS latency.
A Read or Write Command with auto-precharge can not be interrupted before the entire burst operation is completed. Therefore,
use of a Read, Write, or Precharge Command is prohibited during a read or write cycle with auto-precharge. Once the precharge
operation has started, the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. Issue of Auto-Precharge
command is illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write with AutoPrecharge function is initiated. The SDRAM automatically enters the precharge operation one clock delay from the last burst
write cycle. This delay is referred to as Write tDPL. The bank undergoing auto-precharge can not be reactivated until tDPL and tRP are
satisfied. This is referred to as tDAL, Data-in to Active delay (tDAL = tDPL + tRP). When using the Auto-precharge Command, the
interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy tRAS(min).
Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is entered when
CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge
each bank separately or all banks simultaneously. Three address bits, A10, A12, and A13, are used to define which bank(s) is to
be precharged when the command is issued. After the Precharge Command is issued, the precharged bank must be reactivated
before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must
be greater than or equal to the Precharge time (tRP).
Self Refresh Command
The Self Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock.
All banks must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held low to
keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except
CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will exit Self
Refresh operation after CKE is returned high. A minimum delay time is required when the device exits Self Refresh Operation
and before the next command can be issued. This delay is equal to the tAC cycle time plus the Self Refresh exit time.
If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly distributed), a burst of
4,096 AUTO REFRESH cycles should be completed just prior to entering and just after exiting the self refresh mode.
Power Down Mode
The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are gated off to reduce the
power. The Power Down mode does not perform any refresh operations, therefore the device can not remain in Power Down
mode longer than the Refresh period (tREF) of the device.
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command is required on the next
rising clock edge, depending on tCK. The input buffers need to be enabled with CKE held high for a period equal to tCES(min) +
tCK(min).
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W986416CH
1M x 16 bit x 4 Banks SDRAM
No Operation Command
The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to prevent the SDRAM from
registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS,
CAS, and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is
still executing, such as a burst read or write cycle.
Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought
high, the RAS, CAS, and WE signals become don't cares.
Clock Suspend Mode
During normal access mode, CKE must be held high enabling the clock. When CKE is registered low while at least one of the
banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends any
clocked operation that was currently being executed. There is a one clock delay between the registration of CKE low and the
time at which the SDRAM operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are
issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high
to when Clock Suspend mode is exited.
Revision 1.2 Publication Release Date: June, 1999
- 14 -
Page 15
Timing Waveform
Command Input Timing
W986416CH
1M x 16 bit x 4 Banks SDRAM
CLK
CS
RAS
CAS
WE
A0-A11
BS0, 1
VIH
VIL
t
CK
tCMS tCMH
tCMS tCMH
tCMS tCMH
tCMS tCMH
tAS tAH
tCHtCL
tT tT
tCMH tCMS
CKE
tCKS
tCKH
tCKS
tCKH
tCKS
tCKH
Revision 1.2 Publication Release Date: June, 1999
- 15 -
Page 16
Read Timing
CLK
CS
RAS
W986416CH
1M x 16 bit x 4 Banks SDRAM
Read CAS Latency
CAS
WE
A0-A11
BS0, 1
DQ
Read Command
AC
t
OH
Valid
Data-Out
t
Burst Length
t
OH
Valid
Data-Out
HZ
t
AC
t
t
LZ
Revision 1.2 Publication Release Date: June, 1999
- 16 -
Page 17
Control Timing of Input Data
(Word Mask)
CLK
t
CMH
DQM
t
DS
t
DH
t
CMStCMH
W986416CH
1M x 16 bit x 4 Banks SDRAM
t
CMS
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
Valid
DQ0 -15
Data-in
(Clock Mask)
CLK
t
CKH
CKE
t
DS
t
DH
Valid
DQ0 -15
Data-in
Control Timing of Output Data
(Output Enable)
CLK
t
CMH
DQM
t
t
OH
DQ0 -15
Valid
Data-in
t
CKS
t
CKH
t
DS
t
DH
Valid
Data-in
t
t
CMS
AC
CMH
t
Valid
Data-Out
t
AC
OH
t
t
CKS
CMS
Valid
Data-Out
t
HZ
t
OH
t
DS
Valid
Data-in
Valid
Data-in
OPEN
Valid
Data-in
t
DH
t
AC
t
LZ
t
DS
t
DH
Valid
Data-in
t
AC
t
OH
Valid
Data-Out
(Clock Mask)
CLK
t
CKH
t
CKS
t
CKH
t
CKS
CKE
t
AC
t
OH
t
Valid
Data-Out
t
AC
OH
DQ0 -15
t
AC
t
OH
t
Valid
Data-Out
t
AC
OH
Valid
Data-Out
Revision 1.2 Publication Release Date: June, 1999
- 17 -
Page 18
Mode Register Set Cycle
CLK
t
t
CS
RAS
t
CAS
t
CMH
CMS
t
CMH
t
CMS
CMStCMH
t
CMH
CMS
t
W986416CH
1M x 16 bit x 4 Banks SDRAM
RSC
WE
A0-A10
BS
t
AS
t
AH
Register
set data
A0
A1
Burst Length
A2
A3
Addressing Mode
A4
A5
CAS Latency
A6
"0"
"0"
"0"
"0"
"0"
"0"
(Test Mode)
A0Write Mode
A0
Reserved
A0A7
A8 Reserved
A0A9
A10
A0
A11
BS0
A0BS1
A0
A0A2 A1 A0
A00 0 0
A00 0 1
A0
0 1 0
A00 1 1
A0Sequential A0Interleave
1 A01
A02 A02
A0
4
A0
8
A0
Burst Length
A01 0 0
A0
1 0 1
A0Reserved
A01 1 0
A0
1 1 1
A0
Full Page
A0A3 A0Addressing Mode
A0
0
A0
Sequential
A01 A0Interleave
A0A6 A5 A4
A00 0 0
A00 0 1
A00 1 0
A0
0 1 1
A01 0 0
A0
A9
Single Write Mode
A0CAS Latency
A0Reserved
A0Reserved
2
A0
3
Reserved
A00 A0Burst read and Burst write
A01 A0Burst read and single write
next
command
A0
4
A0
8
A0
Reserved
Revision 1.2 Publication Release Date: June, 1999
- 18 -
Page 19
Operating Timing Example
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)
(CLK = 100 MHz)
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
1 2 3 4 5
0
W986416CH
1M x 16 bit x 4 Banks SDRAM
CS
RAS
CAS
WE
BS0
BS1
A10
A0-A9,
A11
DQM
tRC tRC
tRC tRC
tRAS tRP tRAS tRP
tRPtRAS tRAS
tRCD
RAa RBb RAc RBd
RAa
CAw
tRCD tRCD tRCD
RBb
CBx
RAc CAy
RBd CBz
RAe
RAe
CKE
tAC
Active
cy0 cy1
cy2
tRRD
Precharge
Read
cy3
DQ
Bank #0
Bank #1
Bank #2
Bank #3
Active
Idle
tAC
aw0
tRRD tRRD
Read
aw2 aw3 bx0
aw1
Precharge
Active Read
tAC
Active
bx1
bx2
tRRD
Precharge
bx3
Read
Revision 1.2 Publication Release Date: June, 1999
- 19 -
tAC
Active
Page 20
1M x 16 bit x 4 Banks SDRAM
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Autoprecharge)
(CLK = 100 MHz)
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
1 2 3 4 5
0
W986416CH
CS
RAS
CAS
WE
BS0
BS1
A10
A0-A9,
A11
DQM
CKE
DQ
t
RC
RC
t
t
RAS
t
RCD
RAa RBb RAc
RAa CAw
RBb
t
RCD
t
AC
aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3 dz0
t
CBx
RAS
t
RP
RAc
t
AC
t
RCD
CAy
t
RAS
t
RC
t
RC
t
CBz
t
RP
RAS
RAe
RAe
AC
t
RP
t
t
RCD
RBd
RBd
AC
t
Bank #0
Bank #1
Active
RRD
t
RRD
Read
Active
t
RRD
AP*
Active
Read
t
Read
AP*
Active
AP*
t
RRD
Active
Read
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
Revision 1.2 Publication Release Date: June, 1999
- 20 -
Page 21
Interleaved Bank Read (Burst Length=8, CAS Latency=3)
(CLK = 100 MHz)
W986416CH
1M x 16 bit x 4 Banks SDRAM
CLK
CS
RAS
CAS
WE
BS0
BS1
A10
A0-A9
A11
1 2 3 4 5 6 7
0
t
RCD
RAa
RAa CAx
8 9 10 11 12 13 14 15 16 17 18
t
RC
tRC
t
RAS
tRP tRAS tRP
t
RCD
RBb
RBb CBy
t
RP
RAc
RAc
t
t
RAS
RCD
19 20 21 22 23
t
RC
CAz
DQM
CKE
DQ
Bank #0
Bank #1
Bank #2
Bank #3
Active
Idle
tAC
ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 by4 by5 by6 by7 CZ0
tRRD tRRD
Read
Precharge
Active
Read
tAC
Precharge Active
tAC
Read
Precharge
Revision 1.2 Publication Release Date: June, 1999
- 21 -
Page 22
1M x 16 bit x 4 Banks SDRAM
Interleaved Bank Read (Burst Length=8, CAS Latency=3, Autoprecharge)
(CLK = 100 MHz)
W986416CH
CLK
CS
RAS
CAS
WE
BS0
BS1
A10
A0-A9
DQM
1 2 3 4 5
0
t
RCD
RAa
RAa
CAx
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
t
RC
t
RC
t
RAS
RCD
t
RBb
RBb CBy
t
RP
t
RAS
t
RCD
RAc
RAc
CAz
21 22 23
t
RAS
t
RP
CKE
DQ
Bank #0
Bank #1
Bank #2
Bank #3
Active
Idle
Read
t
RRD
t
CAC
ax0
ax1
ax2
ax3 ax4
t
AP*
Active
Read
* AP is the internal precharge start timing
ax5 ax6 ax7 by0 by1 by4 by5 by6
RRD
CAC
t
Active
Read
AP*
t
CAC
CZ0
Revision 1.2 Publication Release Date: June, 1999
- 22 -
Page 23
Interleaved Bank Write (Burst Length=8)
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
tRAS tRP
CLK
CS
RAS
CAS
WE
1 2 3 4 5
0
tRCD tRCD tRCD
(CLK = 100 MHz)
t
RC
W986416CH
1M x 16 bit x 4 Banks SDRAM
t
RAS
tRAS
tRP
BS0
BS1
A10
A0-A9,
A11
DQM
CKE
DQ
Bank #0
Bank #1
Bank #2
Bank #3
RAa
RAa
Active Write
Idle
CAx
ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 CZ0 CZ1 CZ2
t
RBb
RBb CBy
RRD t
Active Write
RRD
Precharge
RAc
RAc CAz
Active
Write
Precharge
Revision 1.2 Publication Release Date: June, 1999
- 23 -
Page 24
Interleaved Bank Write (Burst Length=8, Autoprecharge)
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
tRC
RAS
tRAS
CAS
WE
W986416CH
1M x 16 bit x 4 Banks SDRAM
tRP tRAS
tRAS tRP
BS0
BS1
A10
A0-A9,
A11
DQM
CKE
DQ
Bank #0
Bank #1
Bank #2
Bank #3
tRCD tRCD tRCD
RAa
RAa
Active Write
Idle
CAx
ax0 ax1
t
RRD
RBb
RBb
ax4
ax5 ax6 ax7 by0 by1
Active
* AP is the internal precharge start timing
CBy
AP*
Write
t
by2
RRD
by3 by4
RAb
RAc
by5
by6 by7 CZ0 CZ1 CZ2
Active
CAz
Write
AP*
Revision 1.2 Publication Release Date: June, 1999
- 24 -
Page 25
Page Mode Read (Burst Length=4, CAS Latency=3)
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
tCCD tCCD tCCD
CS
tRAS tRP
RAS
CAS
WE
W986416CH
1M x 16 bit x 4 Banks SDRAM
tRAS tRP
BS0
BS1
A10
A0-A9,
A11
DQM
CKE
DQ
Bank #0
Bank #1
Bank #2
Bank #3
tRCD tRCD
RAa
RAa
tRRD
Active
Idle
RBb
RBb CBx CAy CAm CBz
CAI
tAC
Ay0 Ay1 Ay2 am0
bx1
Read
Active Read
tACtAC
a0 a1
a3 bx0
a2
Read Read
* AP is the internal precharge start timing
tAC
am1 am2 bz0 bz1 bz2 bz3
Read
tAC
Precharge
AP*
Revision 1.2 Publication Release Date: June, 1999
- 25 -
Page 26
1M x 16 bit x 4 Banks SDRAM
Page Mode Read / Write (Burst Length=8, CAS Latency=3)
(CLK = 100 MHz)
CLK
0
1 2 3
6 7 8
5
4
9 10
11 12 13
14 15
16 17 18
W986416CH
19
21
20
22 23
CS
RAS
CAS
WE
BS0
BS1
A10
A0-A9,
A11
DQM
RAa
RAa
t
RCD
CAx
t
RAS
CAy
RP
t
CKE
t
DQ
Bank #0
Active Read
AC
ax0 ax1
ax2
Q Q Q Q Q Q
ax3
ax5 ay1
ax4
ay0 ay2 ay4
D
D
ay3
D DD
Write
WR
t
Precharge
Bank #1
Bank #2
Bank #3
Idle
Revision 1.2 Publication Release Date: June, 1999
- 26 -
Page 27
AutoPrecharge Read (Burst Length = 4, CAS Latency = 3)
(CLK = 100 MHz)
CLK
CS
RAS
0
1 2 3
6 7 8
5
4
t
RC
9 10
11 12 13
W986416CH
1M x 16 bit x 4 Banks SDRAM
14 15
16 17 18
t
RC
19
21
20
22 23
CAS
WE
BS0
BS1
A10
A0-A9,
A11
DQM
CKE
DQ
t
RCD
RAa
RAa CAw
t
RAS
t
AC
aw0 aw1 aw2 aw3
t
RP
t
RCD
RAb
RAb
CAx
t
RAS
t
AC
bx0 bx1
bx2
t
RP
bx3
Bank #0
Active
Read
AP*
Active Read
AP*
Bank #1
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
Revision 1.2 Publication Release Date: June, 1999
- 27 -
Page 28
AutoPrecharge Write (Burst Length = 4)
CLK
CS
0
1 2 3
4
5
6 7 8
1M x 16 bit x 4 Banks SDRAM
(CLK = 100 MHz)
9 10
11 12 13
14 15
16 17 18
W986416CH
19
21
20
22 23
RAS
CAS
WE
BS0
BS1
A10
A0-A9,
A11
DQM
CKE
tRC
tRAS
3CK tRCD
RAa
RAa CAw RAb CAx
tRP tRAS tRP
RAb
tRC
RAc
RAc
DQ
Bank #0
Active
aw0
Write
aw1 aw2
aw3
AP*
Active Write
bx0
bx1
bx2
bx3
AP*
Active
Bank #1
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
Revision 1.2 Publication Release Date: June, 1999
- 28 -
Page 29
AutoRefresh cycle
W986416CH
1M x 16 bit x 4 Banks SDRAM
(CLK = 100 MHz)
CLK
CS
RAS
CAS
WE
BS0,1
A10
A0-A9,
A11
0
1 2 3
6 7 8
5
4
9 10
tRCtRP tRC
11 12 13
14 15
16 17 18
19
20
21
22 23
DQM
CKE
DQ
All Banks
Prechage
Auto
Refresh
Auto Refresh (Arbitrary Cycle)
Revision 1.2 Publication Release Date: June, 1999
- 29 -
Page 30
SelfRefresh Cycle
0
CLK
CS
RAS
CAS
WE
BS0,1
1 2 3
tRP
W986416CH
1M x 16 bit x 4 Banks SDRAM
(CLK = 100 MHz)
6 7 8
5
4
9 10
11 12 13
14 15
16 17 18
19
21
20
22 23
A10
A0-A9,
A11
DQM
CKE
DQ
All Banks
Precharge
tSB
CKS
t
Self Refresh
Entry
Self Refresh Cycle
tCKS
No Operation Cycle
tRC
CKS
t
Arbitrary Cycle
Revision 1.2 Publication Release Date: June, 1999
- 30 -
Page 31
1M x 16 bit x 4 Banks SDRAM
Burst Read and Single Write (Burst Lenght = 4, CAS Latency = 3)
(CLK = 100 MHz)
W986416CH
CLK
CS
RAS
CAS
WE
BS0
BS1
A10
A0-A9,
A11
0
RBa
RBa
1 2 3
tRCD
CBv CBw CBx CBy
6 7 8
5
4
9 10
11 12 13
14 15
CBz
16 17 18
19
20
21
22 23
DQM
CKE
tAC
az1 az2 az3
az0
DQ
Bank #0
Bank #1
Bank #2
Bank #3
Idle
Read
tAC
av0 av1
Q Q Q Q D DD Q Q Q Q
av3 aw0 ax0 ay0
av2
Single WriteActive
Read
Revision 1.2 Publication Release Date: June, 1999
- 31 -
Page 32
PowerDown Mode
1 2 3
0
CLK
CS
RAS
CAS
WE
BS
W986416CH
1M x 16 bit x 4 Banks SDRAM
(CLK = 100 MHz)
6 7 8
5
4
9 10
11 12 13
14 15
16 17 18
19
21
20
22 23
A10
A0-A9
DQM
CKE
DQ
RAa RAa
RAa CAa RAa CAx
tCKS
Active
tSB
tCKS tCKS
ax0
ax1
Wrate
NOP
Active Standby
Power Down mode
ax2 ax3
tSB
tCKS
Precharge NOPActive
Precharge Standby
Power Down mode
Note: The PowerDown Mode is entered by asserting CKE "low".
All Input/Output buffers (except CKE buffers) are turned off in the PowerDown mode.
When CKE goes high, command input must be No operation at next CLK rising edge.
Revision 1.2 Publication Release Date: June, 1999
- 32 -
Page 33
Autoprecharge Timing ( Read Cycle )
0 1110987654321
(1) CAS Latency=2
( a ) burst length = 1
Command
( b ) burst length = 2
Command
( c ) burst length = 4
Command
( d ) burst length = 8
Command
(2) CAS Latency=3
( a ) burst length = 1
Command
( b ) burst length = 2
Command
( c ) burst length = 4
Command
( d ) burst length = 8
Command
Read AP
DQ
Read AP Act
DQ
Read AP Act
DQ
DQ
Read AP Act
DQ
Read AP Act
DQ
Read AP Act
DQ
Read AP Act
DQ
Act
RP
t
Q0
RP
t
Q0
Q0
Q1
Q1 Q2
Q0 Q1
t
RP
Q0
Q0
Q0
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
1M x 16 bit x 4 Banks SDRAM
t
RP
Q3
AP ActRead
Q2 Q3 Q4 Q5 Q6 Q7
RP
t
Q1
RP
Q1 Q2 Q3
t
W986416CH
t
RP
t
RP
Note )
Read
AP
Act
represents the Read with Auto precharge command.
represents the start of internal precharging.
represents the Bank Activate command.
When the Auto precharge command is asserted, the period from Bank Activate command to
the start of internal precgarging must be at least t
RAS
(min).
Revision 1.2 Publication Release Date: June, 1999
- 33 -
Page 34
Autoprecharge timing ( Write Cycle )
0 1110987654321
(1) CAS Latency=2
( a ) burst length = 1
Command
( b ) burst length = 2
Command
( c ) burst length = 4
Command
( d ) burst length = 8
Command
(2) CAS Latency=3
( a ) burst length = 1
Command
( b ) burst length = 2
Command
( c ) burst length = 4
Command
( d ) burst length = 8
Command
Write ActAP
t
DQ
WR
D0
Write
DQ
D0
D1
Write
DQ
D0
D1
Write
DQ
D0
Write
DQ
D0
D1
AP Act
t
WR
Write
DQ
D0
D1
Write
DQ
D0
D1 D2 D3
Write
DQ
D0 D1 D2 D3 D4 D5 D6 D7
t
RP
AP Act
t
t
WR
RP
AP Act
t
WR
D2
D2
D3
D3 D4 D5 D6 D7
t
RP
AP Act
t
t
WR
RP
AP Act
t
WR
W986416CH
1M x 16 bit x 4 Banks SDRAM
t
RP
AP Act
t
WR
t
RP
AP Act
t
WR
t
RP
t
RP
Note )
Write
AP
Act
When the Auto precharge command is asserted, the period from Bank Activate
command to the start of internal precgarging must be at least tRAS(min) .
represents the Write with Auto precharge command.
represents the start of internal precharging.
represents the Bank Activate command.
Revision 1.2 Publication Release Date: June, 1999
- 34 -
Page 35
Timing Chart of Read to Write cycle
In the case of Burst Length=4
W986416CH
1M x 16 bit x 4 Banks SDRAM
(1) CAS Latency=2
( a ) Command
DQM
( b ) Command
DQM
(2) CAS Latency=3
( a ) Command
DQM
( b ) Command
DQM
0
Read Write
DQ
D0 D1 D2 D3
Read Write
DQ
Read
DQ
Write
Read
DQ
Note ) The Output data must be masked by DQM to avoid I/O conflict
D0 D1 D2 D3
D0 D1 D2 D3
Write
D0 D1 D2 D3
1110987654321
Revision 1.2 Publication Release Date: June, 1999
- 35 -
Page 36
Timing Chart of Write-to-Read cycle
In the case of Burst Length=4
W986416CH
1M x 16 bit x 4 Banks SDRAM
(1) CAS Latency=2
( a ) Command
DQM
DQ
( b ) Command
DQM
DQ
(2) CAS Latency=3
( a ) Command
DQM
DQ
( b ) Command
DQM
DQ
0
1110987654321
ReadWrite
D0
Write
D0 D1
Write
Read
Read
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3D0
Write
D0 D1
Read
Q0
Q1
Q2 Q3
Revision 1.2 Publication Release Date: June, 1999
- 36 -
Page 37
Timing chart of Burst Stop cycle ( Burst stop Command )
0 1110987654321
(3) Read cycle
( a ) CAS latency =2
Command
Read BST
W986416CH
1M x 16 bit x 4 Banks SDRAM
( b )CAS latency = 3
Command
(2) Write cycle
Command
DQ
Read
DQ
Write
DQ
D0 D1
Note ) represents the Burst stop command
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
D2 D3
BST
BST
BST
D4
Q4
Q4
Revision 1.2 Publication Release Date: June, 1999
- 37 -
Page 38
(1) Read cycle
( a )CAS latency =2
1M x 16 bit x 4 Banks SDRAM
Timing chart of Burst Stop cycle ( Precharge Command )
In the case of Burst Lenght = 8
0 1110987654321
Commad
Read
PRCG
W986416CH
( b )CAS latency = 3
(2) Write cycle
( a ) CAS latency =2
( b )CAS latency = 3
DQ
Commad
DQ
Commad
DQM
DQ
Commad
DQM
DQ
Q0 Q1 Q2 Q3
Read
Write
D0 D1 D2 D3
Write
D0 D1 D2 D3
Note ) represents the Precharge commandPRCG
Q4
PRCG
Q0 Q1 Q2 Q3
PRCG
tWR
D4
PRCG
t
WR
D4
Q4
Revision 1.2 Publication Release Date: June, 1999
- 38 -
Page 39
CKE/DQM Input timing ( Write cycle )
W986416CH
1M x 16 bit x 4 Banks SDRAM
CLK cycle No.
External
CLK
Internal
CKE
CLK cycle No.
External
CLK
Internal
DQM
DQ
CKE
DQM
1
D1 D6D5D3D2
1
DQM MASK
( 1 )
5432
5432
6
CKE MASK
6
7
7
CLK cycle No.
External
CLK
DQ
Internal
CKE
DQM
DQ
D1
1
D1
D3D2
DQM MASK
( 2 )
CKE MASK
D5
5432
D3D2
CKE MASK
( 3 )
D6
76
D6D5D4
Revision 1.2 Publication Release Date: June, 1999
- 39 -
Page 40
CKE/DQM Input timing ( Read cycle )
W986416CH
1M x 16 bit x 4 Banks SDRAM
CLK cycle No.
External
CLK
Internal
CLK cycle No.
External
CLK
Internal
CKE
DQM
DQ
CKE
DQM
1
Q1
1
Q4Q3Q2
( 1 )
5432
Open Open
5432
6
6
7
Q6
7
DQ
CLK cycle No.
External
CLK
Internal
CKE
DQM
DQ
Q1
1
Q1
Q2
Q2
Q3
Q3
Q4
Open
( 2 )
Q5Q4
( 3 )
Q6
765432
Q6
Revision 1.2 Publication Release Date: June, 1999
- 40 -
Page 41
1M x 16 bit x 4 Banks SDRAM
Self Refresh/Power Down Mode Exit Timing
Asynchronous Control
Input Buffer turn on time ( Power down mode exit time ) is specified by t
CKS
(min) + tCK(min)
W986416CH
CLK
CKE
Command
CLK
CKE
A ) tCK < t
B) t
CK
>= t
CKS
(min)+tCK(min)
CKS
(min) + t
CKS
t
(min)+tCK(min)
NOP
CK
(min)
t
CK
tCK
t
CKS
(min)+tCK(min)
Command
Input Buffer Enable
Command
Command
Input Buffer Enable
Note )
All Input Buffer(Include CLK Buffer) are turned off in the Power Down mode
and Self Refresh mode
NOP
Command
Represents the No-Operation command
Represents one command
Revision 1.2 Publication Release Date: June, 1999
- 41 -
Page 42
1M x 16 bit x 4 Banks SDRAM
Package Dimension
54L TSOP (II)-400 mil
54 28
W986416CH
H
E
E
1 27
ZD
e
D
Y
SEATING PLANE
b
Controlling Dimension : Millimeters
DIMENSION
(MM)
SYMBOL
A
A1
0.05
A2
b
0.24
c
D
10.06 10.16 10.26 0.400 0.404
E
H
E
e
0.40 0.50
L
L1
Y 0.10
ZD
0.10 0.004
1.00
0.32
0.15
22.2222.12 22.62 0.875 0.905
0.80
0.80 0.032
0.71
MAX.MIN. NOM.
1.20
0.15
0.40
0.60
DIMENSION
(INCH)
0.002
0.039
0.009
0.871
0.396
0.45511.7611.56 11.96 0.463 0.471
0.016
0.012
0.006
0.0315
0.020
0.028
MAX.MIN. NOM.
0.047
0.006
0.016
0.024
0.004
A1
A2
C
A
L
L1
Revision 1.2 Publication Release Date: June, 1999
- 42 -
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