Datasheet W83977TF-PW, W83977TF-P, W83977TF-AW, W83977TF-A Datasheet (Winbond Electronics)

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Page 1

W83977TF

WINBOND I/O

Page 2

W83977TF Data Sheet Revision History

Pages Dates Versi

1 n.a. 05/20/97 0.50 First published.

IV,V,6,7,14,49,5

5,69-80,87-96, 103,113, 117, 118,122, 128, 149

3 III,3,68,134,

146,148; 64-67

4 P101,101.1,102 11/18/97 0.61 Register correction

P1,3,49,62,64,

67,71,73,74, 100,117,119, 120,129

07/01/97 0.51 Typo correction and data calibrated

07/20/97 0.60 Explanation of OnNow/ security wake-up

03/19/98 0.62 Typo correction and data calibrated

Version on Web

Main Contents

functions; Repagenating

Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.

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W83977TF

TABLE OF CONTENTS

GENERAL DESCRIPTION.......................................................................................................1

FEATURES....................................................................................................................................2

PIN CONFIGURATION .............................................................................................................4

1. PIN DESCRIPTION................................................................................................................5

1.1 HOST INTERFACE.....................................................................................................................................5

1.2 GENERAL PURPOSE I/O PORT...............................................................................................................7

1.3 SERIAL PORT INTERFACE......................................................................................................................8

1.4 INFRARED INTERFACE...........................................................................................................................9

1.5 MULTI-MODE PARALLEL PORT...........................................................................................................9

1.6 FDC INTERFACE......................................................................................................................................14

1.7 KBC INTERFACE......................................................................................................................................15

1.8 POWER PINS.............................................................................................................................................16

1.9 ACPI INTERFACE.....................................................................................................................................16

2. FDC FUNCTIONAL DESCRIPTION................................................................................17

2.1 W83977TF FDC.........................................................................................................................................17

2.1.1 AT INTERFACE.............................................................................................................................17

2.1.2 FIFO (DATA)..................................................................................................................................17

2.1.3 DATA SEPARATOR.....................................................................................................................18

2.1.4 WRITE PRECOMPENSATION ...................................................................................................18

2.1.5 PERPENDICULAR RECORDING MODE.................................................................................18

2.1.6 FDC CORE......................................................................................................................................19

2.1.7 FDC COMMANDS ........................................................................................................................19

2.2 REGISTER DESCRIPTIONS...................................................................................................................29

2.2.1 STATUS REGISTER A (SA REGISTER) (READ BASE ADDRESS + 0).............................29

2.2.2 STATUS REGISTER B (SB REGISTER) (READ BASE ADDRESS + 1) .............................31

2.2.3 DIGITAL OUTPUT REGISTER (DO REGISTER) (WRITE BASE ADDRESS + 2)............33

2.2.4 TAPE DRIVE REGISTER (TD REGISTER) (READ BASE ADDRESS + 3)........................33

2.2.5 MAIN STATUS REGISTER (MS REGISTER) (READ BASE ADDRESS + 4)....................34

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W83977TF

2.2.6 DATA RATE REGISTER (DR REGISTER) (WRITE BASE ADDRESS + 4).......................34

2.2.7 FIFO REGISTER (R/W BASE ADDRESS + 5)..........................................................................36

2.2.8 DIGITAL INPUT REGISTER (DI REGISTER) (READ BASE ADDRESS + 7)....................38

2.2.9 CONFIGURATION CONTROL REGISTER (CC REGISTER)

(WRITE BASE ADDRESS + 7)...................................................................................................39

3. UART PORT............................................................................................................................40

3.1 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A, UART B)..................40

3.2 REGISTER ADDRESS..............................................................................................................................40

3.2.1 UART CONTROL REGISTER (UCR) (READ/WRITE)...........................................................40

3.2.2 UART STATUS REGISTER (USR) (READ/WRITE)...............................................................42

3.2.3 HANDSHAKE CONTROL REGISTER (HCR) (READ/WRITE) ............................................43

3.2.4 HANDSHAKE STATUS REGISTER (HSR) (READ/WRITE).................................................44

3.2.5 UART FIFO CONTROL REGISTER (UFR) (WRITE ONLY) .................................................45

3.2.6 INTERRUPT STATUS REGISTER (ISR) (READ ONLY).......................................................46

3.2.7 INTERRUPT CONTROL REGISTER (ICR) (READ/WRITE).................................................47

3.2.8 PROGRAMMABLE BAUD GENERATOR (BLL/BHL) (READ/WRITE) .............................47

3.2.9 USER-DEFINED REGISTER (UDR) (READ/WRITE).............................................................48

4. INFRARED (IR) PORT.........................................................................................................49

5. PARALLEL PORT ...............................................................................................................49

5.1 PRINTER INTERFACE LOGIC...............................................................................................................49

5.2 ENHANCED PARALLEL PORT (EPP)..................................................................................................50

5.2.1 DATA SWAPPER ..........................................................................................................................51

5.2.2 PRINTER STATUS BUFFER.......................................................................................................51

5.2.3 PRINTER CONTROL LATCH AND PRINTER CONTROL SWAPPER...............................52

5.2.4 EPP ADDRESS PORT...................................................................................................................52

5.2.5 EPP DATA PORT 0-3....................................................................................................................53

5.2.6 BIT MAP OF PARALLEL PORT AND EPP REGISTERS .......................................................53

5.2.7 EPP PIN DESCRIPTIONS ............................................................................................................54

5.2.8 EPP OPERATION..........................................................................................................................54

5.3 EXTENDED CAPABILITIES PARALLEL (ECP) PORT.....................................................................55

5.3.1 ECP REGISTER AND MODE DEFINITIONS...........................................................................55

5.3.2 DATA AND ECPAFIFO PORT....................................................................................................56

5.3.3 DEVICE STATUS REGISTER (DSR).........................................................................................56

5.3.4 DEVICE CONTROL REGISTER (DCR) ....................................................................................57

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W83977TF

5.3.5 CFIFO (PARALLEL PORT DATA FIFO) MODE = 010...........................................................58

5.3.6 ECPDFIFO (ECP DATA FIFO) MODE = 011............................................................................58

5.3.7 TFIFO (TEST FIFO MODE) MODE = 110.................................................................................58

5.3.8 CNFGA (CONFIGURATION REGISTER A) MODE = 111 ....................................................58

5.3.9 CNFGB (CONFIGURATION REGISTER B) MODE = 111 .....................................................58

5.3.10 ECR (EXTENDED CONTROL REGISTER) MODE = ALL....................................................59

5.3.11 BIT MAP OF ECP PORT REGISTERS.......................................................................................60

5.3.12 ECP PIN DESCRIPTIONS............................................................................................................61

5.3.13 ECP OPERATION..........................................................................................................................62

5.3.14 FIFO OPERATION ........................................................................................................................62

5.3.15 DMA TRANSFERS........................................................................................................................63

5.3.16 PROGRAMMED I/O (NON-DMA) MODE................................................................................63

5.4 EXTENSION FDD MODE (EXTFDD)...................................................................................................63

5.5 EXTENSION 2FDD MODE (EXT2FDD)..............................................................................................63

6. KEYBOARD CONTROLLER.............................................................................................64

6.1 OUTPUT BUFFER ....................................................................................................................................64

6.2 INPUT BUFFER.........................................................................................................................................64

6.3 STATUS REGISTER.................................................................................................................................65

6.4 COMMANDS .............................................................................................................................................65

6.5 HARDWARE GATEA20/KEYBOARD RESET CONTROL LOGIC .................................................67

6.5.1 KB CONTROL REGISTER (LOGIC DEVICE 5, CR-F0).........................................................67

6.5.2 PORT 92 CONTROL REGISTER (DEFAULT VALUE = 0X24)............................................67

6.4 ONNOW / SECURITY KEYBOARD AND MOUSE WAKE-UP ......................................................68

7. GENERAL PURPOSE I/O....................................................................................................69

7.1 BASIC I/O FUNCTIONS...........................................................................................................................71

7.2 ALTERNATE I/O FUNCTIONS..............................................................................................................73

7.2.1 INTERRUPT STEERING..............................................................................................................73

7.2.2 WATCH DOG TIMER OUTPUT.................................................................................................74

7.2.3 POWER LED...................................................................................................................................74

7.2.4 GENERAL PURPOSE ADDRESS DECODER..........................................................................74

7.2.5 GENERAL PURPOSE WRITE STROBE....................................................................................74

8. PLUG AND PLAY CONFIGURATION ............................................................................75

8.1 COMPATIBLE PNP...................................................................................................................................75

8.1.1 EXTENDED FUNCTION REGISTERS......................................................................................75

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W83977TF

8.1.2 EXTENDED FUNCTIONS ENABLE REGISTERS (EFERS) .................................................76

8.1.3 EXTENDED FUNCTION INDEX REGISTERS (EFIRS), EXTENDED FUNCTION

DATA REGISTERS(EFDRS).......................................................................................................76

9. ACPI REGISTERS FEATURES.........................................................................................77

9.1 SMI TO SCI/SCI TO SMI AND BUS MASTER....................................................................................78

9.2 POWER MANAGEMENT TIMER..........................................................................................................79

9.3 ACPI REGISTERS (ACPIRS)...................................................................................................................80

9.3.1 POWER MANAGEMENT 1 STATUS REGISTER 1 (PM1STS1)..........................................80

9.3.2 POWER MANAGEMENT 1 STATUS REGISTER 2 (PM1STS2)..........................................81

9.3.3 POWER MANAGEMENT 1 ENABLE REGISTER 1(PM1EN1) ............................................82

9.3.4 POWER MANAGEMENT 1 ENABLE REGISTER 2 (PM1EN2)...........................................82

9.3.5 POWER MANAGEMENT 1 CONTROL REGISTER 1 (PM1CTL1)......................................83

9.3.6 POWER MANAGEMENT 1 CONTROL REGISTER 2 (PM1CTL2)......................................83

9.3.7 POWER MANAGEMENT 1 CONTROL REGISTER 3 (PM1CTL3)......................................84

9.3.8 POWER MANAGEMENT 1 CONTROL REGISTER 4 (PM1CTL4)......................................84

9.3.9 POWER MANAGEMENT 1 TIMER 1 (PM1TMR1) ................................................................85

9.3.10 POWER MANAGEMENT 1 TIMER 2 (PM1TMR2) ................................................................85

9.3.11 POWER MANAGEMENT 1 TIMER 3 (PM1TMR3) ................................................................86

9.3.12 POWER MANAGEMENT 1 TIMER 4 (PM1TMR4) ................................................................87

9.3.13 GENERAL PURPOSE EVENT 0 STATUS REGISTER 1 (GP0STS1)...................................87

9.3.14 GENERAL PURPOSE EVENT 0 STATUS REGISTER 2 (GP0STS2)...................................88

9.3.15 GENERAL PURPOSE EVENT 0 ENABLE REGISTER 1 (GP0EN1)....................................89

9.3.16 GENERAL PURPOSE EVENT 0 ENABLE REGISTER 2 (GP0EN2)....................................89

9.3.17 GENERAL PURPOSE EVENT 1 STATUS REGISTER 1 (GP1STS1)...................................90

9.3.18 GENERAL PURPOSE EVENT 1 STATUS REGISTER 2 (GP1STS2)...................................90

9.3.19 GENERAL PURPOSE EVENT 1 ENABLE REGISTER 1 (GP1EN1)....................................91

9.3.20 GENERAL PURPOSE EVENT 1 ENABLE REGISTER 2 (GP1EN2)....................................91

9.3.21 BIT MAP CONFIGURATION REGISTERS...............................................................................92

10. SERIAL IRQ.........................................................................................................................93

10.1 START FRAME .........................................................................................................................................94

10.2 IRQ/DATA FRAME...................................................................................................................................94

10.3 STOP FRAME............................................................................................................................................94

10.4 RESET AND INITIALIZATION..............................................................................................................95

11. CONFIGURATION REGISTER.......................................................................................96

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W83977TF

11.1 CHIP (GLOBAL) CONTROL REGISTER..............................................................................................96

11.2 LOGICAL DEVICE 0 (FDC)...................................................................................................................100

11.3 LOGICAL DEVICE 1 (PARALLEL PORT)..........................................................................................103

11.4 LOGICAL DEVICE 2 (UART A)¢) ........................................................................................................104

11.5 LOGICAL DEVICE 3 (UART B) ...........................................................................................................104

11.6 LOGICAL DEVICE 5 (KBC)..................................................................................................................106

11.7 LOGICAL DEVICE 7 (GP I/O PORT I).................................................................................................107

11.8 LOGICAL DEVICE 8 (GP I/O PORT II)...............................................................................................110

11.9 LOGICAL DEVICE 9 (GP I/O PORT III)..............................................................................................114

11.10 LOGICAL DEVICE A (ACPI)................................................................................................................117

12. SPECIFICATIONS............................................................................................................123

12.1 ABSOLUTE MAXIMUM RATINGS ....................................................................................................123

12.2 DC CHARACTERISTICS.......................................................................................................................123

12.3 AC CHARACTERISTICS.......................................................................................................................127

12.3.1 FDC: DATA RATE = 1 MB, 500 KB, 300 KB, 250 KB/SEC...............................................127

12.3.2 UART/PARALLEL PORT........................................................................................................129

12.3.3 PARALLEL PORT MODE PARAMETERS..........................................................................129

12.3.4 EPP DATA OR ADDRESS READ CYCLE TIMING PARAMETERS..............................130

12.3.5 EPP DATA OR ADDRESS WRITE CYCLE TIMING PARAMETERS ............................131

12.3.6 PARALLEL PORT FIFO TIMING PARAMETERS..............................................................132

12.3.7 ECP PARALLEL PORT FORWARD TIMING PARAMETERS .........................................132

12.3.8 ECP PARALLEL PORT REVERSE TIMING PARAMETERS...........................................132

12.3.9 KBC TIMING PARAMETERS................................................................................................133

12.3.10 GPIO TIMING PARAMETERS................................................................................................134

13. TIMING WAVEFORMS..................................................................................................135

13.1 FDC............................................................................................................................................................135

13.2 UART/PARALLEL...................................................................................................................................136

13.2.1 MODEM CONTROL TIMING ................................................................................................137

13.3 PARALLEL PORT...................................................................................................................................138

13.3.1 PARALLEL PORT TIMING.....................................................................................................138

13.3.2 EPP DATA OR ADDRESS READ CYCLE (EPP VERSION 1.9)......................................139

13.3.3 EPP DATA OR ADDRESS WRITE CYCLE (EPP VERSION 1.9)....................................140

13.3.4 EPP DATA OR ADDRESS READ CYCLE (EPP VERSION 1.7)......................................141

13.3.5 EPP DATA OR ADDRESS WRITE CYCLE (EPP VERSION 1.7)....................................142

13.3.6 PARALLEL PORT FIFO TIMING...........................................................................................142

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W83977TF

13.3.7 ECP PARALLEL PORT FORWARD TIMING......................................................................143

13.3.8 ECP PARALLEL PORT REVERSE TIMING........................................................................143

13.4 KBC............................................................................................................................................................144

13.4.1 WRITE CYCLE TIMING..........................................................................................................144

13.4.2 READ CYCLE TIMING...........................................................................................................144

13.4.3 SEND DATA TO K/B...............................................................................................................144

13.4.4 RECEIVE DATA FROM K/B ..................................................................................................145

13.4.5 INPUT CLOCK..........................................................................................................................145

13.4.6 SEND DATA TO MOUSE.......................................................................................................145

13.4.7 RECEIVE DATA FROM MOUSE..........................................................................................145

13.5 GPIO WRITE TIMING DIAGRAM.......................................................................................................146

13.6 MASTER RESET (MR) TIMING...........................................................................................................146

14. APPLICATION CIRCUITS.............................................................................................147

14.1 PARALLEL PORT EXTENSION FDD.................................................................................................147

14.2 PARALLEL PORT EXTENSION 2FDD...............................................................................................147

14.3 FOUR FDD MODE..................................................................................................................................148

15. ORDERING INFORMATION.........................................................................................148

16. HOW TO READ THE TOP MARKING .......................................................................148

17. PACKAGE DIMENSIONS...............................................................................................149

Publication Release Date: March 1998

- VI - Revision 0.62

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W83977TF

SMI

SCI

WINBOND I/O

GENERAL DESCRIPTION

The W83977TF is an evolving product from Winbond's most popular I/O chip W83877F --- which integrates the disk drive adapter, serial port (UART), IrDA 1.0 SIR, parallel port, configurable plug-and-

play registers for the whole chip --- plus additional powerful features: with PS/2 mouse support, 23 general purpose I/O ports, full 16-bit address decoding, OnNow keyboard

wake-up, OnNow mouse wake-up.

The disk drive adapter functions of W83977TF include a floppy disk drive controller compatible with the industry standard 82077/ 765, data separator, write pre-compensation circuit, decode logic, data rate selection, clock generator, drive interface control logic, and interrupt and DMA logic. The wide range of functions integrated into the W83977TF greatly reduces the number of components required for interfacing with floppy disk drives. The W83977TF supports four 360K, 720K, 1.2M, 1.44M, or 2.88M disk drives and data transfer rates of 250 Kb/s, 300 Kb/s, 500 Kb/s,1 Mb/s, and 2 Mb/s.

The W83977TF provides two high-speed serial communication ports (UARTs), one of which supports serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable baud rate generator, complete modem control capability, and a processor interrupt system. Both UARTs provide legacy speed with baud rate up to 115.2k bps and also advanced speed with baud rates

230k, 460k

The W83977TF supports one PC-compatible printer port (SPP), Bi-directional Printer port (BPP) and also Enhanced Parallel Port (EPP) and Extended Capabilities Port (ECP). Through the printer port interface pins, also available are: Extension FDD Mode and Extension 2FDD Mode allowing one or two external floppy disk drives to be connected.

The configuration registers support mode selection, function enable/disable, and power down function selection. Furthermore, the configurable PnP features are compatible with the plug-and-play feature demand of Windows 95TM, which makes system resource allocation more efficient than ever.

W83977TF provides functions that comply with which includes support of legacy and ACPI power management through

W83977TF also has auto power management to reduce power consumption. The keyboard controller is based on 8042 compatible instruction set with a 2K Byte programmable ROM

and a 256-Byte RAM bank. Keyboard BIOS firmware is available with optional AMIKEY MultiKey/42TM, or customer code.

The W83977TF provides a set of flexible I/O control functions to the system designer through a set of General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually configured to provide a predefined alternate function.

W83977TF is made to fully comply with I/O space resource are flexible to adjust to meet ISA PnP requirement. Moreover W83977TF is made to meet the specification of PC97's requirement in the power management: Power Management).

Another benifit is that W83977TF has the same pin assignment as W83977AF, W83977F, W83977ATF.

This makes the design very flexible.

921k bps

, or

which support higher speed modems.

ACPI (Advanced Configuration and Power Interface

Microsoft PC97 Hardware Design Guide

ACPI

, 8042 keyboard controller

ACPI

function pins.

. IRQs, DMAs, and

DPM

and

2, Phoenix

(Device

Publication Release Date: April 1998

-1- Preliminary Revision 0.62

Page 10

W83977TF

SCI

PRELIMINARY

FEATURES

General

•

Plug & Play 1.0A compatible

• Support 13 IRQs, 4 DMA channels, full 16-bit address decoding

•

Capable of ISA Bus IRQ Sharing

•

Compliant with

•

Support

•

Report ACPI status interrupt by

• Programmable configuration settings

•

Single 24/48 Mhz clock input

FDC

•

Compatible with IBM PC AT disk drive systems

•

Variable write pre-compensation with track selectable capability

• Support vertical recording format

•

DMA enable logic

•

16-byte data FIFOs

•

Support floppy disk drives and tape drives

•

Detects all overrun and underrun conditions

•

Built-in address mark detection circuit to simplify the read electronics

•

FDD anti-virus functions with software write protect and FDD write enable signal (write data signal was

forced to be inactive)

•

Support up to four 3.5-inch or 5.25-inch floppy disk drives

•

Completely compatible with industry standard 82077

•

360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate

•

Support

Microsoft PC97

DPM

(Device Power Management),

3-mode FDD, and its Win95 driver

Hardware Design Guide

ACPI

signal issued from any of the 13 IQRs pins or GPIO xx

UART

•

Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs

•

MIDI compatible

•

Fully programmable serial-interface characteristics:

--- 5, 6, 7 or 8-bit characters

--- Even, odd or no parity bit generation/detection

--- 1, 1.5 or 2 stop bits generation

•

Internal diagnostic capabilities:

--- Loop-back controls for communications link fault isolation

--- Break, parity, overrun, framing error simulation

•

Programmable baud generator allows division of 1.8461 Mhz and 24 Mhz by 1 to (216-1)

Maximum baud rate up to

-2- Revision 0.62

921k bps

for 14.769 Mhz and 1.5M bps for 24 Mhz

Publication Release Date: April 1998

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W83977TF

PRELIMINARY

Infrared

•

Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps

•

Support SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps

• Support S/W driver for Windows95TM and Windows98TM (MemphisTM)

Parallel Port

•

Compatible with IBM parallel port

•

Support PS/2 compatible bi-directional parallel port

•

Support Enhanced Parallel Port (EPP) − Compatible with IEEE 1284 specification

•

Support Extended Capabilities Port (ECP) − Compatible with IEEE 1284 specification

•

Extension FDD mode supports disk drive B; and Extension 2FDD mode supports disk drives A and B

through parallel port

•

Enhanced printer port back-drive current protection

Keyboard Controller

•

8042 based with optional F/W from AMIKKEYTM-2, Phoenix MultiKey/42

with 2K bytes of programmable ROM, and 256 bytes of RAM

•

Asynchronous Access to Two Data Registers and One status Register

•

Software compatibility with the 8042 and PC87911 microcontrollers

•

Support PS/2 mouse

•

Support port 92

• Support both interrupt and polling modes

•

Fast Gate A20 and Hardware Keyboard Reset

•

8 Bit Timer/ Counter

•

Support binary and BCD arithmetic

• 6MHz, 8 MHz, 12 MHz, or 16 MHz operating frequency

or customer code

General Purpose I/O Ports

•

23 programmable general purpose I/O ports; 3 dedicate, 20 optional

•

General purpose I/O ports can serve as simple I/O ports, interrupt steering inputs, watching dog timer

output, power LED output, infrared I/O pins, general purpose address decoder, KBC control I/O pins

OnNow Funtions

•

Keyboard wake-up by programmable keys

•

Mouse wake-up by programmable buttons

Package

•

128-pin PQFP

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-3 - Revision 0.62

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W83977TF

PIN CONFIGURATION

IRQ14/GP14

IRQ15/GP15

IOR

IOW

AEN

IOCHRDY

D0 D1

D2 D3

VCC

DACK0/GP16

SCI/DRQ0/GP17

VSS

DACK1

DRQ1

DACK2

DRQ2

DACK3

DRQ3

D4 D5

D6 MR

103 104

105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128

1 2 345

I R Q 3

989

R Q 4

969

5949392

678 9

I R

9 1

1 0111213

9089888

1 415161718

PRELIMINARY

P A

A N

C C

011

868

1 920

838

281807978

2 1

A 5

222

324252627

777

A1A2A3A4A6A7A8A

7 5

282

747

271

9303132

V S B

G P 2 1

3 3

706

867

VBAT

XTAL1

VSS

XTAL2 MDATA

KDATA

KBLOCK/GP13

KBRST/GP12

57 56

GA20/GP11 VCC

55 54

DCDB

SOUTB/PEN48

SINB

DTRB

RTSB

DSRB

CTSB

DCDA

SOUTA/PENKBC

SINA

DTRA/PNPCSV

RTSA/HEFRAS

DSRA

CTSA

GP24

GP25

C L K I N

, G P 1 0

, /

S C

E X

S Y

S 5

I N

/ I N I T

Publication Release Date: April 1998

-4- Revision 0.62

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W83977TF

IOR

IOW

1. PIN DESCRIPTION

Note: Please refer to Section 11.2 DC CHARACTERISTICS for details. I/O6t - TTL level bi-directional pin with 6 mA source-sink capability I/O8t - TTL level bi-directional pin with 8 mA source-sink capability I/O8 - CMOS level bi-directional pin with 8 mA source-sink capability I/O

- TTL level bi-directional pin with 12 mA source-sink capability

12t

I/O12 - CMOS level bi-directional pin with 12 mA source-sink capability I/O

- CMOS level bi-directional pin with 16 mA source-sink capability with internal pull-up resistor

16u

I/OD

- CMOS level bi-directional pin open drain output with 16 mA sink capability with internal pull-up resistor

16u

I/O

- TTL level bi-directional pin with 24 mA source-sink capability

24t

OUT8t - TTL level output pin with 8 mA source-sink capability OUT

- TTL level output pin with 12 mA source-sink capability

12t

OD12 - Open-drain output pin with 12 mA sink capability OD24 - Open-drain output pin with 24 mA sink capability INt - TTL level input pin INc - CMOS level input pin INcu - CMOS level input pin with internal pull-up resitor INcs - CMOS level Schmitt-triggered input pin INts - TTL level Schmitt-triggered input pin IN

- TTL level Schmitt-triggered input pin with internal pull-up resistor

tsu

PRELIMINARY

1.1 Host Interface

SYMBOL PIN I/O FUNCTION

I/O

IN IN

System address bus bits 0-10

System address bus bits 11-14

System address bus bit 15

System data bus bits 0-5

12t

System data bus bits 6-7

12t

CPU I/O read signal

CPU I/O write signal

System address bus enable

In EPP Mode, this pin is the IO Channel Ready output to extend

the host read/write cycle. Master Reset; Active high; MR is low during normal operations.

Publication Release Date: April 1998

A0−A10 A11-A14 86-89 A15 91 IN D0−D5

74-84

109-

114

D6−D7

116-

117 105 IN

106 IN

AEN 107 IN IOCHRDY 108 OD

MR 118 IN

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W83977TF

DACK0

SCI

DACK1

DACK2

DACK3

1.1 Host Interface, continued

SYMBOL PIN I/O FUNCTION

I/O

OUT

DMA Channel 0 Acknowledge signal. (CR2C bit 5_4 = 00, default)

tsu

General purpose I/O port 1bit 6. (CR2C bit 5_4 = 01)

12t

Alternate function from GP16: Watch dog timer output KBC P15 I/O port. (CR2C bit 5_4 = 10)

12t

DMA Channel 0 request signal. (CR2C bit 7_6 = 00, default)

12t

General purpose I/O port 1bit 7. (CR2C bit 7_6 = 01)

12t

Alternate Function from GP17: Power LED output. KBC P14 I/O port (CR2C bit 7_6 = 10)

12t

System Control Interrupt (CR2C bit 7_6 = 11)

12t

DMA Channel 1 Acknowledge signal

DMA Channel 1 request signal

12t

DMA Channel 2 Acknowledge signal

DMA Channel 2 request signal

12t

DMA Channel 3 Acknowledge signal

DMA Channel 3 request signal

12t

Terminal Count. When active, this pin indicates termination of a

119 IN

I/O

121 OUT

I/O

122 IN

GP16 (WDTO)

P15 DRQ0

GP17 (PLEDO)

P14

DRQ1 123 OUT

124 IN

DRQ2 125 OUT

126 IN

DRQ3 127 OUT TC 128 IN

DMA transfer. IRQ1 99 OUT IRQ3 98 OUT IRQ4 97 OUT IRQ5 96 OUT IRQ6 95 OUT IRQ7 94 OUT IRQ8 93 OUT IRQ9 92 OUT IRQ10 100 OUT IRQ11 101 OUT IRQ12 102 OUT

Interrupt request 1

12t

Interrupt request 3

12t

Interrupt request 4

12t

Interrupt request 5

12t

Interrupt request 6

12t

Interrupt request 7

12t

Interrupt request 8

12t

Interrupt request 9

12t

Interrupt request 10

12t

Interrupt request 11

12t

Interrupt request 12

12t

PRELIMINARY

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W83977TF

GPACS

GPAWE

SMI

SCI

PANSWOUT

PANSWIN

1.1 Host Interface, continued

SYMBOL PIN I/O FUNCTION

IRQ14 103 OUT GP14 I/O

(

)

Alternate Function 1 from GP14: General purpose address

Interrupt request 14. (CR2C bit 1_0 = 00, default)

12t

General purpose I/O port 1 bit 4. (CR2C bit 1_0 = 01)

12t

decode output. (P17)

PLEDO OUT

IRQ15 GP15 (

)

(P12) WDT

CLKIN 1 IN

Alternate Function 2 from GP14: KBC P17 I/O port.

Power LED output. (CR2C bit 1_0 = 10)

12t

104 OUT

I/O

Interrupt request 15.(CR2C bit 3_2 = 00, default)

12t

General purpose I/O port 1 bit 5. (CR2C bit 3_2 = 01)

12t

Alternate Function 1 from GP15: General purpose address write

enable output.

Alternate Function 2 from GP15: KBC P12 I/O port. OUT

Watch-Dog timer output. (CR2C bit 3_2 = 10)

12t

24 or 48 MHz clock input, selectable through bit 5 of CR24.

1.2 General Purpose I/O Port

SYMBOL PIN I/O FUNCTION

GP20 (KBRST)

GP21

69 I/O

70 OUT

I/O

(P13) Alternate Function from GP21: KBC P13 I/O port.

P16

I/O

72 OUT GP22 (P14)

GP23 (P15)

Alternate Function from GP22: KBC P14 I/O port.

73 IN

Alternate Function from GP23: KBC P15 I/O port

GP24 40 I/O

(P16) Alternate Function from GP24: KBC P16 I/O port

P13 GP25

(GA20)

39 I/O

Alternate Function from GP25: GATE A20 (KBC P21)

I/O

General purpose I/O port 2 bit 0.

12t

Alternate Function from GP20: Keyboard reset (KBC P20)

12t

For the power management, the

is active low by the power

management events, that generate and (CR2B bit 4_3 = 00, default)

General purpose I/O port 2 bit 1. (CR2B bit 4_3 = 01)

12t

KBC P16 I/O port. (CR2B bit 4_3 = 10)

12t

Panel Switch output. (CR2B bit 5 = 0, default)

12t

General purpose I/O port 2 bit 2. (CR2B bit 5 = 1)

12t

Panel Switch input. (CR2B bit 7_6 = 00, default)

12t

General purpose I/O port 2 bit 3. (CR2B bit 7_6 = 01)

12t

General purpose I/O port 2 bit 4 (CR2A bit 5_4 = 01)

12t

KBC P13 I/O port. (CR2A bit 5_4 = 10)

12t

General purpose I/O port 2 bit 5.

in ACPI mode.

PRELIMINARY

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W83977TF

CTSA

CTSB

DSRA

DSRB

RTSA

RTSB

DTRA

PNPCSV

DTRB

DCDA

DCDB

1.3 Serial Port Interface

SYMBOL PIN I/O FUNCTION

HEFRAS

41 48

42 49

During power-on reset, this pin is pulled down internally and is

I/O

Clear To Send is the modem control input.

The function of these pins can be tested by reading Bit 4 of the handshake status register.

Data Set Ready. An active low signal indicates the modem or data

set is ready to establish a communication link and transfer data to the UART.

UART A Request To Send. An active low signal informs the

modem or data set that the controller is ready to send data.

defined as HEFRAS, which provides the power-on value for CR26 bit 6 (HEFRAS). A 4.7 kΩ is recommended if intends to pull up. (select 370H as configuration I/O port′s address)

UART B Request To Send. An active low signal informs the

modem or data set that the controller is ready to send data. UART A Data Terminal Ready. An active low signal informs the

modem or data set that the controller is ready to communicate. During power-on reset, this pin is pulled down internally and is

defined as bit 0 (

, which provides the power-on value for CR24

). A 4.7 kΩ is recommended if intends to pull up.

(clear the default value of FDC, UARTs, and PRT)

PRELIMINARY

SINA SINB

SOUTA

45, 52

PENKBC

I/O

UART B Data Terminal Ready. An active low signal informs the

modem or data set that controller is ready to communicate.

Serial Input. Used to receive serial data through the

communication link. UART A Serial Output. Used to transmit serial data out to the

communication link. During power-on reset, this pin is pulled down internally and is

defined as PENKBC, which provides the power-on value for CR24 bit 2 (ENKBC). A 4.7 kΩ resistor is recommended if intends to pull

up. (enable KBC) SOUTB

PEN48

I/O

UART B Serial Output. During power-on reset, this pin is pulled

down internally and is defined as PEN48, which provides the

power-on value for CR24 bit 6 (EN48). A 4.7 kΩ resistor is

recommended if intends to pull up.

47 54

Data Carrier Detect. An active low signal indicates the modem or

data set has detected a data carrier.

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RIA RIB

WE2

WD2

PRELIMINARY

1.3 Serial Port Interface, continued

SYMBOL PIN I/O FUNCTION

65 66

Ring Indicator. An active low signal indicates that a ring signal is

being received from the modem or data set.

1.4 Infrared Interface

SYMBOL PIN I/O FUNCTION

IRRX 37 IN IRTX 38 OUT

Infrared Receiver input.

Infrared Transmitter Output.

12t

1.5 Multi-Mode Parallel Port

The following pins have alternate functions, which are controlled by CR28 and L3-CRF0.

SYMBOL PIN I/O FUNCTION

PRINTER MODE: SLCT

SLCT 18 IN

19 IN

An active high input on this pin indicates that the printer is selected.

This pin is pulled high internally. Refer to description of the

parallel port for definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE:

This pin is for Extension FDD B; its function is the same as the WE

pin of FDC.

EXTENSION 2FDD MODE:

This pin is for Extension FDD A and B; it function is the same as

the WE pin of FDC.

PRINTER MODE: PE

An active high input on this pin indicates that the printer has

detected the end of the paper. This pin is pulled high internally.

Refer to description of the parallel port for definition of this pin in

ECP and EPP mode.

EXTENSION FDD MODE:

This pin is for Extension FDD B; its function is the same as the

pin of FDC.

EXTENSION 2FDD MODE:

This pin is for Extension FDD A and B; its function is the same as

the WD pin of FDC.

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W83977TF

MOB2

MOB

MOB2

MOB

ACK

DSB2

DSB

DSB2

DSB

ERR

HEAD

1.5 Multi-Mode Parallel Port, continued

SYMBOL PIN I/O FUNCTION

BUSY

21 IN

22 IN

PRINTER MODE: BUSY

An active high input indicates that the printer is not ready to receive

data. This pin is pulled high internally. Refer to description of the

parallel port for definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE:

This pin is for Extension FDD B; the function of this pin is the same

as the

EXTENSION 2FDD MODE:

pin of FDC.

This pin is for Extension FDD A and B; the function of this pin is the

same as the

PRINTER MODE:

pin of FDC.

An active low input on this pin indicates that the printer has

received data and is ready to accept more data. This pin is pulled

high internally. Refer to description of the parallel port for

definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE:

This pin is for the Extension FDD B; its functions is the same as the

pin of FDC.

EXTENSION 2FDD MODE:

This pin is for Extension FDD A and B; it functions is the same as

the

PRINTER MODE:

pin of FDC.

An active low input on this pin indicates that the printer has

encountered an error condition. This pin is pulled high internally.

Refer to description of the parallel port for definition of this pin in

ECP and EPP mode.

EXTENSION FDD MODE:

This pin is for Extension FDD B; its function is the same as the

pin of FDC.

EXTENSION 2FDD MODE:

This pin is for Extension FDD A and B; its function is the same as

the

pin of FDC.

PRELIMINARY

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W83977TF

SLIN

STEP

INIT

DIR2

DIR

DIR2

DIR

AFD

1.5 Multi-Mode Parallel Port, continued

SYMBOL PIN I/O FUNCTION

32 OD

33 OD

35 OD

PRINTER MODE: Output line for detection of printer selection. This pin is pulled high

internally. Refer to description of the parallel port for definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE:

This pin is for Extension FDD B; its function is the same as the

pin of FDC.

EXTENSION 2FDD MODE:

This pin is for Extension FDD A and B; its function is the same as the

PRINTER MODE:

pin of FDC.

Output line for the printer initialization. This pin is pulled high internally. Refer to description of the parallel port for definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE:

This pin is for Extension FDD B; its function is the same as the pin of FDC.

EXTENSION 2FDD MODE:

This pin is for Extension FDD A and B; its function is the same as the

PRINTER MODE:

pin of FDC.

An active low output from this pin causes the printer to auto feed a line after a line is printed. This pin is pulled high internally. Refer to description of the parallel port for definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: DRVDEN0

This pin is for Extension FDD B; its function is the same as the DRVDEN0 pin of FDC.

EXTENSION 2FDD MODE: DRVDEN0

This pin is for Extension FDD A and B; its function is the same as the DRVDEN0 pin of FDC.

PRELIMINARY

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W83977TF

STB

INDEX

TRAK

WP2

1.5 Multi-Mode Parallel Port, continued

SYMBOL PIN I/O FUNCTION

36 OD

PRINTER MODE:

An active low output is used to latch the parallel data into the

printer. This pin is pulled high internally. Refer to description of the

parallel port for definition of this pin in ECP and EPP mode.

PD0

31 I/O

- EXTENSION FDD MODE: This pin is a tri-state output.

- EXTENSION 2FDD MODE: This pin is a tri-state output. PRINTER MODE: PD0

24t

Parallel port data bus bit 0. Refer to description of the parallel port for definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: This pin is for Extension FDD B; the function of this pin is the same

as the

EXTENSION 2FDD MODE:

pin of FDC. It is pulled high internally.

This pin is for Extension FDD A and B; the function of this pin is the

PD1

same as the

30 I/O

PRINTER MODE: PD1

24t

Parallel port data bus bit 1. Refer to description of the parallel port for definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE:

This pin is for Extension FDD B; the function of this pin is the same as the

EXTENSION. 2FDD MODE:

pin of FDC. It is pulled high internally.

This pin is for Extension FDD A and B; the function of this pin is the

PD2

same as the

29 I/O

PRINTER MODE: PD2

24t

Parallel port data bus bit 2. Refer to description of the parallel port for definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE:

This pin is for Extension FDD B; the function of this pin is the same as the WP pin of FDC. It is pulled high internally.

EXTENSION. 2FDD MODE:

pin of FDC. It is pulled high internally.

This pin is for Extension FDD A and B; the function of this pin is the same as the WP pin of FDC. It is pulled high internally.

PRELIMINARY

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W83977TF

RDATA

DSKCHG

MOA2

MOA

1.5 Multi-Mode Parallel Port, continued

SYMBOL PIN I/O FUNCTION

PD3

28 I/O

24t

PRINTER MODE: PD3 Parallel port data bus bit 3. Refer to description of the parallel port

for definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: This pin is for Extension FDD B; the function of this pin is the same as the

EXTENSION 2FDD MODE:

pin of FDC. It is pulled high internally.

This pin is for Extension FDD A and B; this function of this pin is the

PD4

same as the

27 I/O

24t

PRINTER MODE: PD4 Parallel port data bus bit 4. Refer to description of the parallel port

for definition of this pin in ECP and EPP mode. EXTENSION FDD MODE:

This pin is for Extension FDD B; the function of this pin is the same as the

EXTENSION 2FDD MODE:

pin of FDC. It is pulled high internally.

This pin is for Extension FDD A and B; this function of this pin is the

PD5

PD6

same as the

26 I/O

24 I/O

PRINTER MODE: PD5

24t

Parallel port data bus bit 5. Refer to description of the parallel port for definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: This pin is a tri-state output.

PRINTER MODE: PD6

24t

Parallel port data bus bit 6. Refer to description of the parallel port for definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION. 2FDD MODE:

This pin is for Extension FDD A; its function is the same as the

pin of FDC. It is pulled high internally.

pin of FDC.

PRELIMINARY

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W83977TF

DSA2

DSA

SCI

HEAD

STEP

DIR

MOB

DSA

DSB

1.5 Multi-Mode Parallel Port, continued

SYMBOL PIN I/O FUNCTION

PD7

23 I/O

PRINTER MODE: PD7

24t

Parallel port data bus bit 7. Refer to description of the parallel port for definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: This pin is a tri-state output.

EXTENSION 2FDD MODE:

This pin is for Extension FDD A; its function is the same as the

pin of FDC.

1.6 FDC Interface

SYMBOL PIN I/O FUNCTION

DRVDEN0 2 OD DRVDEN1 GP10 (IRQIN1) P12

3 OD

IO Alternate Function from GP10: Interrupt channel input. IO OUT

5 OD

9 OD

10 OD

11 OD

12 OD

13 OD

14 OD

15 OD

Drive Density Select bit 0.

Drive Density Select bit 1. (CR2A bit 1_0 = 00, default)

General purpose I/O port 1 bit 0. (CR2A bit 1_0 = 01)

24t

KBC P12 I/O port. (CR2A bit 1_0 = 10)

24t

System Control Interrupt (CR2A bit 1_0 = 11)

12t

Head select. This open drain output determines which disk drive

head is active. Logic 1 = side 0 Logic 0 = side 1

Write enable. An open drain output.

Write data. This logic low open drain writes pre-compensation

serial data to the selected FDD. An open drain output. Step output pulses. This active low open drain output produces a

pulse to move the head to another track. Direction of the head step motor. An open drain output.

Logic 1 = outward motion Logic 0 = inward motion Motor B On. When set to 0, this pin enables disk drive 1. This is

an open drain output. Drive Select A. When set to 0, this pin enables disk drive A. This

is an open drain output. Drive Select B. When set to 0, this pin enables disk drive B. This

is an open drain output.

PRELIMINARY

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W83977TF

MOA

DSKCHG

RDATA

TRAK0

INDEX

1.6 FDC Interface, continued

SYMBOL PIN I/O FUNCTION

Motor A On. When set to 0, this pin enables disk drive 0. This is

an open drain output. Diskette change. This signal is active low at power on and

whenever the diskette is removed. This input pin is pulled up

16 OD

4 IN

internally by a 1 KΩ resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN).

6 IN

The read data input signal from the FDD. This input pin is pulled

up internally by a 1 KΩ resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN).

7 IN

Write protected. This active low Schmitt input from the disk drive

indicates that the diskette is write-protected. This input pin is pulled up internally by a 1 KΩ resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN).

8 IN

Track 0. This Schmitt-triggered input from the disk drive is active

low when the head is positioned over the outermost track. This input pin is pulled up internally by a 1 KΩ resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN).

17 IN

This Schmitt-triggered input from the disk drive is active low when

the head is positioned over the beginning of a track marked by an index hole. This input pin is pulled up internally by a 1 KΩ resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN).

PRELIMINARY

1.7 KBC Interface

SYMBOL PIN I/O FUNCTION

KDATA 59 I/OD MDATA 60 I/OD KCLK 67 I/OD MCLK 68 I/OD GA20 56 I/O GP11 I/O

(IRQIN2) Alternate Function from GP11: Interrupt channel input.

KBRST 57 I/O GP12 I/O

(WDTO) Alternate Function 1 from GP12 : Watchdog timer output.

Keyboard Data

16u

PS2 Mouse Data

16u

Keyboard Clock

16u

PS2 Mouse Clock

16u

KBC GATE A20 (P21) Output. (CR2A bit 6 = 0, default)

12t

General purpose I/O port 1 bit 1. (CR2A bit 6 = 1)

12t

W83C45 Keyboard Reset (P20) Output. (CR2A bit 7 = 0, default)

12t

General purpose I/O port 1 bit 2. (CR2A bit 7 = 1)

12t

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W83977TF

1.7 KBC Interface, continued

SYMBOL PIN I/O FUNCTION

KBLOCK 58 IN GP13 I/O

W83C45 KINH (P17) Input. (CR2B bit 0 = 0, default)

General purpose I/O port 1 bit 3. (CR2B bit 0 = 1)

16t

1.8 POWER PINS

SYMBOL PIN FUNCTION

VCC 20, 55, 85,

115 VSB 71 +5V stand-by power supply for the digital circuitry

GND 25, 62, 90,

120

+5V power supply for the digital circuitry

Ground

1.9 ACPI Interface

SYMBOL PIN I/O FUNCTION

VBAT 64 NA XTAL1 63 IN XTAL2 61 O

battery voltage input

32.768Khz Clock Input

32.768Khz Clock Output

PRELIMINARY

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W83977TF

PRELIMINARY

2. FDC FUNCTIONAL DESCRIPTION

2.1 W83977TF FDC

The floppy disk controller of the W83977TF integrates all of the logic required for floppy disk control. The FDC implements a PC/AT or PS/2 solution. All programmable options default to compatible values. The FIFO provides better system performance in multi-master systems. The digital data separator supports up to 2 M bits/sec data rate.

The FDC includes the following blocks: AT interface, Precompensation, Data Rate Selection, Digital Data Separator, FIFO, and FDC Core.

2.1.1 AT interface

The interface consists of the standard asynchronous signals: RD, WR, A0-A3, IRQ, DMA control, and a data bus. The address lines select between the configuration registers, the FIFO and control/status registers. This interface can be switched between PC/AT, Model 30, or PS/2 normal modes. The PS/2 register sets are a superset of the registers found in a PC/AT.

2.1.2 FIFO (Data)

The FIFO is 16 bytes in size and has programmable threshold values. All command parameter information and disk data transfers go through the FIFO. Data transfers are governed by the RQM and DIO bits in the Main Status Register.

The FIFO defaults to disabled mode after any form of reset. This maintains PC/AT hardware compatibility. The default values can be changed through the CONFIGURE command. The advantage of the FIFO is that it allows the system a larger DMA latency without causing disk errors. The following tables give several examples of the delays with a FIFO. The data are based upon the following formula:

THRESHOLD # × (1/DATA/RATE) *8 - 1.5 µS = DELAY

FIFO THRESHOLD MAXIMUM DELAY TO SERVICING AT 500K BPS

1 Byte 2 Byte 8 Byte

15 Byte

FIFO THRESHOLD MAXIMUM DELAY TO SERVICING AT 1M BPS

Data Rate

1 Byte 2 Byte 8 Byte

15 Byte

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Data Rate

1 × 16 µS - 1.5 µS = 14.5 µS 2 × 16 µS - 1.5 µS = 30.5 µS 8 × 16 µS - 1.5 µS = 6.5 µS 15 × 16 µS - 1.5 µS = 238.5 µS

1 × 8 µS - 1.5 µS = 6.5 µS 2 × 8 µS - 1.5 µS = 14.5 µS 8 × 8 µS - 1.5 µS = 62.5 µS 15 × 8 µS - 1.5 µS = 118.5 µS

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W83977TF

DACK

PRELIMINARY

At the start of a command the FIFO is always disabled and command parameters must be sent based upon the RQM and DIO bit settings in the main status register. When the FDC enters the command execution phase, it clears the FIFO of any data to ensure that invalid data are not transferred.

An overrun and underrun will terminate the current command and the data transfer. Disk writes will complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result phase may be entered.

DMA transfers are enabled with the SPECIFY command and are initiated by the FDC by activating the DRQ pin during a data transfer command. The FIFO is enabled directly by asserting

addresses need not be valid. Note that if the DMA controller is programmed to function in verify mode a pseudo read is performed by

the FDC based only on mode (FIFO disabled) and is programmed to do a read. With the FIFO enabled the above operation is performed by using the new VERIFY command. No DMA operation is needed.

2.1.3 Data Separator

The function of the data separator is to lock onto the incoming serial read data. When a lock is achieved the serial front end logic of the chip is provided with a clock which is synchronized to the read data. The synchronized clock, called the Data Window, is used to internally sample the serial data portion of the bit cell, and the alternate state samples the clock portion. Serial to parallel conversion logic separates the read data into clock and data bytes.

The Digital Data Separator (DDS) has three parts: control logic, error adjustment, and speed tracking. The DDS circuit cycles once every 12 clock cycles ideally. Any data pulse input will be synchronized and then adjusted by immediate error adjustment. The control logic will generate RDD and RWD for every pulse input. During any cycle where no data pulse is present, the DDS cycles are based on speed. A digital integrator is used to keep track of the speed changes in the input data stream.

. This mode is only available when the FDC has been configured into byte

and

2.1.4 Write Precompensation

The write precompensation logic is used to minimize bit shifts in the RDDATA stream from the disk drive. Shifting of bits is a known phenomenon in magnetic media and is dependent on the disk media and the floppy drive.

The FDC monitors the bit stream that is being sent to the drive. The data patterns that require precompensation are well known. Depending upon the pattern, the bit is shifted either early or late relative to the surrounding bits.

2.1.5 Perpendicular Recording Mode

The FDC is also capable of interfacing directly to perpendicular recording floppy drives. Perpendicular recording differs from the traditional longitudinal method in that the magnetic bits are oriented vertically. This scheme packs more data bits into the same area.

FDCs with perpendicular recording drives can read standard 3.5" floppy disks and can read and write perpendicular media. Some manufacturers offer drives that can read and write standard and perpendicular media in a perpendicular media drive.

A single command puts the FDC into perpendicular mode. All other commands operate as they normally do. The perpendicular mode requires a 1 Mbps data rate for the FDC. At this data rate the FIFO eases the host interface bottleneck due to the speed of data transfer to or from the disk.

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W83977TF

PRELIMINARY

2.1.6 FDC Core

The W83977TF FDC is capable of performing twenty commands. Each command is initiated by a multibyte transfer from the microprocessor. The result can also be a multi-byte transfer back to the microprocessor. Each command consists of three phases: command, execution, and result.

Command The microprocessor issues all required information to the controller to perform a specific operation. Execution The controller performs the specified operation. Result After the operation is completed, status information and other housekeeping information is provided to

the microprocessor.

2.1.7 FDC Commands

Command Symbol Descriptions: C: Cylinder number 0 - 256 D: Data Pattern DIR: Step Direction DIR = 0, step out DIR = 1, step in DS0: Disk Drive Select 0 DS1: Disk Drive Select 1 DTL: Data Length EC: Enable Count EOT: End of Track EFIFO: Enable FIFO EIS: Enable Implied Seek EOT: End of track FIFOTHR: FIFO Threshold GAP: Gap length selection GPL: Gap Length H: Head number HDS: Head number select HLT: Head Load Time HUT: Head Unload Time LOCK: Lock EFIFO, FIFOTHR, PTRTRK bits prevent affected by software reset MFM: MFM or FM Mode MT: Multitrack N: The number of data bytes written in a sector NCN: New Cylinder Number ND: Non-DMA Mode OW: Overwritten PCN: Present Cylinder Number POLL: Polling Disable PRETRK: Precompensation Start Track Number

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W83977TF

PRELIMINARY

R: Record RCN: Relative Cylinder Number R/W: Read/Write SC: Sector/per cylinder SK: Skip deleted data address mark SRT: Step Rate Time ST0: Status Register 0 ST1: Status Register 1 ST2: Status Register 2 ST3: Status Register 3 WG: Write gate alters timing of WE

(1) Read Data

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W MT MFM SK 0 0 1 1 0 Command codes

Execution Data transfer between the

Result R

W 0 0 0 0 0 HDS DS1 DS0 W

R R

R R R

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

-------------------- EOT -----------------------

-------------------- GPL -----------------------

-------------------- DTL -----------------------

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID information prior to command execution

FDD and system Status information after

command execution

Sector ID information after command execution

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W83977TF

W W

PRELIMINARY

(2) Read Deleted Data

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W MT MFM SK 0 1 1 0 0 Command codes

Execution Data transfer between the

Result R

W 0 0 0 0 0 HDS DS1 DS0

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

-------------------- EOT -----------------------

-------------------- GPL -----------------------

-------------------- DTL -----------------------

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

Sector ID information prior to command execution

FDD and system Status information after

command execution

R R R

-------------------- ST2 -----------------------

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID information after command execution

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PRELIMINARY

(3) Read A Track

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 MFM 0 0 0 0 1 0 Command codes

W 0 0 0 0 0 HDS DS1 DS0 W

Execution

Result R

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

-------------------- EOT -----------------------

-------------------- GPL -----------------------

-------------------- DTL ----------------------- Data transfer between the

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

Sector ID information prior to command execution

FDD and system; FDD reads contents of all cylinders from index hole to EOT

Status information after command execution

R R R

-------------------- ST2 -----------------------

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID information after command execution

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PRELIMINARY

(4) Read ID

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 MFM 0 0 1 0 1 0 Command codes W 0 0 0 0 0 HDS DS1 DS0

Execution

Result R

(5) Verify

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

R R

R R R

The first correct ID

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

information on the cylinder is stored in Data Register

Status information after command execution

Disk status after the command has been completed

Command W MT MFM SK 1 0 1 1 0 Command codes

W EC 0 0 0 0 HDS DS1 DS0 W

-------------------- DTL/SC -------------------

Execution No data transfer takes

Result R

R R

R R R

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

-------------------- EOT -----------------------

-------------------- GPL -----------------------

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID information prior to command execution

place Status information after

command execution

Sector ID information after command execution

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W83977TF

W W

PRELIMINARY

(6) Version

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 1 0 0 0 0 Command code Result R 1 0 0 1 0 0 0 0 Enhanced controller

(7) Write Data

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W MT MFM 0 0 0 1 0 1 Command codes

W 0 0 0 0 0 HDS DS1 DS0 W

Execution Data transfer between the

Result R

R R

R R R

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

-------------------- EOT -----------------------

-------------------- GPL -----------------------

-------------------- DTL -----------------------

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID information prior to Command execution

FDD and system Status information after

Command execution

Sector ID information after Command execution

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PRELIMINARY

(8) Write Deleted Data

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W MT MFM 0 0 1 0 0 1 Command codes

W 0 0 0 0 0 HDS DS1 DS0 W

Execution Data transfer between the

Result R

W W

R R

R R R

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

-------------------- EOT -----------------------

-------------------- GPL -----------------------

-------------------- DTL -----------------------

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID information prior to command execution

FDD and system Status information after

command execution

Sector ID information after command execution

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W83977TF

PRELIMINARY

(9) Format A Track

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 MFM 0 0 1 1 0 1 Command codes

W 0 0 0 0 0 HDS DS1 DS0 W

Execution for Each Sector Repeat:

Result R

W W W

R R

R R R

---------------------- N ------------------------

--------------------- SC -----------------------

--------------------- GPL ---------------------

---------------------- D ------------------------

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

---------------- Undefined -------------------

Bytes/Sector Sectors/Cylinder Gap 3 Filler Byte Input Sector Parameters

Status information after command execution

(10) Recalibrate

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 0 1 1 1 Command codes W 0 0 0 0 0 0 DS1 DS0

Execution Head retracted to Track 0

Interrupt

(11) Sense Interrupt Status

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 1 0 0 0 Command code Result

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R R

---------------- ST0 -------------------------

---------------- PCN -------------------------

Status information at the end of each seek operation

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W83977TF

PRELIMINARY

(12) Specify

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 0 0 1 1 Command codes

(13) Seek

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 1 1 1 1 Command codes W W 0 0 0 0 0 HDS DS1 DS0

Execution R Head positioned over proper

(14) Configure

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

W W | ---------SRT ----------- | --------- HUT ---------- |

|------------ HLT ----------------------------------| ND

-------------------- NCN -----------------------

cylinder on diskette

Command W 0 0 0 1 0 0 1 1 Configure information W

Execution Internal registers written

(15) Relative Seek

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 1 DIR 0 0 1 1 1 1 Command codes

0 0 0 0 0 0 0 0 W W

W W

0 EIS EFIFO POLL | ------ FIFOTHR ----|

| --------------------PRETRK ----------------------- |

0 0 0 0 0 HDS DS1 DS0

| -------------------- RCN ---------------------------- |

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PRELIMINARY

(16) Dumpreg

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 1 1 1 0 Registers placed in FIFO Result

(17) Perpendicular Mode

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 1 0 0 1 0 Command Code W OW 0 D3 D2 D1 D0 GAP WG

R R R R R R R R R R

----------------------- PCN-Drive 0--------------------

----------------------- PCN-Drive 1 -------------------

----------------------- PCN-Drive 2--------------------

----------------------- PCN-Drive 3 -------------------

--------SRT ------------------ | --------- HUT --------

----------- HLT -----------------------------------| ND

------------------------ SC/EOT ---------------------LOCK 0 D3 D2 D1 D0 GAP WG

0 EIS EFIFO POLL | ------ FIFOTHR --------

-----------------------PRETRK -------------------------

(18) Lock

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W LOCK 0 0 1 0 1 0 0 Command Code Result R 0 0 0 LOCK 0 0 0 0

(19) Sense Drive Status

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 0 1 0 0 Command Code W 0 0 0 0 0 HDS DS1 DS0

Result

(20) Invalid

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W ------------- Invalid Codes ----------------- Invalid codes (no operation-

Result R

---------------- ST3 ------------------------- Status information about

-------------------- ST0 ----------------------

disk drive

FDC goes to standby state) ST0 = 80H

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W83977TF

DRV2

STEP

TRAK

PRELIMINARY

2.2 Register Descriptions

There are several status, data, and control registers in W83977TF. These registers are defined below:

ADDRESS REGISTER

OFFSET READ WRITE

base address + 0 base address + 1 base address + 2 base address + 3 base address + 4 MS REGISTER DR REGISTER base address + 5 DT (FIFO) REGISTER DT (FIFO) REGISTER base address + 7 DI REGISTER CC REGISTER

2.2.1 Status Register A (SA Register) (Read base address + 0)

This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode, the bit definitions for this register are as follows:

SA REGISTER

SB REGISTER

TD REGISTER

34567

DO REGISTER

TD REGISTER

INIT PENDING (Bit 7): This bit indicates the value of the floppy disk interrupt output.

(Bit 6): 0 A second drive has been installed 1 A second drive has not been installed

STEP (Bit 5): This bit indicates the complement of

(Bit 4):

This bit indicates the value of HEAD (Bit 3):

output.

input.

DIR

WP INDEX HEAD TRAK0

STEP DRV2

INIT PENDING

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HEAD

INDEX

INIT PENDING

STEP

TRAK

HEAD

This bit indicates the complement of

output. 0 side 0 1 side 1

(Bit 2):

This bit indicates the value of

output.

(Bit 1): 0disk is write-protected 1disk is not write-protected

DIR (Bit 0) This bit indicates the direction of head movement. 0 outward direction 1 inward direction

In PS/2 Model 30 mode, the bit definitions for this register are as follows:

34567

PRELIMINARY

INIT PENDING (Bit 7): This bit indicates the value of the floppy disk interrupt output.

DRQ (Bit 6): This bit indicates the value of DRQ output pin. STEP F/F (Bit 5):

This bit indicates the complement of latched TRAK0 (Bit 4):

This bit indicates the complement of

(Bit 3):

This bit indicates the value of

output. 0 side 1 1 side 0

input.

output.

DIR

WP INDEX

HEAD TRAK0 STEP F/F

DRQ

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W83977TF

INDEX

DIR

RDATA

MOB

MOA

PRELIMINARY

INDEX (Bit 2): This bit indicates the complement of

WP (Bit 1): 0 disk is not write-protected 1 disk is write-protected

(Bit 0) This bit indicates the direction of head movement. 0 inward direction 1 outward direction

2.2.2 Status Register B (SB Register) (Read base address + 1)

This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode, the bit definitions for this register are as follows:

output.

34567

MOT EN A MOT EN B

WE RDATA Toggle

WDATA Toggle

Drive SEL0

Drive SEL0 (Bit 5): This bit indicates the status of DO REGISTER bit 0 (drive select bit 0).

WDATA Toggle (Bit 4): This bit changes state at every rising edge of the WD output pin.

RDATA Toggle (Bit 3): This bit changes state at every rising edge of the

output pin.

WE (Bit 2): This bit indicates the complement of the WE output pin.

MOT EN B (Bit 1) This bit indicates the complement of the

output pin.

MOT EN A (Bit 0) This bit indicates the complement of the

output pin.

In PS/2 Model 30 mode, the bit definitions for this register are as follows:

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W83977TF

DRV2

DSB

DSA

RDATA

DSD

DSC

(Bit 7): 0 A second drive has been installed 1 A second drive has not been installed

(Bit 6):

This bit indicates the status of

output pin.

(Bit 5):

This bit indicates the status of

output pin.

WD F/F(Bit 4):

PRELIMINARY

34567

DSC DSD

WE F/F RDATA F/F

WD F/F

DSA DSB

This bit indicates the complement of the latched WD output pin at every rising edge of the WD output pin.

RDATA F/F(Bit 3): This bit indicates the complement of the latched

output pin .

WE F/F (Bit 2): This bit indicates the complement of latched WE output pin.

(Bit 1): 0 Drive D has been selected 1 Drive D has not been selected

(Bit 0): 0 Drive C has been selected 1 Drive C has not been selected

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W83977TF

PRELIMINARY

2.2.3 Digital Output Register (DO Register) (Write base address + 2)

The Digital Output Register is a write-only register controlling drive motors, drive selection, DRQ/IRQ enable, and FDC resetting. All the bits in this register are cleared by the MR pin. The bit definitions are as follows:

7 6

5 4

2.2.4 Tape Drive Register (TD Register) (Read base address + 3)

This register is used to assign a particular drive number to the tape drive support mode of the data separator. This register also holds the media ID, drive type, and floppy boot drive information of the floppy disk drive. In normal floppy mode, this register includes only bit 0 and 1. The bit definitions are as follows:

X X

X X X X

1-0

Drive Select: 00 select drive A

Floppy Disk Controller Reset Active low resets FDC DMA and INT Enable Active high enable DRQ/IRQ Motor Enable A. Motor A on when active high Motor Enable B. Motor B on when active high Motor Enable C. Motor C on when active high Motor Enable D. Motor D on when active high

34567

01 select drive B 10 select drive C 11 select drive D

Tape sel 0

Tape sel 1

If three mode FDD function is enabled (EN3MODE = 1 in Logical Device 0 CRF0 bit:0), the bit definitions are as follows:

34567

Tape Sel 0

Tape Sel 1

Floppy boot drive 0 Floppy boot drive 1 Drive type ID0

Drive type ID1 Media ID0 Media ID1

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PRELIMINARY

Media ID1 Media ID0 (Bit 7, 6): These two bits are read only. These two bits reflect the value of Logical Device 0 CRF1 bit 4,5.

Drive type ID1 Drive type ID0 (Bit 5, 4): These two bits reflect two of the bits of Logical Device 0 CRF2. Which two bits are reflected depends on

the last drive selected in the DO REGISTER. Floppy Boot drive 1, 0 (Bit 3, 2):

These two bits reflect the value of Logical Device 0 CRF1 bit 7,6. Tape Sel 1, Tape Sel 0 (Bit 1, 0):

These two bits assign a logical drive number to the tape drive. Drive 0 is not available as a tape drive and is reserved as the floppy disk boot drive.

TAPE SEL 1 TAPE SEL 0 DRIVE SELECTED

0 0 None 0 1 1 1 0 2 1 1 3

2.2.5 Main Status Register (MS Register) (Read base address + 4)

The Main Status Register is used to control the flow of data between the microprocessor and the controller. The bit definitions for this register are as follows:

5 4 3 2 1

FDD 0 Busy, (D0B = 1), FDD number 0 is in the SEEK mode. FDD 1 Busy, (D1B = 1), FDD number 1 is in the SEEK mode. FDD 2 Busy, (D2B = 1), FDD number 2 is in the SEEK mode. FDD 3 Busy, (D3B = 1), FDD number 3 is in the SEEK mode.

FDC Busy, (CB). A read or write command is in the process when CB = HIGH. Non-DMA mode, the FDC is in the non-DMA mode, this bit is set only during the execution phase in non-DMA mode. Transition to LOW state indicates execution phase has ended. DATA INPUT/OUTPUT, (DIO). If DIO= HIGH then transfer is from Data Register to the processor.

If DIO = LOW then transfer is from processor to Data Register.

Request for Master (RQM). A high on this bit indicates Data Register is ready to send or receive data to or from the processor.

2.2.6 Data Rate Register (DR Register) (Write base address + 4)

The Data Rate Register is used to set the transfer rate and write precompensation. The data rate of the FDC is programmed by the CC REGISTER for PC-AT and PS/2 Model 30 and PS/2 mode, and not by the DR REGISTER. The real data rate is determined by the most recent write to either of the DR REGISTER or CC REGISTER.

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POWER DOWN

PRELIMINARY

34567

S/W RESET (Bit 7): This bit is the software reset bit.

POWER-DOWN (Bit 6): 0 FDC in normal mode 1 FDC in power-down mode

PRECOMP2 PRECOMP1 PRECOMP0 (Bit 4, 3, 2): These three bits select the value of write precompensation. The following tables show the

precompensation values for the combination of these bits.

PRECOMP

2 1 0

250K - 1 Mbps 2 Mbps Tape drive 0 0 0 Default Delays Default Delays 0 0 1 41.67 nS 20.8 nS 0 1 0 83.34 nS 41.17 nS 0 1 1 125.00 nS 62.5nS 1 0 0 166.67 nS 83.3 nS 1 0 1 208.33 nS 104.2 nS 1 1 0 250.00 nS 125.00 nS 1 1 1 0.00 nS (disabled) 0.00 nS (disabled)

DRATE0 DRATE1 PRECOMP0

PRECOMP1 PRECOMP2

S/W RESET

PRECOMPENSATION DELAY

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RWC

11 Abnormal termination because the ready signal from FDD changed state during command execution

PRELIMINARY

DATA RATE DEFAULT PRECOMPENSATION DELAYS

250 KB/S 125 nS 300 KB/S 125 nS 500 KB/S 125 nS

1 MB/S 41.67nS 2 MB/S 20.8 nS

DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC and reduced write current control.

00 500 KB/S (MFM), 250 KB/S (FM), 01 300 KB/S (MFM), 150 KB/S (FM), 10 250 KB/S (MFM), 125 KB/S (FM), 11 1 MB/S (MFM), Illegal (FM),

The 2 MB/S data rate for Tape drive is only supported by setting 01 to DRATE1 and DRATE0 bits, as well as setting 10 to DRT1 and DRT0 bits which are two of the Configure Register CRF4 or CRF5 bits in logic device 0. Please refer to the function description of CRF4 or CRF5 and data rate table for individual data rates setting.

2.2.7 FIFO Register (R/W base address + 5)

The Data Register consists of four status registers in a stack with only one register presented to the data bus at a time. This register stores data, commands, and parameters and provides diskette-drive status information. Data bytes are passed through the data register to program or obtain results after a command. In the W83977TF, this register defaults to FIFO disabled mode after reset. The FIFO can change its value and enable its operation through the CONFIGURE command.

Status Register 0 (ST0)

7-6 5

3 2 1-0

= 1 = 0 = 0

= 1

US1, US0 Drive Select:

00 Drive A selected 01 Drive B selected 10 Drive C selected 11 Drive D selected

HD Head address:

1 Head selected 0 Head selected

NR Not Ready:

1 Drive is not ready 0 Drive is ready

EC Equipment Check:

1 When a fault signal is received from the FDD or the track 0 signal fails to occur after 77 step pulses 0 No error

SE Seek end:

1 seek end 0 seek error

IC Interrupt Code:

00 Normal termination of command 01 Abnormal termination of command 10 Invalid command issue

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W83977TF

1 During execution of the Scan command, if the equal condition is satisfied

WP Write Protected

Status Register 1 (ST1)

Status Register 2 (ST2)

7 0

PRELIMINARY

234567

Missing Address Mark. 1 When the FDC cannot detect the data address mark or the data address mark has been deleted.

NW (Not Writable). 1 If a write Protect signal is detected from the diskette drive during execution of write data.

ND (No DATA). 1 If specified sector cannot be found during execution of a read, write or verifly data. Not used. This bit is always 0. OR (Over Rum). 1 If the FDC is not serviced by the host system within a certain time interval during data transfer. DE (data Error).1 When the FDC detects a CRC error in either the ID field or the data field.

Not used. This bit is always 0.

EN (End of track). 1 When the FDC tries to access a sector beyond the final sector of a cylinder.

234

MD (Missing Address Mark in Data Field). 1 If the FDC cannot find a data address mark (or the address mark has been deleted) when reading data from the media 0 No error BC (Bad Cylinder) 1 Bad Cylinder 0 No error SN (Scan Not satisfied) 1 During execution of the Scan command 0 No error SH (Scan Equal Hit)

0 No error WC (Wrong Cylinder) 1 Indicates wrong Cylinder

DD (Data error in the Data field)

1 If the FDC detects a CRC error in the data field

0 No error CM (Control Mark) 1 During execution of the read data or scan command 0 No error Not used. This bit is always 0

Status Register 3 (ST3)

US0 Unit Select 0 US1 Unit Select 1 HD Head Address TS Two-Side TO Track 0 RY Ready

FT Fault

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W83977TF

DSKCHG

During a read of this register, these bits are in tri-state

DSKCHG

HIGH DENS

34567

PRELIMINARY

2.2.8 Digital Input Register (DI Register) (Read base address + 7)

The Digital Input Register is an 8-bit read-only register used for diagnostic purposes. In a PC/XT or AT only Bit 7 is checked by the BIOS. When the register is read, Bit 7 shows the complement of

while other bits of the data bus remain in tri-state. Bit definitions are as follows:

567

xxx

In the PS/2 mode, the bit definitions are as follows:

1 111

DSKCHG (Bit 7): This bit indicates the complement of the Bit 6-3: These bits are always a logic 1 during a read.

DRATE1 DRATE0 (Bit 2, 1): These two bits select the data rate of the FDC. Refer to the DR register bits 1 and 0 for the settings

corresponding to the individual data rates.

(Bit 0): 0 500 KB/S or 1 MB/S data rate (high density FDD) 1 250 KB/S or 300 KB/S data rate

In the PS/2 Model 30 mode, the bit definitions are as follows:

0 00

01234

xxx

Reserved for the hard disk controller

DSKCHG

34567

input.

HIGH DENS

DRATE0

DRATE1

DSKCHG (Bit 7):

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DRATE0

DRATE1

NOPREC DMAEN

DSKCHG

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W83977TF

DSKCHG

PRELIMINARY

This bit indicates the status of Bit 6-4: These bits are always a logic 1 during a read.

DMAEN (Bit 3): This bit indicates the value of DO REGISTER bit 3.

NOPREC (Bit 2): This bit indicates the value of CC REGISTER NOPREC bit.

DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC.

2.2.9 Configuration Control Register (CC Register) (Write base address + 7)

This register is used to control the data rate. In the PC/AT and PS/2 mode, the bit definitions are as follows:

input.

x x x x x x

DRATE0

X: Reserved

Bit 7-2: Reserved. These bits should be set to 0. DRATE1 DRATE0 (Bit 1, 0):

These two bits select the data rate of the FDC. In the PS/2 Model 30 mode, the bit definitions are as follows:

X X

34567

X X X

DRATE1

DRATE0

DRATE1

NOPREC

X: Reserved Bit 7-3: Reserved. These bits should be set to 0.

NOPREC (Bit 2): This bit indicates no precompensation. It has no function and can be set by software.

DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC.

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W83977TF

PRELIMINARY

3. UART PORT

3.1 Universal Asynchronous Receiver/Transmitter (UART A, UART B)

The UARTs are used to convert parallel data into serial format on the transmit side and convert serial data to parallel format on the receiver side. The serial format, in order of transmission and reception, is a start bit, followed by five to eight data bits, a parity bit (if programmed) and one, one and half (five-bit format only) or two stop bits. The UARTs are capable of handling divisors of 1 to 65535 and producing a 16x clock for driving the internal transmitter logic. Provisions are also included to use this 16x clock to drive the receiver logic. The UARTs also support the MIDI data rate. Furthermore, the UARTs also include complete modem control capability and a processor interrupt system that may be software trailed to the computing time required to handle the communication link. The UARTs have a FIFO mode to reduce the number of interrupts presented to the CPU. In each UART, there are 16-byte FIFOs for both receive and transmit mode.

3.2 Register Address

3.2.1 UART Control Register (UCR) (Read/Write)

The UART Control Register controls and defines the protocol for asynchronous data communications, including data length, stop bit, parity, and baud rate selection.

7 0

Data length select bit 0 (DLS0) Data length select bit 1(DLS1) Multiple stop bits enable (MSBE) Parity bit enable (PBE) Even parity enable (EPE) Parity bit fixed enable (PBFE) Set silence enable (SSE) Baudrate divisor latch access bit (BDLAB)

Bit 7: BDLAB. When this bit is set to a logical 1, designers can access the divisor (in 16-bit binary format)

from the divisor latches of the baudrate generator during a read or write operation. When this bit is reset, the Receiver Buffer Register, the Transmitter Buffer Register, or the Interrupt Control Register can be accessed.

Bit 6: SSE. A logical 1 forces the Serial Output (SOUT) to a silent state (a logical 0). Only IRTX is

affected by this bit; the transmitter is not affected.

Bit 5: PBFE. When PBE and PBFE of UCR are both set to a logical 1,

(1) if EPE is logical 1, the parity bit is fixed as logical 0 to transmit and check. (2) if EPE is logical 0, the parity bit is fixed as logical 1 to transmit and check.

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PRELIMINARY

TABLE 3-1 UART Register Bit Map

W83977TF

+ 0

BDLAB = 0

+ 0

BDLAB = 0

+ 1

BDLAB = 0

+ 2 Interrupt Status

+ 2 UART FIFO

+ 3 UART Control

+ 4 Handshake

+ 5 UART Status

+ 6 Handshake

+ 7 User Defined

+ 0

BDLAB = 1

+ 1

BDLAB = 1

Receiver

(Read Only) Transmitter

Buffer Register

(Write Only)

Interrupt

Control

(Read Only)

Control

(Write Only)

Control

Status Register

Baudrate

Divisor Latch

Baudrate

Divisor Latch

*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received. **: These bits are always 0 in 16450 Mode.

Buffer

Low

High

Bit Number

RBR

TBR

ICR

ISR

UFR

UCR

HCR

USR

HSR

UDR

BLL

BHL

0 1 2 3 4 5 6 7

RX Data

Bit 0

TX Data

Bit 0

RBR Data

Ready

Interrupt

Enable

(ERDRI)

"0" if Interrupt

Pending

FIFO

Enable

Data

Length

Select

Bit 0

(DLS0)

Data

Terminal

Ready (DTR)

RBR Data

Ready

(RDR)

CTS

Toggling

(TCTS)

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15

RX Data

Bit 1

TX Data

Bit 1

TBR

Empty

Interrupt

Enable

(ETBREI)

Interrupt

Status Bit (0)

RCVR

FIFO

Reset

Data

Length

Select

Bit 1

(DLS1)

Request

Send

(RTS)

Overrun

Error

(OER)

DSR

Toggling

(TDSR)

RX Data

Bit 2

TX Data

Bit 2

USR

Interrupt

Enable

(EUSRI)

Interrupt

Status Bit (1)

XMIT

FIFO

Reset

Multiple

Stop Bits

Enable

(MSBE)

Loopback

Input

Parity Bit

Error

(PBER)

RI Falling

Edge

(FERI)

RX Data

Bit 3

TX Data

Bit 3

HSR

Interrupt

Enable

(EHSRI) Interrupt

Status

Bit (2)**

DMA

Mode

Select

Parity

Bit

Enable

(PBE)

IRQ

Enable

No Stop

Bit

Error

(NSER)

DCD

Toggling

(TDCD)

RX Data

Bit 4

TX Data

Bit 4

0 0 0 0

0 0 FIFOs

Reserved Reversed RX

Even

Parity

Enable

(EPE)

Internal

Loopback

Enable

Silent

Byte

Detected

(SBD)

Clear

to Send

(CTS)

RX Data

Bit 5

TX Data

Bit 5

Parity

Bit Fixed

Enable PBFE)

0 0 0

TBR

Empty

(TBRE)

Data Set

Ready (DSR)

RX Data

Bit 6

TX Data

Bit 6

Enabled

Interrupt

Active Level

(LSB)

Set

Silence

Enable

(SSE)

TSR

Empty

(TSRE)

Ring

Indicator

(RI)

RX Data

Bit 7

TX Data

Bit 7

FIFOs

Enabled

Interrupt

Active Level

(MSB)

Baudrate

Divisor

Latch

Access Bit

(BDLAB)

RX FIFO

Error Indication (RFEI) **

Data Carrier

Detect (DCD)

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Bit 4: EPE. This bit describes the number of logic 1's in the data word bits and parity bit only when bit 3 is

programmed. When this bit is set, an even number of logic 1's are sent or checked. When the bit is reset, an odd number of logic 1's are sent or checked.

Bit 3: PBE. When this bit is set, the position between the last data bit and the stop bit of the SOUT will be

stuffed with the parity bit at the transmitter. For the receiver, the parity bit in the same position as the transmitter will be detected.

Bit 2: MSBE. This bit defines the number of stop bits in each serial character that is transmitted or

received. (1) If MSBE is set to a logical 0, one stop bit is sent and checked. (2) If MSBE is set to a logical 1, and data length is 5 bits, one and a half stop bits are sent and

checked.

(3) If MSBE is set to a logical 1, and data length is 6, 7, or 8 bits, two stop bits are sent and

Bits 0 and 1: DLS0, DLS1. These two bits define the number of data bits that are sent or checked in

TABLE 3-2 WORD LENGTH DEFINITION

checked.

each serial character.

DLS1 DLS0 DATA LENGTH

0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits

3.2.2 UART Status Register (USR) (Read/Write)

This 8-bit register provides information about the status of the data transfer during communication.

67 0

RBR Data ready (RDR) Overrun error (OER) Parity bit error (PBER) No stop bit error (NSER) Silent byte detected (SBD) Transmitter Buffer Register empty (TBRE)

Transmitter Shift Register empty (TSRE) RX FIFO Error Indication (RFEI)

Bit 7: RFEI. In 16450 mode, this bit is always set to a logic 0. In 16550 mode, this bit is set to a logic 1

when there is at least one parity bit error, no stop bit error or silent byte detected in the FIFO. In 16550 mode, this bit is cleared by reading from the USR if there are no remaining errors left in the FIFO.

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Bit 6: TSRE. In 16450 mode, when TBR and TSR are both empty, this bit will be set to a logical 1. In

16550 mode, if the transmit FIFO and TSR are both empty, it will be set to a logical 1. Other thanthese two cases, this bit will be reset to a logical 0.

Bit 5: TBRE. In 16450 mode, when a data character is transferred from TBR to TSR, this bit will be set to

a logical 1. If ETREI of ICR is a logical 1, an interrupt will be generated to notify the CPU to write the next data. In 16550 mode, this bit will be set to a logical 1 when the transmit FIFO is empty. It will be reset to a logical 0 when the CPU writes data into TBR or FIFO.

Bit 4: SBD. This bit is set to a logical 1 to indicate that received data are kept in silent state for a full word

time, including start bit, data bits, parity bit, and stop bits. In 16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a logical 0.

Bit 3: NSER. This bit is set to a logical 1 to indicate that the received data have no stop bit. In 16550

mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a logical 0.

Bit 2: PBER. This bit is set to a logical 1 to indicate that the parity bit of received data is wrong. In 16550

mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a logical 0.

Bit 1: OER. This bit is set to a logical 1 to indicate received data have been overwritten by the next

received data before they were read by the CPU. In 16550 mode, it indicates the same condition instead of FIFO full. When the CPU reads USR, it will clear this bit to a logical 0.

Bit 0: RDR. This bit is set to a logical 1 to indicate received data are ready to be read by the CPU in the

RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical 0.

3.2.3 Handshake Control Register (HCR) (Read/Write)

This register controls the pins of the UART used for handshaking peripherals such as modem, and controls the diagnostic mode of the UART.

345

Data terminal ready (DTR) Request to send (RTS) Loopback RI input IRQ enable

Internal loopback enable

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DSR

CTS

DCD

RTS

DTR

DCD

DSR

CTS

DCD

Bit 4: When this bit is set to a logical 1, the UART enters diagnostic mode by an internal loopback, as

follows:

(1) SOUT is forced to logical 1, and SIN is isolated from the communication link instead of the

TSR. (2) Modem output pins are set to their inactive state. (3) Modem input pins are isolated from the communication link and connect internally as DTR

(bit 0 of HCR) → RI and IRQ enable ( bit 3 of HCR) →

Aside from the above connections, the UART operates normally. This method allows the

CPU to test the UART in a convenient way.

Bit 3: The UART interrupt output is enabled by setting this bit to a logic 1. In the diagnostic mode this bit

is internally connected to the modem control input

Bit 2: This bit is used only in the diagnostic mode. In the diagnostic mode this bit is internally connected

to the modem control input RI.

, RTS ( bit 1 of HCR) →

, Loopback RI input ( bit 2 of HCR) →

Bit 1: This bit controls the Bit 0: This bit controls the

output. The value of this bit is inverted and output to output. The value of this bit is inverted and output to

. .

3.2.4 Handshake Status Register (HSR) (Read/Write)

This register reflects the current state of four input pins for handshake peripherals such as a modem and records changes on these pins.

1234567 0

toggling (TCTS)

CTS

toggling (TDSR)

DSR

RI falling edge (FERI)

toggling (TDCD)

DCD Clear to send (CTS) Data set ready (DSR) Ring indicator (RI)

Bit 7: This bit is the opposite of the

Data carrier detect (DCD)

input. This bit is equivalent to bit 3 of HCR in loopback mode.

Bit 6: This bit is the opposite of the RI input. This bit is equivalent to bit 2 of HCR in loopback mode. Bit 5: This bit is the opposite of the Bit 4: This bit is the opposite of the

input. This bit is equivalent to bit 0 of HCR in loopback mode. input. This bit is equivalent to bit 1 of HCR in loopback mode.

Bit 3: TDCD. This bit indicates that the

pin has changed state after HSR was read by the CPU.

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DSR

CTS

Bit 2: FERI. This bit indicates that the RI pin has changed from low to high state after HSR was read

by the CPU. Bit 1: TDSR. This bit indicates that the Bit 0: TCTS. This bit indicates that the

3.2.5 UART FIFO Control Register (UFR) (Write only)

This register is used to control the FIFO functions of the UART.

Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if the

interrupt active level is set as 4 bytes, once there are more than 4 data characters in the receiver

FIFO, the interrupt will be activated to notify the CPU to read the data from the FIFO.

TABLE 3-3 FIFO TRIGGER LEVEL

pin has changed state after HSR was read by the CPU.

pin has changed state after HSR was read.

34567 0

FIFO enable Receiver FIFO reset Transmitter FIFO reset

DMA mode select Reserved Reserved RX interrupt active level (LSB) RX interrupt active level (MSB)

BIT 7 BIT 6 RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)

0 0 01 0 1 04 1 0 08 1 1 14

Bit 4, 5: Reserved Bit 3: When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if

UFR bit 0 = 1. Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to initial state. This bit will clear to a

logical 0 by itself after being set to a logical 1. Bit 1: Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will clear to a

logical 0 by itself after being set to a logical 1. Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1 before

other bits of UFR are programmed.

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3.2.6 Interrupt Status Register (ISR) (Read only)

This register reflects the UART interrupt status, which is encoded by different interrupt sources into 3 bits.

1234567

0 0

0 if interrupt pending Interrupt Status bit 0

Interrupt Status bit 1 Interrupt Status bit 2 FIFOs enabled

FIFOs enabled

Bit 7, 6: These two bits are set to a logical 1 when UFR bit 0 = 1. Bit 5, 4: These two bits are always logic 0. Bit 3: In 16450 mode, this bit is 0. In 16550 mode, both bit 3 and 2 are set to a logical 1 when a time-out

interrupt is pending. Bit 2, 1: These two bits identify the priority level of the pending interrupt, as shown in the table below. Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred,

this bit will be set to a logical 0.

TABLE 3-4 INTERRUPT CONTROL FUNCTION

ISR INTERRUPT SET AND FUNCTION

Bit 3 Bit 2 Bit 1 Bit 0 Interrupt

priority

0 0 0 0 1 1 0 First UART Receive

0 1 0 0 Second RBR Data Ready 1. RBR data ready

1 1 0 0 Second FIFO Data Timeout Data present in RX FIFO for 4

0 0 1 0 Third TBR Empty TBR empty 1. Write data into TBR

0 0 0 0 Fourth Handshake status 1. TCTS = 1 2. TDSR = 1

** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.

Interrupt Type

- - No Interrupt pending -

Status

Interrupt Source

1. OER = 1 2. PBER =1

3. NSER = 1 4. SBD = 1

2. FIFO interrupt active level reached

characters period of time since last access of RX FIFO.

3. FERI = 1 4. TDCD = 1

Clear Interrupt

Read USR

1. Read RBR

2. Read RBR until FIFO data under active level

Read RBR

2. Read ISR (if priority is third)

Read HSR

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UART receive status interrupt enable (EUSRI)

Handshake status interrupt enable (EHSRI)

3.2.7 Interrupt Control Register (ICR) (Read/Write)

This 8-bit register allows the five types of controller interrupts to activate the interrupt output signal separately. The interrupt system can be totally disabled by resetting bits 0 through 3 of the Interrupt Control Register (ICR). A selected interrupt can be enabled by setting the appropriate bits of this register to a logical 1.

7 0

6 0 0 0

RBR data ready interrupt enable (ERDRI) TBR empty interrupt enable (ETBREI)

Bit 7-4: These four bits are always logic 0. Bit 3: EHSRI. Setting this bit to a logical 1 enables the handshake status register interrupt. Bit 2: EUSRI. Setting this bit to a logical 1 enables the UART status register interrupt. Bit 1: ETBREI. Setting this bit to a logical 1 enables the TBR empty interrupt. Bit 0: ERDRI. Setting this bit to a logical 1 enables the RBR data ready interrupt.

3.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write)

Two 8-bit registers, BLL and BHL, compose a programmable baud generator that uses 24 MHz to generate a 1.8461 MHz frequency and divides it by a divisor from 1 to 216-1. The output frequency of the baud generator is the baud rate multiplied by 16, and this is the base frequency for the transmitter and receiver. The table in the next page illustrates the use of the baud generator with a frequency of

1.8461 MHz. In high-speed UART mode (refer to CR0C bit7 and CR0C bit6), the programmable baud generator directly uses 24 MHz and the same divisor as the normal speed divisor. In high-speed mode, the data transmission rate can be as high as 1.5M bps.

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3.2.9 User-defined Register (UDR) (Read/Write)

This is a temporary register that can be accessed and defined by the user. TABLE 3-5 BAUD RATE TABLE

BAUD RATE FROM DIFFERENT PRE-DIVIDER

Pre-Div: 13

1.8461M Hz 50 400 650 2304 ** 75 600 975 1536 **

110 880 1430 1047 0.18%

134.5 1076 1478.5 857 0.099% 150 1200 1950 768 ** 300 2400 3900 384 ** 600 4800 7800 192 **

1200 9600 15600 96 ** 1800 14400 23400 64 ** 2000 16000 26000 58 0.53% 2400 19200 31200 48 ** 3600 28800 46800 32 ** 4800 38400 62400 24 ** 7200 57600 93600 16 **

9600 76800 124800 12 ** 19200 153600 249600 6 ** 38400 307200 499200 3 ** 57600 460800 748800 2 **

115200 921600 1497600 1 **

** The percentage error for all baud rates, except where indicated otherwise, is 0.16%. Note. Pre-Divisor is determined by CRF0 of UART A and B.

Pre-Div:1.625

14.769M Hz

Pre-Div: 1.0

24M Hz

Decimal divisor used

to generate 16X clock

Error Percentage between

desired and actual

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4. INFRARED (IR) PORT

The Infrared (IR) function provides point-to-point (or multi-point to multi-point) wireless communication which can operate under various transmission protocols including IrDA 1.0 SIR, SHARP ASK-IR. IR port shares the same port with UART B port in W83977TF. Please refer to section 11.5 for configuration information.

5. PARALLEL PORT

5.1 Printer Interface Logic

The parallel port of the W83977TF makes possible the attachment of various devices that accept eight bits of parallel data at standard TTL level. The W83977TF supports an IBM XT/AT compatible parallel port (SPP), bi-directional parallel port (BPP), Enhanced Parallel Port (EPP), Extended Capabilities Parallel Port (ECP), Extension FDD mode (EXTFDD), Extension 2FDD mode (EXT2FDD) on the parallel port. Refer to the configuration registers for more information on disabling, power-down, and on selecting the mode of operation.

Table 5-1 shows the pin definitions for different modes of the parallel port.

TABLE 5-1-1

CONNECTOR

Notes: n<name > : Active Low

1. Compatible Mode

2. High Speed Mode

3. For more information, refer to the IEEE 1284 standard.

PARALLEL PORT CONNECTOR AND PIN DEFINITIONS

HOST

1 36 O nSTB nWrite nSTB, HostClk

2-9 31-26, 24-23 I/O PD<0:7> PD<0:7> PD<0:7>

10 22 I nACK Intr nACK, PeriphClk 11 21 I BUSY nWait BUSY, PeriphAck 12 19 I PE PE PEerror, nAckReverse 13 18 I SLCT Select SLCT, Xflag 14 35 O nAFD nDStrb nAFD, HostAck 15 34 I nERR nError nFault1, nPeriphRequest 16 33 O nINIT nInit nINIT1, nReverseRqst 17 32 O nSLIN nAStrb nSLIN1 , ECPMode

PIN NUMBER

OF W83977TF

ATTRIBUTE

SPP EPP ECP

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INDEX

TRAK

WP2

RDATA

DSKCHG

MOA2

DSA2

DSB2

MOB2

WD2

WE2

RWC2

DIR2

STEP

TABLE 5-1-2

CONNECTOR

PARALLEL PORT CONNECTOR AND PIN DEFINITIONS

HOST

1 36 O nSTB --- --- --- --2 31 I/O PD0 I

3 30 I/O PD1 I 4 29 I/O PD2 I 5 28 I/O PD3 I 6 27 I/O PD4 I 7 26 I/O PD5 --- --- --- ---

8 24 I/O PD6 OD

9 23 I/O PD7 OD 10 22 I nACK OD 11 21 I BUSY OD 12 19 I PE OD 13 18 I SLCT OD 14 35 O nAFD OD 15 34 I nERR OD 16 33 O nINIT OD 17 32 O nSLIN OD

PIN NUMBER OF

W83977TF

ATTRIBUTE

SPP PIN

ATTRIBUTE

EXT2FDD PIN

ATTRIBUTE

HEAD2

--- ---

--- --- OD OD OD OD OD OD OD OD

EXTFDD

I I I I I

HEAD2

5.2 Enhanced Parallel Port (EPP)

TABLE 5-2

Notes:

1. These registers are available in all modes.

2. These registers are available only in EPP mode.

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PRINTER MODE AND EPP REGISTER ADDRESS

A2 A1 A0 REGISTER NOTE

0 0 0 Data port (R/W) 1 0 0 1 Printer status buffer (Read) 1 0 1 0 Printer control latch (Write) 1 0 1 0 Printer control swapper (Read) 1 0 1 1 EPP address port (R/W) 2 1 0 0 EPP data port 0 (R/W) 2 1 0 1 EPP data port 1 (R/W) 2 1 1 0 EPP data port 2 (R/W) 2 1 1 1 EPP data port 2 (R/W) 2

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BUSY

ACK

BUSY

5.2.1 Data Swapper

The system microprocessor can read the contents of the printer's data latch by reading the data swapper.

5.2.2 Printer Status Buffer

The system microprocessor can read the printer status by reading the address of the printer status buffer. The bit definitions are as follows:

235 467 0 1 1

TMOUT ERROR

SLCT PE

ACK

Bit 7: This signal is active during data entry, when the printer is off-line during printing, when the print

head is changing position, or during an error state. When this signal is active, the printer is busy and cannot accept data.

Bit 6: This bit represents the current state of the printer's

received a character and is ready to accept another. Normally, this signal will be active for approximately 5 microseconds before

stops. Bit 5: Logical 1 means the printer has detected the end of paper. Bit 4: Logical 1 means the printer is selected.

Bit 3: Logical 0 means the printer has encountered an error condition. Bit 1, 2: These two bits are not implemented and are logic one during a read of the status register.

Bit 0: This bit is valid in EPP mode only. It indicates that a 10 µS time-out has occurred on the EPP

bus. A logic 0 means that no time-out error has occurred; a logic 1 means that a time-out error has been detected. Writing a logic 1 to this bit will clear the time-out status bit; writing a logic 0 has no effect.

signal. A 0 means the printer has

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DIR

ACK

5.2.3 Printer Control Latch and Printer Control Swapper

The system microprocessor can read the contents of the printer control latch by reading the printer control swapper. Bit definitions are as follows:

234567 0

111

STROBE AUTO FD

INIT SLCT IN IRQ ENABLE

Bit 7, 6: These two bits are a logic one during a read. They can be written. Bit 5: Direction control bit

When this bit is a logic 1, the parallel port is in input mode (read); when it is a logic 0, the

parallel port is in output mode (write). This bit can be read and written. In SPP mode, this bit is invalid and fixed at zero.

Bit 4: A 1 in this position allows an interrupt to occur when

changes from low to high.

Bit 3: A 1 in this bit position selects the printer. Bit 2: A 0 starts the printer (50 microsecond pulse, minimum). Bit 1: A 1 causes the printer to line-feed after a line is printed. Bit 0: A 0.5 microsecond minimum high active pulse clocks data into the printer. Valid data must be

present for a minimum of 0.5 microseconds before and after the strobe pulse.

5.2.4 EPP Address Port

The address port is available only in EPP mode. Bit definitions are as follows:

1234567 0

PD0 PD1

PD2 PD3 PD4

PD5 PD6 PD7

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IOW

IOR

IOW

IOR

BUSY

ACK

ERROR

INIT AUTOFD

STROBE

INIT AUTOFD

STROBE

The contents of DB0-DB7 are buffered (non-inverting) and output to ports PD0-PD7 during a write operation. The leading edge of trailing edge of

latches the data for the duration of the EPP write cycle.

auses an EPP address write cycle to be performed, and the

PD0-PD7 ports are read during a read operation. The leading edge of

causes an EPP address

read cycle to be performed and the data to be output to the host CPU.

5.2.5 EPP Data Port 0-3

These four registers are available only in EPP mode. Bit definitions of each data port are as follows:

123456

PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7

When accesses are made to any EPP data port, the contents of DB0-DB7 are buffered (noninverting) and output to the ports PD0-PD7 during a write operation. The leading edge of an EPP data write cycle to be performed, and the trailing edge of

duration of the EPP write cycle. During a read operation, ports PD0-PD7 are read, and the leading edge of

latches the data for the

causes an EPP read

causes

cycle to be performed and the data to be output to the host CPU.

5.2.6 Bit Map of Parallel Port and EPP Registers

Data Port (R/W)

Status Buffer (Read)

Control Swapper (Read) Control Latch (Write) EPP Address Port R/W)

EPP Data Port 0 (R/W)

EPP Data Port 1 (R/W)

7 6 5 4 3 2 1 0

PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

1 1 1 IRQEN SLIN 1 1 DIR IRQ SLIN

PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

PE SLCT

1 1 TMOUT

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EPP Data Port 2 (R/W)

W83977TF

PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

EPP Data Port 3 (R/W)

PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

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WAIT

5.2.7 EPP Pin Descriptions

EPP NAME TYPE EPP DESCRIPTION nWrite O Denotes an address or data read or write operation. PD<0:7> I/O Bi-directional EPP address and data bus. Intr I Used by peripheral device to interrupt the host. nWait I Inactive to acknowledge that data transfer is completed. Active to

indicate that the device is ready for the next transfer. PE I Paper end; same as SPP mode. Select I Printer selected status; same as SPP mode. nDStrb O This signal is active low. It denotes a data read or write operation. nError I Error; same as SPP mode. nInits O This signal is active low. When it is active, the EPP device is reset to its

initial operating mode. nAStrb O This signal is active low. It denotes an address read or write operation.

5.2.8 EPP Operation

When the EPP mode is selected in the configuration register, the standard and bi-directional modes are also available. The PDx bus is in the standard or bi-directional mode when no EPP read, write, or address cycle is currently being executed. In this condition all output signals are set by the SPP Control Port and the direction is controlled by DIR of the Control Port.

A watchdog timer is required to prevent system lockup. The timer indicates that more than 10 µS have elapsed from the start of the EPP cycle to the time

is aborted when a time-out occurs. The time-out condition is indicated in Status bit 0.

5.2.8.1 EPP Operation The EPP operates on a two-phase cycle. First, the host selects the register within the device for

subsequent operations. Second, the host performs a series of read and/or write byte operations to the selected register. Four operations are supported on the EPP: Address Write, Data Write, Address Read, and Data Read. All operations on the EPP device are performed asynchronously.

5.2.8.2 EPP Version 1.9 Operation The EPP read/write operation can be completed under the following conditions:

a. If the nWait is active low, when the read cycle (nWrite inactive high, nDStrb/nAStrb active low) or write cycle (nWrite active low, nDStrb/nAStrb active low) starts, the read/write cycle proceeds normally and will be completed when nWait goes inactive high.

b. If nWait is inactive high, the read/write cycle will not start. It must wait until nWait changes to active low, at which time it will start as described above.

5.2.8.3 EPP Version 1.7 Operation The EPP read/write cycle can start without checking whether nWait is active or inactive. Once the

read/write cycle starts, however, it will not terminate until nWait changes from active low to inactive high.

is deasserted. The current EPP cycle

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5.3 Extended Capabilities Parallel (ECP) Port

This

port is software and hardware compatible with existing parallel ports, so it may be used as a standard printer mode if ECP is not required. It provides an automatic high burst-bandwidth channel that supports DMA for ECP in both the forward (host to peripheral) and reverse (peripheral to host) directions.

Small FIFOs are used in both forward and reverse directions to improve the maximum bandwidth requirement. The size of the FIFO is 16 bytes. The ECP port supports an automatic handshake for the standard parallel port to improve compatibility mode transfer speed.

The ECP port supports run-length-encoded (RLE) decompression (required) in hardware. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated. Hardware support for compression is optional.

For more information about the ECP Protocol, refer to the Extended Capabilities Port Protocol and ISA Interface Standard.

5.3.1 ECP Register and Mode Definitions

NAME ADDRESS I/O ECP MODES FUNCTION data Base+000h R/W 000-001 Data Register ecpAFifo Base+000h R/W 011 ECP FIFO (Address) dsr Base+001h R All Status Register dcr Base+002h R/W All Control Register cFifo Base+400h R/W 010 Parallel Port Data FIFO ecpDFifo Base+400h R/W 011 ECP FIFO (DATA) tFifo Base+400h R/W 110 Test FIFO cnfgA Base+400h R 111 Configuration Register A cnfgB Base+401h R/W 111 Configuration Register B ecr Base+402h R/W All Extended Control Register

Note: The base addresses are specified by CR60 and 61, which are determined by configuration register or hardware setting.

MODE DESCRIPTION

000 SPP mode 001 PS/2 Parallel Port mode 010 Parallel Port Data FIFO mode 011 ECP Parallel Port mode 100 EPP mode (If this option is enabled in the CRF0 to select ECP/EPP mode) 101 Reserved 110 Test mode 111 Configuration mode

Note: The mode selection bits are bit 7-5 of the Extended Control Register.

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PD7

Address or RLE

5.3.2 Data and ecpAFifo Port

Modes 000 (SPP) and 001 (PS/2) (Data Port) During a write operation, the Data Register latches the contents of the data bus on the rising edge of

the input. The contents of this register are output to the PD0-PD7 ports. During a read operation, ports PD0-PD7 are read and output to the host. The bit definitions are as follows:

7 6 5 4 3 2 1 0

PD0 PD1

PD2 PD3 PD4 PD5 PD6

Mode 011 (ECP FIFO-Address/RLE) A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The

hardware at the ECP port transmits this byte to the peripheral automatically. The operation of this register is defined only for the forward direction. The bit definitions are as follows:

7 6 5 4 3 2 1 0

Address/RLE

5.3.3 Device Status Register (DSR)

These bits are at low level during a read of the Printer Status Register. The bits of this status register are defined as follows:

7 6 5 4 3 2 1 0

11 1

nFault Select PError nAck nBusy

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ACK

SLIN

INIT

AFD

STB

Bit 7: This bit reflects the complement of the Busy input. Bit 6: This bit reflects the nAck input. Bit 5: This bit reflects the PError input. Bit 4: This bit reflects the Select input. Bit 3: This bit reflects the nFault input. Bit 2-0: These three bits are not implemented and are always logic one during a read.

5.3.4 Device Control Register (DCR)

The bit definitions are as follows:

7 6 5 4 3 2 1 0

1 1

strobe autofd nInit SelectIn ackIntEn Direction

Bit 6, 7: These two bits are logic one during a read and cannot be written. Bit 5: This bit has no effect and the direction is always out if mode = 000 or mode = 010. Direction is

valid in all other modes. 0 the parallel port is in output mode. 1 the parallel port is in input mode.

Bit 4: Interrupt request enable. When this bit is set to a high level, it may be used to enable interrupt requests from the parallel port to the CPU due to a low to high transition on the

Bit 3: This bit is inverted and output to the

output.

input.

0 The printer is not selected. 1 The printer is selected.

Bit 2: This bit is output to the Bit 1: This bit is inverted and output to the Bit 0: This bit is inverted and output to the

output.

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compress

5.3.5 cFifo (Parallel Port Data FIFO) Mode = 010

This mode is defined only for the forward direction. The standard parallel port protocol is used by a hardware handshake to the peripheral to transmit bytes written or DMAed from the system to this FIFO. Transfers to the FIFO are byte aligned.

5.3.6 ecpDFifo (ECP Data FIFO) Mode = 011

When the direction bit is 0, bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are byte aligned.

When the direction bit is 1, data bytes from the peripheral are read under automatic hardware handshake from ECP into this FIFO. Reads or DMAs from the FIFO will return bytes of ECP data to the system.

5.3.7 tFifo (Test FIFO Mode) Mode = 110

Data bytes may be read, written, or DMAed to or from the system to this FIFO in any direction. Data in the tFIFO will not be transmitted to the parallel port lines. However, data in the tFIFO may be displayed on the parallel port data lines.

5.3.8 cnfgA (Configuration Register A) Mode = 111

This register is a read-only register. When it is read, 10H is returned. This indicates to the system that this is an 8-bit implementation.

5.3.9 cnfgB (Configuration Register B) Mode = 111

The bit definitions are as follows:

7 6 5 4 3 2 1 0

1 1 1

IRQx 0 IRQx 1 IRQx 2

intrValue

Bit 7: This bit is read-only. It is at low level during a read. This means that this chip does not support

hardware RLE compression.

Bit 6: Returns the value on the ISA IRQ line to determine possible conflicts.

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Bit 5-3: Reflect the IRQ resource assigned for ECP port.

cnfgB[5:3] IRQ resource

000 reflect other IRQ resources selected by PnP register (default) 001 IRQ7 010 IRQ9 011 IRQ10 100 IRQ11 101 IRQ14 110 IRQ15

Bit 2-0: These five bits are at high level during a read and can be written

5.3.10 ecr (Extended Control Register) Mode = all

This register controls the extended ECP parallel port functions. The bit definitions are follows:

Bit 7-5: These bits are read/write and select the mode.

111 IRQ5

7 6 5 4 3 2 1 0

empty full service Intr dmaEn nErrIntrEn MODE MODE

MODE

000 Standard Parallel Port mode. The FIFO is reset in this mode. 001 PS/2 Parallel Port mode. This is the same as 000 except that direction may be

used to tri-state the data lines and reading the data register returns the value on the data lines and not the value in the data register.

010 Parallel Port FIFO mode. This is the same as 000 except that bytes are written or

DMAed to the FIFO. FIFO data are automatically transmitted using the standard parallel port protocol. This mode is useful only when direction is 0.

011 ECP Parallel Port Mode. When the direction is 0 (forward direction), bytes placed

into the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and auto transmitted to the peripheral using ECP Protocol. When the direction is 1 (reverse direction), bytes are moved from the ECP parallel port and packed into

bytes in the ecpDFifo. 100 Selects EPP Mode. In this mode, EPP is activated if the EPP mode is selected. 101 Reserved. 110 Test Mode. The FIFO may be written and read in this mode, but the data will not be

transmitted on the parallel port. 111 Configuration Mode. The confgA and confgB registers are accessible at 0x400 and

0x401 in this mode.

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Bit 4: Read/Write (Valid only in ECP Mode)

1 Disables the interrupt generated on the asserting edge of nFault. 0 Enables an interrupt pulse on the high to low edge of nFault. If nFault is asserted

(interrupt) an interrupt will be generated and this bit is written from a 1 to 0.

Bit 3: Read/Write

1 Enables DMA. 0 Disables DMA unconditionally.

Bit 2: Read/Write

1 Disables DMA and all of the service interrupts. 0 Enables one of the following cases of interrupts. When one of the service interrupts

has occurred, the serviceIntr bit is set to a 1 by hardware. This bit must be reset to 0 to re-enable the interrupts. Writing a 1 to this bit will not cause an interrupt.

(a) dmaEn = 1: During DMA this bit is set to a 1 when terminal count is reached. (b) dmaEn = 0 direction = 0: This bit is set to 1 whenever there are writeIntr

Threshold or more bytes free in the FIFO. (c) dmaEn = 0 direction = 1: This bit is set to 1 whenever there are readIntr

Threshold or more valid bytes to be read from the FIFO.

Bit 1: Read only

0 The FIFO has at least 1 free byte. 1 The FIFO cannot accept another byte or the FIFO is completely full.

Bit 0: Read only

0 The FIFO contains at least 1 byte of data. 1 The FIFO is completely empty.

W83977TF

5.3.11 Bit Map of ECP Port Registers

D7 D6 D5 D4 D3 D2 D1 D0 NOTE

data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr

Notes:

1. These registers are available in all modes.

2. All FIFOs use one common 16-byte FIFO.

PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Addr/RLE Address or RLE field 2

nBusy nAck PError Select nFault 1 1 1 1

1 1 Directio ackIntEn SelectIn nInit autofd strobe 1 Parallel Port Data FIFO 2 ECP Data FIFO 2 Test FIFO 2

0 0 0 1 0 0 0 0

compress intrValue 1 1 1 1 1 1

MODE nErrIntrEn dmaEn serviceIntr full empty

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5.3.12 ECP Pin Descriptions

NAME TYPE DESCRIPTION

nStrobe (HostClk) O The nStrobe registers data or address into the slave on the

asserting edge during write operations. This signal handshakes

with Busy. PD<7:0> I/O These signals contains address or data or RLE data. nAck (PeriphClk) I This signal indicates valid data driven by the peripheral when

asserted. This signal handshakes with nAutoFd in reverse. Busy (PeriphAck) I This signal deasserts to indicate that the peripheral can accept

data. It indicates whether the data lines contain ECP command

information or data in the reverse direction. When in reverse

direction, normal data are transferred when Busy (PeriphAck)

is high and an 8-bit command is transferred when it is low. PError (nAckReverse) I This signal is used to acknowledge a change in the direction of

the transfer (asserted = forward). The peripheral drives this

signal low to acknowledge nReverseRequest. The host relies

upon nAckReverse to determine when it is permitted to drive

the data bus. Select (Xflag) I Indicates printer on line. nAutoFd (HostAck) O Requests a byte of data from the peripheral when it is asserted.

This signal indicates whether the data lines contain ECP

address or data in the forward direction. When in forward

direction, normal data are transferred when nAutoFd (HostAck)

is high and an 8-bit command is transferred when it is low. nFault (nPeriphRequest) I Generates an error interrupt when it is asserted. This signal is

valid only in the forward direction. The peripheral is permitted

(but not required) to drive this pin low to request a reverse

transfer during ECP Mode. nInit (nReverseRequest) O This signal sets the transfer direction (asserted = reverse,

deasserted = forward). This pin is driven low to place the

channel in the reverse direction. nSelectIn (ECPMode) O This signal is always deasserted in ECP mode.

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5.3.13 ECP Operation

The host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol before ECP operation. After negotiation, it is necessary to initialize some of the port bits. The following are required:

(a) Set direction = 0, enabling the drivers. (b) Set strobe = 0, causing the nStrobe signal to default to the deasserted state. (c) Set autoFd = 0, causing the nAutoFd signal to default to the deasserted state. (d) Set mode = 011 (ECP Mode)

ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo, respectively.

5.3.13.1 Mode Switching Software will execute P1284 negotiation and all operations prior to a data transfer phase under

programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ECP port only in the data transfer phase (mode 011 or 010).

If the port is in mode 000 or 001 it may switch to any other mode. If the port is not in mode 000 or 001 it can only be switched into mode 000 or 001. The direction can be changed only in mode 001.

When in extended forward mode, the software should wait for the FIFO to be empty before switching back to mode 000 or 001. In ECP reverse mode the software waits for all the data to be read from the FIFO before changing back to mode 000 or 001.

5.3.13.2 Command/Data ECP mode allows the transfer of normal 8-bit data or 8-bit commands. In the forward direction,

normal data are transferred when HostAck is high and an 8-bit command is transferred when HostAck is low. The most significant bits of the command indicate whether it is a run-length count (for compression) or a channel address.

In the reverse direction, normal data are transferred when PeriphAck is high and an 8-bit command is transferred when PeriphAck is low. The most significant bit of the command is always zero.

5.3.13.3 Data Compression The W83977TF supports run length encoded (RLE) decompression in hardware and can transfer

compressed data to a peripheral. Note that the odd (RLE) compression in hardware is not supported. In order to transfer data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo.

5.3.14 FIFO Operation

The FIFO threshold is set in configuration register 5. All data transfers to or from the parallel port can proceed in DMA or Programmed I/O (non-DMA) mode, as indicated by the selected mode. The FIFO is used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. After a reset, the FIFO is disabled.

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MOB

DSB

DSKCHG

RDATA

TRAK

INDEX

MOA

DSA, MOB

DSB

DSKCHG

RDATA

TRAK

INDEX

5.3.15 DMA Transfers

DMA transfers are always to or from the ecpDFifo, tFifo, or CFifo. The DMA uses the standard PC DMA services. The ECP requests DMA transfers from the host by activating the PDRQ pin. The DMA will empty or fill the FIFO using the appropriate direction and mode. When the terminal count in the DMA controller is reached, an interrupt is generated and serviceIntr is asserted, which will disable the DMA.

5.3.16 Programmed I/O (NON-DMA) Mode

The ECP or parallel port FIFOs can also be operated using interrupt driven programmed I/O. Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo located at 400H, or to/from the tFifo at 400H. The host must set the direction, state, dmaEn = 0 and serviceIntr = 0 in the programmed I/O transfers.

The ECP requests programmed I/O transfers from the host by activating the IRQ pin. The programmed I/O will empty or fill the FIFO using the appropriate direction and mode.

5.4 Extension FDD Mode (EXTFDD)

In this mode, the W83977TF changes the printer interface pins to FDC input/output pins, allowing the user to install a second floppy disk drive (FDD B) through the DB-25 printer connector. The pin assignments for the FDC input/output pins are shown in Table 5-1.

After the printer interface is set to EXTFDD mode, the following occur: (1) Pins (2) Pins

as input signals to the FDC.

(3) Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for

FDD open drain/collector output.

(4) If the parallel port is set to EXTFDD mode after the system has booted DOS or another operating

system, a warm reset is needed to enable the system to recognize the extension floppy drive.

and

will be forced to inactive state.

, WP,

will be logically ORed with pins PD4-PD0 to serve

5.5 Extension 2FDD Mode (EXT2FDD)

In this mode, the W83977TF changes the printer interface pins to FDC input/output pins, allowing the user to install two external floppy disk drives through the DB-25 printer connector to replace internal floppy disk drives A and B. The pin assignments for the FDC input/output pins are shown in Table5-1.

After the printer interface is set to EXTFDD mode, the following occur: (1) Pins (2) Pins

serve as input signals to the FDC.

(3) Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for

FDD open drain/collector output.

(4) If the parallel port is set to EXT2FDD mode after the system has booted DOS or another operating

system, a warm reset is needed to enable the system to recognize the extension floppy drive.

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, and

, WP,

will be forced to inactive state.

, and

will be logically ORed with pins PD4-PD0 to

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6. KEYBOARD CONTROLLER

W83977TF

The KBC (8042 with licensed KB BIOS) circuit of W83977TF is designed to provide the functions needed to interface a CPU with a keyboard and/or a PS/2 mouse, and can be used with IBM

-

compatible personal computers or PS/2-based systems. The controller receives serial data from the keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer. Then, the controller will assert an interrupt to the system when data are placed in its output buffer. The keyboard and PS/2 mouse are required to acknowledge all data transmissions. No transmission should be sent to the keyboard or PS/2 mouse until an acknowledge is received for the previous data byte.

GP I/O PINS

Multiplex I/O PINS

P17KINH

P12~P16

8042

P24 P25 P21

P20

P27

P10

P26 T0

P23

P22

P11

KIRQ MIRQ GATEA20 KBRST

KDAT

KCLK

MCLK

MDAT

Keyboard and Mouse Interface

6.1 Output Buffer

The output buffer is an 8-bit read-only register at I/O address 60H (Default, PnP programmable I/O address LD5-CR60 and LD5-CR61). The keyboard controller uses the output buffer to send the scan code received from the keyboard and data bytes required by commands to the system. The output buffer can only be read when the output buffer full bit in the register is "1".

6.2 Input Buffer

The input buffer is an 8-bit write-only register at I/O address 60H or 64H (Default, PnP programmable I/O address LD5-CR60, LD5-CR61, LD5-CR62, and LD5-CR63). Writing to address 60H sets a flag to indicate a data write; writing to address 64H sets a flag to indicate a command write. Data written to I/O address 60H is sent to keyboard (unless the keyboard controller is expecting a data byte) through the controller's input buffer only if the input buffer full bit in the status register is 0 .

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6.3 Status Register

The status register is an 8-bit read-only register at I/O address 64H (Default, PnP programmable I/O address LD5-CR62 and LD5-CR63), that holds information about the status of the keyboard controller and interface. It may be read at any time.

BIT BIT FUNCTION DESCRIPTION

0 Output Buffer Full 0: Output buffer empty

1: Output buffer full

1 Input Buffer Full 0: Input buffer empty

1: Input buffer full

2 System Flag This bit may be set to 0 or 1 by writing to the system flag

bit in the command byte of the keyboard controller. It defaults to 0 after a power-on reset.

3 Command/Data 0: Data byte

1: Command byte

4 Inhibit Switch 0: Keyboard is inhibited

1: Keyboard is not inhibited

5 Auxiliary Device Output

Buffer

6 General Purpose Time-

out

7 Parity Error 0: Odd parity

0: Auxiliary device output buffer empty 1: Auxiliary device output buffer full

0: No time-out error 1: Time-out error

1: Even parity (error)

6.4 Commands

COMMAND FUNCTION

20h Read Command Byte of Keyboard Controller 60h Write Command Byte of Keyboard Controller

A4h Test Password

BIT

Reserved

7 6

IBM Keyboard Translate Mode

Disable Auxiliary Device

5 4

Disable Keyboard

Reserve System Flag

2 1

Enable Auxiliary Interrupt

Enable Keyboard Interrupt

BIT DEFINITION

Returns 0Fah if Password is loaded Returns 0F1h if Password is not loaded

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6.4 Commands, continued

COMMAND FUNCTION

A5h Load Password

A6h Enable Password

A7h Disable Auxiliary Device Interface A8h Enable Auxiliary Device Interface A9h Interface Test

AAh Self-test

ABh Interface Test

ADh Disable Keyboard Interface AEh Enable Keyboard Interface C0h Read Input Port(P1) and send data to the system C1h Continuously puts the lower four bits of Port1 into STATUS register C2h Continuously puts the upper four bits of Port1 into STATUS register D0h Send Port2 value to the system D1h Only set/reset GateA20 line based on the system data bit 1 D2h Send data back to the system as if it came from Keyboard D3h Send data back to the system as if it came from Auxiliary Device D4h Output next received byte of data from system to Auxiliary Device

E0h Reports the status of the test inputs

FXh

W83977TF

Load Password until a "0" is received from the system

Enable the checking of keystrokes for a match with the password

BIT

No Error Detected

00 01

Auxiliary Device "Clock" line is stuck low Auxiliary Device "Clock" line is stuck high

02 03

Auxiliary Device "Data" line is stuck low

Returns 055h if self test succeeds

BIT

00 01

02 03 04

Pulse only RC(the reset line) low for 6µS if Command byte is even

BIT DEFINITION

No Error Detected Keyboard "Clock" line is stuck low

Keyboard "Clock" line is stuck high

Keyboard "Data" line is stuck low Keyboard "Data" line is stuck high

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6.5 Hardware GATEA20/Keyboard Reset Control Logic

The KBC implements a hardware control logic to speed-up GATEA20 and KBRESET. This control logic is controlled by LD5-CRF0 as follows:

6.5.1 KB Control Register (Logic Device 5, CR-F0)

BIT 7 6 5 4 3 2 1 0

NAME KCLKS1 KCLKS0 Reserved Reserved Reserved P92EN HGA20 HKBRST

KCLKS1, KCLKS0

This 2 bits are for the KBC clock rate selection. = 0 0 KBC clock input is 6 Mhz

= 0 1 KBC clock input is 8 Mhz = 1 0 KBC clock input is 12 Mhz = 1 1 KBC clock input is 16 Mhz

P92EN

A "1" on this bit enables Port 92 to control GATEA20 and KBRESET. A "0" on this bit disables Port 92 functions.

HGA20

A "1" on this bit selects hardware GATEA20 control logic to control GATE A20 signal. A "0" on this bit disables hardware GATEA20 control logic function.

HKBRST

A "1" on this bit selects hardware KB RESET control logic to control KBRESET signal. A "0" on this bit disables hardware KB RESET control logic function.

When the KBC receives data that follows a "D1" command, the hardware control logic sets or clears GATE A20 according to the received data bit 1. Similarly, the hardware control logic sets or clears KBRESET depending on the received data bit 0. When the KBC receives a "FE" command, the KBRESET is pulse low for 6µS(Min.) with 14µS(Min.) delay.

GATEA20 and KBRESET are controlled by either the software control or the hardware control logic and they are mutually exclusive. Then, GATEA20 and KBRESET are merged along with Port92 when P92EN bit is set.

(Port 92 Enable)

(Hardware GATE A20)

(Hardware Keyboard Reset)

6.5.2 Port 92 Control Register (Default Value = 0x24)

BIT 7 6 5 4 3 2 1 0

NAME Res. (0) Res. (0) Res. (1) Res. (0) Res. (0) Res. (1) SGA20 PLKBRST

SGA20

A "1" on this bit drives GATE A20 signal to high. A "0" on this bit drives GATE A20 signal to low.

PLKBRST

A "1" on this bit causes KBRESET to drive low for 6µS(Min.) with 14µS(Min.) delay. Before issuing another keyboard reset command, the bit must be cleared.

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(Special GATE A20 Control)

(Pull-Low KBRESET)

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PANSWOUT

PANSWIN

PANSWOUT

6.6 OnNow / Security Keyboard and Mouse Wake-Up

---- Programmable Keyboard / Mouse Wake-Up Functions

Winbond's unique programmable keyboard/ mouse wake-up functions provide the system diversified methods for either OnNow wake-up application, or security control application. The keyboard or mouse can wake up the system by producing a panel switch low pulse on it to chipset (for example IntelTM chipset TX, LX PIIX4) panel switch input. The wake-up conditions can be programmed as pre-determined or any keys/buttons. To implement this function, a

32.768KHz crystal must be installed between XTAL1 and XTAL2, or a 32.768KHz clock to be connected to XTAL1 and leave XTAL2 open. The VSB pin must be connected to +5V VSB of ATX power supply, and an external battery should be installed on V passwords and wake-up status which had been set already) when power fails.

6.6.1 Keyboard Wake-Up Function

The keyboard wake-up function is enable by setting LD-0A CR-E0 bit 6. The pre-determined keys data are stored in registers, and they can be access by an indirection method. At first, write their index address to LD-0A CR-E1, then access them by reading/writing LD-0A CR-E2. A zero data is written to the register means the comparison of this register will be ignored. The pre-programmed keys may be 1 to 5 keys with various combinations. If LD-0A CR-E0 bit 0 is set, the system will be waken up after any key struck.

6.6.2 Keyboard Password Wake-Up Function

To implement this function, the bit 7 of LD-0A CR-E0 must be set, and panel switch input is connected to and make only keyboard can wake up the system with preset keys (password).

pin. Thus

is blocked to

BAT

pin to store the data (the

, by setting LD-0A CR-E0 properly

pin, and connect

6.6.3 Mouse Wake-Up Function

The mouse wake-up function is activated by setting bit 5 of LD-0A CR-E0. If bit 1 of LD-0A CR-E0 is set, any movement or button clicking will make up the system. Otherwise, the mouse can wake up the system only by clicking its button twice successively with the mouse unmoved. The bit 4 of LD0A CR-E0 determines which button (left or right) to perform wake-up function.

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7. GENERAL PURPOSE I/O

W83977TF provides 23 Input/Output ports that can be individually configured to perform a simple basic I/O function or a pre-defined alternate function. Those 23 GP I/O ports are divided into three groups, the first group contains 8 ports, the second group contains only 7 ports, and the third group contains 8 ports. Each port in first group corresponds to a configuration register in logical device 7, the second group in logical device 8, and the third group in logical device 9. Users can select those I/O ports functions by independently programming those configuration registers. Figure 7.1, 7.2, and

7.3 respectively show the GP I/O port's structure of logical device 7, 8, and 9. Right after Power-on reset, those ports default to perform basic I/O functions.

Figure 7.1

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Figure 7.2

Figure 7.3

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7.1 Basic I/O functions

The Basic I/O functions of W83977TF provide several I/O operations including driving a logic value to output port, latching a logic value from input port, inverting the input/output logic value, and steering Common Interrupt (only available in the second group of the GP I/O port). Common Interrupt is the ORed function of all interrupt channels in the second group of the GP I/O ports, and it also connects to a 1ms debounce filter which can reject a noise of 1 ms pulse width or less. There are three 8-bit registers (GP1, GP2, and GP3) which are directly connected to those GP I/O ports. Each GP I/O port is represented as a bit in one of three 8-bit registers. Only 6 bits of GP2 are implemented. Table

7.1.1 shows their combinations of Basic I/O functions, and Table 7.1.2 shows the register bit

assignments of GP1, GP2, and GP3.

Table 7.1.1

I/O BIT

0 = OUTPUT

1 = INPUT

0 0 0 Basic non-inverting output 0 0 1 Basic inverting output 0 1 0 Non-inverted output bit value of GP2

0 1 1 Inverted output bit value of GP2 drive

1 0 0 Basic non-inverting input 1 0 1 Basic inverting input 1 1 0 Non-inverted input drive to Common

1 1 1 Inverted input drive to Common

ENABLE INT BIT

0 = DISABLE

1 = ENABLE

POLARITY BIT

0 = NON INVERT

1 = INVERT

BASIC I/O OPERATIONS

drive to Common Interrupt

to Common Interrupt

Interrupt

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Table 7.1.2

W83977TF

GP I/O PORT ACCESSED

BIT 0 GP10 BIT 1 GP11

BIT 3 GP13

GP1 BIT 4 GP14

BIT 5 GP15 BIT 6 GP16 BIT 7 GP17

BIT 0 GP20 BIT 1 GP21

GP2 BIT 2 GP22

BIT 3 GP23 BIT 4 GP24 BIT 5 GP25

ASSIGNMENT

BIT 2 GP12

GP I/O PORT

BIT 6 GP26

BIT 0 GP30 BIT 1 GP31 BIT 2 GP32 BIT 3 GP33

GP3 BIT 4 GP34

BIT 6 GP36 BIT 7 GP37

BIT 5 GP35

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7.2 Alternate I/O Functions

W83977TF provides several alternate functions which are scattered among the GP I/O ports. Table

7.2.1 shows their assignments. Polarity bit can also be set to alter their polarity.

Table 7.2.1

GP I/O PORT ALTERNATE FUNCTION

GP10 Interrupt Steering GP11 Interrupt Steering GP12 Watch Dog Timer Output/IRRX input GP13 Power LED output/IRTX output GP14 General Purpose Address Decoder/Keyboard Inhibit(P17) GP15 General Purpose Write Strobe/ 8042 P12 GP16 Watch Dog Timer Output GP17 Power LED output GP20 Keyboard Reset (8042 P20) GP21 8042 P13 GP22 8042 P14 GP23 8042 P15 GP24 8042 P16 GP25 GATE A20 (8042 P21)

GP30 Interrupt Steering GP31 Interrupt Steering GP32 General Purpose Address Decoder GP33 General Purpose Address Decoder GP34 Watch Dog Timer Output

7.2.1 Interrupt Steering

GP10, GP11, GP30, and GP31 can be programmed to map their own interrupt channels. The

selection of IRQ channel can be done in configuration registers CR70 and CR72 of logical device 7

and logical device 9. Each interrupt channel also has its own 1 ms debounce filter that is used to

reject any noise whose width is equal to or less than 1 ms.

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7.2.2 Watch Dog Timer Output

Watch Dog Timer contains a one minute resolution down counter, CRF2 of Logical Device 8, and two watch Dog control registers, WDT_CTRL0 and WDT_CTRL1 of Logical Device 8. The down counter can be programmed within the range from 1 to 255 minutes. Writing any new non-zero value to CRF2 or reset signal coming from a Mouse interrupt or Keyboard interrupt (CRF2 also contains nonzero value) will cause the Watch Dog Timer to reload and start to count down from the new value. As the counter reaches zero, (1) Watch Dog Timer time-out occurs and the bit 0 of WDT_CTRL1 will be set to logic 1; (2) Watch Dog interrupt output is asserted if the interrupt is enable in CR72 of logical device 8; and (3) Power LED starts to toggle output if the bit 3 of WDT_CTRL0 is enabled. WDT_CTRL1 also can be accessed through GP2 I/O base address + 1.

7.2.3 Power LED

The Power LED function provides 1 Hertz rate toggle pulse output with 50 percent duty cycle. Table

7.2.2 shows how to enable Power LED.

Table 7.2.2

WDT_CTRL1 BIT[1] WDT_CTRL0 BIT[3] WDT_CTRL1 BIT[0] POWER LED STATE

* Note: Continuous high or low depends on the polarity bit of GP13 or GP17 configuration registers.

1 X X 1 Hertz Toggle pulse 0 0 X Continuous high or low * 0 1 0 Continuous high or low * 0 1 1 1 Hertz Toggle pulse

7.2.4 General Purpose Address Decoder

General Purpose Address Decoder provides two address decode as AEN equal to logic 0. The address base is stored at CR62, CR63 of logical device 7 for GP14 and at CR62-65 of logical device

9 for GP32 and GP33. The decoding output is normally active low. Users can alter its polarity

through the polarity bit of the GP14, GP32, and GP33's configuration register.

7.2.5 General Purpose Write Strobe

General Purpose Write Strobe is an address decoder that performs like General Purpose Address Decoder, but it has to be qualified by

alter its polarity through the polarity bit of the GP15's configuration register.

and AEN. Its output is normally active low. Users can

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8. PLUG AND PLAY CONFIGURATION

The W83977TF uses Compatible PNP protocol to access configuration registers for setting up different types of configurations. In W83977TF, there are nine Logical Devices (from Logical Device

0 to Logical Device A with the exception of logical device 4 and 6 for compatibility) which correspond

to nine individual functions: FDC (logical device 0), PRT (logical device 1), UART1 (logical device 2),

UART2 (logical device 3), KBC (logical device 5), GPIO1 (logical device 7), GPIO2 (logical device 8), GPIO3 (logical device 9), and ACPI ((logical device A). Each Logical Device has its own

configuration registers (above CR30). Host can access those registers by writing an appropriate

logical device number into logical device select register at CR7.

8.1 Compatible PnP

8.1.1 Extended Function Registers

In Compatible PnP, there are two ways to enter Extended Function and read or write the configuration registers. HEFRAS (CR26 bit 6) can be used to select one out of these two methods of entering the Extended Function mode as follows:

HEFRAS address and value

0 write 87h to the location 3F0h twice 1 write 87h to the location 370h twice

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After Power-on reset, the value on PnP, a specific value (87h) must be written twice to the Extended Functions Enable Register (I/O port address 3F0h or 370h). Secondly, an index value (02h, 07h-FFh) must be written to the Extended Functions Index Register (I/O port address 3F0h or 370h same as Extended Functions Enable Register) to identify which configuration register is to be accessed. The designer can then access the desired configuration register through the Extended Functions Data Register (I/O port address 3F1h or 371h).

After programming of the configuration register is finished, an additional value (AAh) should be written to EFERs to exit the Extended Function mode to prevent unintentional access to those configuration registers. The designer can also set bit 5 of CR26 (LOCKREG) to high to protect the configuration registers against accidental accesses.

The configuration registers can be reset to their default or hardware settings only by a cold reset (pin MR = 1). A warm reset will not affect the configuration registers.

8.1.2 Extended Functions Enable Registers (EFERs)

After a power-on reset, the W83977TF enters the default operating mode. Before the W83977TF enters the extended function mode, a specific value must be programmed into the Extended Function Enable Register (EFER) so that the extended function register can be accessed. The Extended Function Enable Registers are write-only registers. On a PC/AT system, their port addresses are 3F0h or 370h (as described in previous section).

8.1.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs)

After the extended function mode is entered, the Extended Function Index Register (EFIR) must be loaded with an index value (02h, 07h-FEh) to access Configuration Register 0 (CR0), Configuration Register 7 (CR07) to Configuration Register FE (CRFE), and so forth through the Extended Function Data Register (EFDR). The EFIRs are write-only registers with port address 3F0h or 370h (as described in section 8.1.1) on PC/AT systems; the EFDRs are read/write registers with port address 3F1h or 371h (as described in section 8.1.1) on PC/AT systems.

(pin 43) is latched by HEFRAS of CR26. In Compatible

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SMI

SCI

SMI

SCI

9. ACPI REGISTERS FEATURES

W83977TF supports both ACPI and legacy power managements. The switch logic of the power managment block generates an

mode. For the legacy mode, the SMI_EN bit is used. If it is set, it routes the power management events to the

interrupt logic. For the ACPI mode, the SCI_EN bit is used. If it is set, it route the

power management events to the register block of Device A and the SCI_EN bit is located in the PM1 register block. See the following figure for illustration.

from SCI to SMI

IRQs

SMI Logic

interrupt in the legacy mode and an

interrupt in the ACPI

interrupt logic. The SMI_EN bit is located in the configuration

SMI_EN

IRQs

SMI output

Logic

SMI

PM Timer

from SMI to SCI

Bus Master SCI

Device Idle

Timers

SCI_EN

SCI Logic

IRQs

SCI output

Logic

Sleep/Wake

State machine

SCI

WAK_STS Clock

Control

Device Trap

Global STBY

Timer

The to output the The

interrupt is routed to pin

interrupt is to route to pin IRQSER, which is the signal pin in the Serial IRQ mode.

interrupt can be routed to pin

, which is dedicated for the

interrupt output. Another way

function. Or it can be

routed to one interrupt request pin, which is selected through CR70.bit3 - 0 of logical device 9. Another way is to output the

interrupt to pin IRQSER if serial IRQ mode is enabled.

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SMI

SCI

SMI

clear

SCI

9.1 SMI to SCI/SCI to SMI and Bus Master

The following figure illustrates the process of generating an interrupt from

from SMI to SCI

BIOS_RLS

GBL_EN

from SCI to SMI

GBL_RLS

BIOS_EN

BUS Master SCI

BM_CNTPL

set

clear

set

clear

set

GBL_STS

To SCI Logic

BIOS_STS

To SMI Logic

BM_STS

To SCI Logic

or from

BM_RLD

: Status bit : Enable bit

For the BIOS software to raise an event to the ACPI software, BIOS_RLS, GBL_EN, and GBL_STS bits are involved. GBL_EN is the enable bit and the GBL_STS is the status bit. Both are controlled by the ACPI software. If BIOS_RLS is set by the BIOS software and GBL_EN is set by the ACPI

software, an GBL_STS to logic 1. Writing a 0 to BIOS_RLS has no effect. Wrinting a 1 to GBL_STS clears it to logic 0 and also clears BIOS_RLS to logic 0. Writing a 0 to GBL_STS has no effect.

interrupt is raised. Writing a 1 to BIOS_RLS sets it to logic 1 and also sets

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For the ACPI software to raise an event to the BIOS software, GBL_RLS, BIOS_EN, and BIOS_STS bits are involved. BIOS_EN is the enable bit and the BIOS_STS is the status bit. Both are controlled by the BIOS software. If GBL_RLS is set by the ACPI software and BIOS_EN is set by the BIOS

software, an logic 1. Writing a 0 to GBL_RLS has no effect. Wrinting a 1 to BIOS_STS clears it to logic 0 and also clears GBL_RLS to logic 0. Writing a 0 to BIOS_STS has no effect.

For the bus master to raise an event to the ACPI software, BM_CNTRL, BM_RLD, and BM_STS bits are involved. Both BM_RLD and BM_STS are controlled by the ACPI software. If BM_CNTRL is set

by the BIOS software and BM_RLD is set by the ACPI software, an 1 to BM_CNTRL sets it to logic 1 and also sets BM_STS to logic 1. Writing a 0 to BM_CNTRL has no effect. Wrinting a 1 to BM_STS clears it to logic 0 and also clears BM_CNTRL to logic 0. Writing a 0 to BM_STS has no effect.

is raised. Writing a 1 to GBL_RLS sets it to logic 1 and also sets BIOS_STS to

interrupt is raised. Writing a

9.2 Power Management Timer

In the ACPI specification, it requires a power management timer. The power management timer is a 24-bit fixed rate free running up-count timer that runs off a 3.579545MHZ clock. The power management timer corresponds to status bit (TMR_STS) and enable bit (TMR_EN). The TMR_STS bit is set any time the last bit of the timer (bit 23) goes from 0 to 1 or from 1 to 0. If the TMR_EN bit

is set, the setting of the TMR_STS bit will generate an read the timer value which are located in the PM1 register block. The power management timer has one enabel bit (TMR_ON) to turn ii on or off. The TMR_ON is located in GPE register block. If it is cleared to 0, the power management timer function would not work. There are no timer reset requirements, except that the timer should function after power-up. See the following figure for illustration.

TMR_ON

3.579545 MHz

24 bit

counter

Bits (23-0)

TMR_VAL

interrupt. Three registers are used to

TMR_STS

To SCI Logic

TMR_EN

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9.3 ACPI Registers (ACPIRs)

The ACPI register model consists of the fixed register blocks that perform the ACPI functuions. A register block may be a event register block which deals with ACPI events or a control register block which deals with control features. The order in the event register block is a status register followed by an enable register.

Each event register, if implemented, contains two two register: a status register and an enable register, of 16 bits wide each. The status register indicates which event triggers the ACPI System

Control Interrupt ( However, the corresponding enable bit is also required to be set before an

raised. If the enable bit is not set, the software can examine the state of the hardware event by

reading the status bit without generating an Any status bit, unless otherwise noted, can only be set by specific hardware event. It is cleared by

writing a 1 to its bit position and writing a 0 has no effect. Except some special status bits, every status bit has the corresponding enable bit on the same bit position in the enable register. Those status bits which have no corresponding enable bit are read for special purpose. Reverved or unimplemented enable bits always return zero, and writing to these bits should has no effect.

The control bit in the control register provides some special control function over the hardware event, or some special control over

and writing to those bits should has no effect.

Table 9-1 (sec. 9.3.21) lists the PM1 register block and its registers. The base address of PM1

Table 9-2 (sec. 9.3.21) lists the GPE register block and its registers. The base address of generalpurpose event block GPE0 is named as GPE0_BLK in the ACPI specification and is specified in CR62, 63 of logical device A. The base address of general-purpose event block GPE1 is named as GPE1_BLK in the ACPI specification and is specified in CR64, 65 of logical device A.

). When the hardware event occurs, the corresponding status bit will be set.

interrupt could be

interrupt.

event. Reserved or unimplemented control bits always return zero,

9.3.1 Power Management 1 Status Register 1 (PM1STS1)

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TMR_STS Reserved Reserved Reserved BM_STS GBL_STS Reserved Reserved

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Bit Name Description

0 TMR_STS This bit is the timer carry status bit. This bit is set anytime the bit 23 of the

24-bit counter changes (whenever the MSB changes from low to high or high to low). When TMR_EN and TMR_STS are set, a power magement event is raised. This bit is only set by hardware and can only be cleared by writing a

1 to this bit position. Writing a 0 has no effect. 1-3 Reserved Reserved. 4 BM_STS This is the bus master status bit. Writing a 1 to BM_CNTRL also sets

BM_STS. Writing a 1 clears this bit and also clears BM_CNTRL. Writing a

0 has no effect. 5 GBL_STS This is the global status bit. This bit is set when the BIOS wants the

attention of the

can only be cleared by writing a 1 to this bit position. Writing a 1 to this bit

position also clears BIOS_RLS. Writing a 0 has no effect. 6-7 Reserved Reserved. These bits always return zeros.

9.3.2 Power Management 1 Status Register 2 (PM1STS2)

34567

handler. BIOS sets this bit by setting BIOS_RLS and

Reserved Reserved Reserved Reserved Reserved Reserved Reserved WAK_STS

Bit Name Description

0-6 Reserved Reserved. 7 WAK_STS This bit is set when the system is in the sleeping state and an enabled resume

event occurs. Upon setting this bit, the sleeping/working state machine will transition the system to the working state. This bit is only set by hardware and is cleared by writing a 1 to this bit position or by the sleeping/working state machine automatically when the global standby timer expires. Writing a 0 has no effect. When the WAK_STS is cleared and all devices are in sleeping state, the whole chip enters the sleeping state.

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9.3.3 Power Management 1 Enable Register 1(PM1EN1)

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Bit Name Description

0 TMR_EN

This is the timer carry interrupt enable bit. When this bit is set then an event is generated whenever the TMR_STS bit is set. When this bit is reset

then no interrupt is generated even when the TMR_STS bit is set. 1-4 Reserved Reserved. These bits always return a value of zero. 5 GBL_EN The global enable bit. When both the GBL_EN bit and the GBL_STS bit are

set, an

interrupt is raised.

6-7 Reserved Reserved.

TMR_EN Reserved Reserved Reserved GBL_EN Reserved Reserved Reserved

9.3.4 Power Management 1 Enable Register 2 (PM1EN2)

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

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Bit Name Description

0-7 Reserved Reserved. These bits always return zeros.

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9.3.5 Power Management 1 Control Register 1 (PM1CTL1)

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Bit Name Description

0 SCI_EN

Select whether the power management event triggers an

interrupt. When this bit is set, then the power management events will

generate an

interrupt. When this bit is reset and SMI_EN bit is set, then

the power management events will generate an 1 BM_RLD This is the bus master reload enable bit. If this bit is set and BM_CNTRL is

set, an

interrupt is raised.

2 GBL_RLS The global release bit. This bit is used by the ACPI software to raise an event

to the BIOS software. The BIOS software has a corresponding enable and

status bit to control its ability to receive the ACPI event. Setting GBL_RLS

sets BIOS_STS, and it generates an 3-7 Reserved Reserved. These bits always return zeros.

SCI_EN BM_RLD GBL_RLD Reserved Reserved Reserved Reserved Reserved

or an

interrupt.

interrupt if BIOS_EN is also set.

9.3.6 Power Management 1 Control Register 2 (PM1CTL2)

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

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Bit Name Description

0-7 Reserved Reserved. These bits always return zeros.

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9.3.7 Power Management 1 Control Register 3 (PM1CTL3)

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

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Bit Name Description

0-7 Reserved Reserved. These bits always return zeros.

9.3.8 Power Management 1 Control Register 4 (PM1CTL4)

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Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

Bit Name Description

0-7 Reserved Reserved. These bits always return zeros.

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9.3.9 Power Management 1 Timer 1 (PM1TMR1)

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Name Description

0-7 TMR_VAL This read-only field returns the running count of the power management timer.

This is a 24-bit counter that runs off of a 3.579545 MHZ clock, and counts in

the working state. The timer is reset and then continues counting until the

CLKIN input the the chip is stopped. If the clock is restarted without a MR

reset, then the counter will resume counting from where it stopped. The

TMR_STS bit is set any time the last bit of the timer (bit 23) goes from 0 to 1

or from 1 to 0. If the TMR_EN bit is set, the setting of the TMR_STS bit will

generate an

interrupt.

TMR_VAL0 TMR_VAL1 TMR_VAL2 TMR_VAL3 TMR_VAL4 TMR_VAL5 TMR_VAL6 TMR_VAL7

9.3.10 Power Management 1 Timer 2 (PM1TMR2)

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TMR_VAL8 TMR_VAL9 TMR_VAL10 TMR_VAL11 TMR_VAL12 TMR_VAL13 TMR_VAL14 TMR_VAL15

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Bit

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Bit

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Name Description

0-7 TMR_VAL This read-only field returns the running count of the power management timer.

This is a 24-bit counter that runs off of a 3.579545 MHZ clock, and counts in

the working state. The timer is reset and then continues counting until the

CLKIN input the the chip is stopped. If the clock is restarted without a MR

reset, then the counter will resume counting from where it stopped. The

TMR_STS bit is set any time the last bit of the timer (bit 23) goes from 0 to 1

or from 1 to 0. If the TMR_EN bit is set, the setting of the TMR_STS bit will

generate an

interrupt.

9.3.11 Power Management 1 Timer 3 (PM1TMR3)

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TMR_VAL16 TMR_VAL17 TMR_VAL18 TMR_VAL19 TMR_VAL20 TMR_VAL21 TMR_VAL22 TMR_VAL23

Name Description

0-7 TMR_VAL This read-only field returns the running count of the power management timer.

This is a 24-bit counter that runs off of a 3.579545 MHZ clock, and counts in

the working state. The timer is reset and then continues counting until the

CLKIN input the the chip is stopped. If the clock is restarted without a MR

reset, then the counter will resume counting from where it stopped. The

TMR_STS bit is set any time the last bit of the timer (bit 23) goes from 0 to 1

or from 1 to 0. If the TMR_EN bit is set, the setting of the TMR_STS bit will

generate an

interrupt.

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9.3.12 Power Management 1 Timer 4 (PM1TMR4)

SCI

34567

Bit Name Description

0-7 Reserved Reserved. These bits always return zeros.

9.3.13 General Purpose Event 0 Status Register 1 (GP0STS1)

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W83977TF

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

URBSCISTS URASCISTS FDCSCISTS PRTSCISTS KBCSCISTS MOUSCISTS Reserved Reserved

These bits indicate the status of the corresponding enable bit in the

input, which is set when the device's IRQ is raised. If the

interrupt enable register (in GP0EN1) is set, an

interrupt is

raised and routed to the output pin. Wrinting a 1 clears the bit, and wrinting a 0 has no effect. If the bit is not cleared, new IRQ to the

logic input is ignored and no

interrupt will be raised.

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Bit Name Description

0 URBSCISTS 1 URASCISTS 2 FDCSCISTS 3 PRTSCISTS

4 KBCSCISTS 5 MOUSCISTS

UART B

UART A

FDC

PRT

KBC

MOUSE

status, which is set by the UART B IRQ. status, which is set by the UART A IRQ.

status, which is set by the FDC IRQ.

status, which is set by the printer port IRQ.

status, which is set by the KBC IRQ.

status, which is set by the MOUSE IRQ.

6-7 Reserved Reserved.

9.3.14 General Purpose Event 0 Status Register 2 (GP0STS2)

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Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

Bit Name Description

0-7 Reserved Reserved. These bits always return zeros.

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9.3.15 General Purpose Event 0 Enable Register 1 (GP0EN1)

SCI

URBSCIEN URASCIEN FDCSCIEN PRTSCIEN KBCSCIEN MOUSCIEN Reserved Reserved

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W83977TF

These bits are used to enable the device's IRQ sources into the

logic. The

logic output for

the IRQs is as follows: SCI logic output = (URBSCIEN and URBSCISTS) or (URASCIEN and URASCISTS) or (FDCSCIEN

and FDCSCISTS) or (PRTSCIEN and PRTSCISTS) or (KBCSCIEN and KBCSCISTS) or

(MOUSCIEN and MOUSCISTS)

Bit Name Description

0 URBSCIEN 1 URASCIEN 2 FDCSCIEN 3 PRTSCIEN

4 KBCSCIEN 5 MOUSCIEN

UART B

UART A

FDC

printer port

KBC

MOUSE

enable, which controls the UART B IRQ. enable, which controls the UART A IRQ.

enable, which controls the FDC IRQ.

enable, which controls the printer port IRQ.

enable, which controls the KBC IRQ.

enable, which controls the MOUSE IRQ.

6-7 Reserved Reserved.

9.3.16 General Purpose Event 0 Enable Register 2 (GP0EN2)

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Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

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Bit Name Description

0-7 Reserved Reserved. These bits always return zeros.

9.3.17 General Purpose Event 1 Status Register 1 (GP1STS1)

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W83977TF

BIOS_STS Reserved Reserved Reserved Reserved Reserved Reserved Reserved

Bit Name Description

0 BIOS_STS The BIOS status bit. This bit is set when GBL_RLS is set. If BIOS_EN is set,

setting GBL_RLS will raise an

event. Writing a 1 to its bit location clears

BIOS_STS and also clears GBL_RLS. Writing a 0 has no effect. 1-7 Reserved Reserved.

9.3.18 General Purpose Event 1 Status Register 2 (GP1STS2)

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