Datasheet W83877F Datasheet (Winbond Electronics)

Page 1

W83877F

WINBOND I/O

GENERAL DESCRIPTION

One of Winbond's popular series of I/O chips, the W83877F integrates a disk drive adapter, serial port (UART), parallel port, IDE bus interface, and game port decoder onto a single chip. The W83877F is an enhanced version of the W83777F, with additional powerful features such as configurable plug-and-play registers for the whole chip and infrared support in one of the serial ports.

The disk drive adapter functions of the W83877F include a floppy disk drive controller compatible with the industry standard 82077/765, data separator, write pre-compensation circuit, decode logic, data rate selection, clock generator, drive interface control logic, and interrupt and DMA logic. The wide range of functions integrated onto the W83877F greatly reduces the number of components required for interfacing with floppy disk drives. The W83877F supports four 360K, 720K, 1.2M, 1.44M, or 2.88M disk drives and data transfer rates of 250 Kb/S, 300 Kb/S, 500 Kb/S, and 1 Mb/S.

The W83877F provides two high-speed serial communication ports (UARTs), one of which supports serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable baud rate generator, complete modem control capability, and a processor interrupt system.

The W83877F supports one PC-compatible printer port. Additional bidirectional I/O capability is available by hardware control or software programming. The parallel port also supports the Enhanced Parallel Port (EPP) and Extended Capabilities Port (ECP).

The W83877F supports two embedded hard disk drive (AT bus) interfaces and a game port with decoded read/write output. The chip's Extension FDD Mode and Extension 2FDD Mode allow one or two external floppy disk drives to be connected to the computer through the printer interface pins in notebook computer applications.

The Extension Adapter Mode of the W83877F allows pocket devices to be installed through the printer interface pins in notebook computer applications according to a protocol set by Winbond, but with upgraded performance. The JOYSTICK mode allows a joystick to be connected to a parallel port with a signal switching cable.

The configuration registers support mode selection, function enable/disable, and power down function selection. Moreover, the configurable PnP registers are compatible with the plug-and-play feature in Windows 95

, which makes system resource allocation more efficient than ever.

Publication Release Date: January 1996

- 1 - Revision A2

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W83877F

FEATURES

FDC:

• Compatible with IBM PC AT disk drive systems

• Variable write pre-compensation with track selectable capability

• DMA enable logic

• Non-burst mode DMA option

• Supports floppy disk drives and tape drives

• Detects all overrun and underrun conditions

• Data rate and drive control registers

• Built-in address mark detection circuit to simplify the read electronics

• IBM PC system address decoder

• Supports up to two embedded hard disk drives (IDE AT BUS)

• Single 24 MHz crystal input

• FDD anti-virus functions with software write protect and FDD write enable signal, write data signal

force inactive

• Supports up to four 3.5-inch or 5.25-inch floppy disk drives

• Completely compatible with industry standard 82077

• 360K/720K/1.2M/1.44M/2.88M format

• 250K, 300K, 500K, 1M bps data transfer rate

• Supports vertical recording format

• 16-byte data FIFOs

UART:

• Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs

• MIDI compatible

• Fully programmable serial-interface characteristics:

− 5, 6, 7 or 8-bit characters

− Even, odd or no parity bit generation/detection

− 1, 1.5 or 2 stop bits generation

• Internal diagnostic capabilities:

− Loop-back controls for communications link fault isolation

− Break, parity, overrun, framing error simulation

• Programmable baud generator allows division of 1.8461 MHz and 24 MHz by 1 to (2

Parallel Port:

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W83877F

• Compatible with IBM parallel port

• Supports parallel port with bidirectional lines

• Supports Enhanced Parallel Port (EPP)

− Compatible with IEEE 1284 specification

• Supports Extended Capabilities Port (ECP)

− Compatible with IEEE 1284 specification

• Extension FDD mode supports disk drive B through parallel port

• Extension Adapter Mode supports pocket devices through parallel port

• Extension 2FDD mode supports disk drives A and B through parallel port

• JOYSTICK mode supports joystick through parallel port

Others:

• Programmable configuration settings

• Immediate or automatic power-down mode for power management

• All hardware power-on settings have internal pull-up or pull-down resistors as default value

• Packaged in 100-pin QFP

• Configurable Plug and Play registers

• Infrared communication port

Publication Release Date: January 1996

- 3 - Revision A2

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PIN CONFIGURATION

/ T

X X X X

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

DSA DSB

WE WD

DIR

GND

CS0 CS1

100

1 2 3 4 5 6 7 8 9 10 11 1213 14 15 16 17 18 19 20 21 22 2324 2526 27 28 29 30

X X X X X

INDEX

STEP

RWC

HEAD

IDBEN IRQ_B

IRQIN

IRQ_A

DACK_B

IRQ_F

DRQ_B

W83877F

/ D

3D2

X X X

D 1

X X X X

E N

XX X X X X

XXX X X X X

A8A7A

X X X

X X X X X X X X XX

A2A

RIB

DCDB

DSRB

CTSB

DTRB

RTSB

IRQ_C

SOUTB

SINB

GMRD

GND

GMWR

SOUTA

IRQ_D

RTSA

DTRA

CTSA

DSRA

DCDA

RIA

S S I D E

RXT

R D Y

A C K | C

/ S T B

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1.0 PIN DESCRIPTION

IOR

IOW

Note: Refer to section 9.2 DC CHARACTERISTICS for details. I/O8t - TTL level bidirectional pin with 8 mA source-sink capability I/O12t - TTL level bidirectional pin with 12 mA source-sink capability I/O24t - TTL level bidirectional pin with 24 mA source-sink capability OUT8t - TTL level output pin with 8 mA source-sink capability OUT12t - TTL level output pin with 12 mA source-sink capability OD12 - Open-drain output pin with 12 mA sink capability OD24 - Open-drain output pin with 24 mA sink capability INt - TTL level input pin INc - CMOS level input pin INcs - CMOS level schmitt-triggered input pin

1.1 Host Interface

SYMBOL PIN I/O FUNCTION

W83877F

D0−D7 A0−A9

66-73 I/O 51-55

57-61 A10 75 IN IOCHRDY 5 OD

MR 6 IN

2 IN

AEN 62 IN

63 IN 64 IN

DRQ_B 100 OUT

DACK_B

98 IN

DRQ_C 4 OUT

DACK_C

18 IN

TC 97 IN

System data bus bits 0-7

24t

System address bus bits 0-9

In ECP Mode, this pin is the A10 address input.

In EPP Mode, this pin is the IO Channel Ready output to extend

the host read/write cycle. Master Reset. Active high. MR is low during normal operations.

Active low chip select signal

System address bus enable

CPU I/O read signal

CPU I/O write signal

DMA request signal B

12t

DMA Acknowledge signal B

DMA request signal C

12t

DMA Acknowledge signal C

Terminal Count. When active, this pin indicates termination of a

DMA transfer.

IRQIN

93 IN

Interrupt request input

Publication Release Date: January 1996

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1.1 Host Interface, continued

CTSA

CTSB

DSRA

DSRB

DCDA

DCDB

RIA

RIB

SYMBOL PIN I/O FUNCTION

IRQ_A /

GIO1

96 OUT

I/O

When CR16 Bit 4 (GOIQSEL) = 0: Interrupt request signal A;

12t

When CR16 Bit 4 (GOIQSEL) = 1: General Purpose I/O port 1.

12t

W83877F

IRQ_B /

GIO0

92 OUT

I/O

IRQ_C 44 OUT IRQ_D 37 OUT IRQ_E 23 OUT IRQ_F 99 OUT XTAL1 7 IN XTAL2 8 OUT

When CR16 Bit 4 (GOIQSEL) = 0: Interrupt request signal B;

12t

When CR16 Bit 4 (GOIQSEL) = 1: General Purpose I/O port 0.

12t

Interrupt request signal C

12t

Interrupt request signal D

12t

Interrupt request signal E

12t

Interrupt request signal F

12t

XTAL oscillator input

XTAL oscillator output

1.2 Serial Port Interface

SYMBOL PIN I/O FUNCTION

34 47

33 48

32 49

Clear To Send is the modem control input.

The function of these pins can be tested by reading Bit 4 of the handshake status register.

Data Set Ready. An active low indicates the modem or data set

is ready to establish a communication link and transfer data to the UART.

Data Carrier Detect. An active low indicates the modem or data

set has detected a data carrier.

SINA SINB/IRRX1

SOUTA/ PIRIDE

50 30

IN 42 38 I/O

Ring Indicator. An active low indicates that a ring signal is being

received by the modem or data set. Serial Input. Used to receive serial data from the communication

link. UART A Serial Output. Used to transmit serial data out to the

communication link. During power-on reset, this pin is pulled up internally and is

defined as PIRIDE, which provides the power-on value for CR16 bit 1 (IRIDE). A 47 kΩ is recommended when intends to pull down at power-on reset.

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1.2 Serial Port Interface, continued

DTRA

DTRB

RTSA

RTSB

SYMBOL PIN I/O FUNCTION

W83877F

SOUTB/ IRTX1/ PGMDRQ

PHEFRAS

PPNPCVS

PGOIQSEL

43 I/O

35 I/O

46 O

36 I/O

45 I/O

UART B Serial Output. Used to transmit serial data out to the

communication link. During power-on reset, this pin is pulled up internally and is

defined as PGMDRQ, which provides the power-on value for CR16 bit 3 (GMDRQ). A 47 kΩ is recommended when intends to pull down at power-on reset.

UART A Data Terminal Ready. An active low informs the

modem or data set that the controller is ready to communicate. During power-on reset, this pin is pulled down internally and is

defined as PHEFRAS, which provides the power-on value for CR16 bit 0 (HEFRAS). A 47 kΩ is recommended when intends to pull up at power-on reset.

UART B Data Terminal Ready. An active low informs the

modem or data set that controller is ready to communicate. UART A Request To Send. An active low informs the modem or

data set that the controller is ready to send data. During power-on reset, this pin is pulled up internally and is

defined as PPNPCVS, which provides the power-on value for CR16 bit 2 (PNPCVS). A 47 kΩ is recommended when intends to pull down at power-on reset.

UART B Request To Send. An active low informs the modem or

data set that the controller is ready to send data. During power-on reset, this pin is pulled down internally and is

defined as PGOIQSEL, which provides the power-on value for CR16 bit 4 (GOIQSEL). A 47 kΩ is recommended when intends to pull up at power-on reset.

Publication Release Date: January 1996

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W83877F

GMRD

GMWR

1.3 Game Port/Power Down Interface

If Bit 3 of CR16 (GMDRQ) is 1, Bit 4 of CR3 (GMODS0) determines whether the game port is in Adapter mode or Portable mode (default is Adapter mode). If Bit 3 of CR16 is 0, pin 39 and 41 are used for DMA A operation.

SYMBOL PIN I/O FUNCTION

41 OUT

PFDCEN

DACK_A

OUT

39 OUT

PEXTEN

DRQ_A

OUT

PDCIN 3 IN

When CR16 Bit 3 (GMDRQ) = 1:

Adapter mode: Game port read control signal.

Portable mode: When parallel port is selected as Extension FDD/Extension 2FDD mode, this pin will be active. The active state is dependent on bit 7 of CRA (PFDCACT), and default is low active.

When CR16 Bit 3 (GMDRQ) = 0: DMA acknowledge signal A. When CR16 Bit 3 (GMDRQ) = 1:

Adapter mode: Game port write control signal.

Portable mode: When a particular extended mode is selected for the parallel port, this pin will be active. The extended modes include Extension Adapter mode, EPP mode, ECP mode, and ECP/EPP mode, which are selected using bit 3 - bit 0 of CRA. The active state is dependent on bit 6 of CRA (PEXTACT); the default is low active.

When CR16 Bit 3 (GMDRQ) = 0:

DMA request signal A.

This input pin controls the chip power down. When this pin is

active, the clock supply to the chip will be inhibited and the output pins will be tri-stated as defined in CR4 and CR6. The PDCIN is pulled down internally. Its active state is defined by bit 4 of CRA (PDCHACT). Default is high active.

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W83877F

MOB

ACK

DSB

1.4 Multi-Mode Parallel Port

The following pins have eight functions, which are controlled by bits PRTMOD0, PRTMOD1, and PRTMOD2 of CR0 and CR9 (refer to section 8.0, Extended Functions).

SYMBOL PIN I/O FUNCTION

BUSY 24 IN

26 IN

PRINTER MODE: BUSY

An active high input indicates that the printer is not ready to receive data. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: This pin is for Extension FDD B; the function of this pin is the

same as that of the

pin. EXTENSION ADAPTER MODE: XIRQ This pin is an interrupt request generated by the Extension

Adapter and is an active high input.

EXTENSION 2FDD MODE: This pin is for Extension FDD A and B; the function of this pin is

the same as that of the

pin.

JOYSTICK MODE: NC pin.

PRINTER MODE: An active low input on this pin indicates that the printer has

received data and is ready to accept more data. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE:

This pin is for the Extension FDD B; its functions are the same as those of the

EXTENSION ADAPTER MODE: XDRQ

pin.

DMA request generated by the Extension Adapter. An active high input.

EXTENSION 2FDD MODE:

This pin is for Extension FDD A and B; this function of this pin is the same as that of the

JOYSTICK MODE: NC pin.

pin.

Publication Release Date: January 1996

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1.4 Multi-Mode Parallel Port, continued

SYMBOL PIN I/O FUNCTION

PE 27 IN

PRINTER MODE: PE

An active high input on this pin indicates that the printer has detected the end of the paper. This pin is pulled high internally.

Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.

W83877F

OUT

SLCT 28 IN

OUT

EXTENSION FDD MODE:

This pin is for Extension FDD B; its function is the same as that of the WD pin.

12t

EXTENSION ADAPTER MODE: XA0 This pin is system address A0 for the Extension Adapter.

EXTENSION 2FDD MODE: This pin is for Extension FDD A and B; this function of this pin is

the same as that of the WD pin. JOYSTICK MODE: NC pin. PRINTER MODE: SLCT

An active high input on this pin indicates that the printer is selected. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: WE2 This pin is for Extension FDD B; its functions are the same as

12t

those of the WE pin. EXTENSION ADAPTER MODE: XA1

This pin is system address A1 for the Extension Adapter. EXTENSION 2FDD MODE:

This pin is for Extension FDD A and B; this function of this pin is the same as that of the WE pin.

JOYSTICK MODE: NC pin.

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1.4 Multi-Mode Parallel Port, continued

ERR

HEAD

SLIN

STEP

SYMBOL PIN I/O FUNCTION

W83877F

29 IN

OUT

22 OD

OUT

PRINTER MODE: An active low input on this pin indicates that the printer has

encountered an error condition. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE:

This pin is for Extension FDD B; its function is the same as that of the

EXTENSION ADAPTER MODE: XA2

12t

pin.

This pin is system address A2 for the Extension Adapter. EXTENSION 2FDD MODE:

This pin is for Extension FDD A and B; its function is the same as that of the

pin.

JOYSTICK MODE: NC pin.

PRINTER MODE: Output line for detection of printer selection. This pin is pulled

high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE:

This pin is for Extension FDD B; its function is the same as that

12t

of the

pin. EXTENSION ADAPTER MODE: XTC This pin is the DMA terminal count for the Extension Adapter.

The count is sent by TC directly.

EXTENSION 2FDD MODE: This pin is for Extension FDD A and B; its function is the same

12t

as that of the

pin .

JOYSTICK MODE: VDD for joystick.

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1.4 Multi-Mode Parallel Port, continued

INIT

DIR

XDACK

PDACKX

DIR

AFD

RWC

XRD

XWR

RWC

SYMBOL PIN I/O FUNCTION

W83877F

21 OD

OUT

20 OD

OUT

PRINTER MODE: Output line for the printer initialization. This pin is pulled high

internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE:

This pin is for Extension FDD B; its function is the same as that

12t

of the

pin.

EXTENSION ADAPTER MODE: This pin is the DMA acknowledge output for the Extension

Adapter; the output is sent directly from

EXTENSION 2FDD MODE: This pin is for Extension FDD A and B; its function is the same

12t

as that of the

pin.

JOYSTICK MODE: VDD for joystick.

PRINTER MODE: An active low output from this pin causes the printer to auto feed

a line after a line is printed. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE:

This pin is for Extension FDD B; its function is the same as that

12t

of the

pin.

EXTENSION ADAPTER MODE: This pin is the I/O read command for the Extension Adapter. When the Extension Adapter base address is written to the

Extension Adapter address register,

and simultaneously so that the command register on the Extension Adapter can latch the same base address.

EXTENSION 2FDD MODE: This pin is for Extension FDD A and B; its function is the same

12t

as that of the

pin.

JOYSTICK MODE: VDD for joystick.

go low

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1.4 Multi-Mode Parallel Port, continued

STB

XWR

XRD

XWR

INDEX

SYMBOL PIN I/O FUNCTION

W83877F

19 OD

OUT

PD0 9 I/O

I/O

PRINTER MODE: An active low output is used to latch the parallel data into the

printer. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP

mode. EXTENSION FDD MODE:

12t

This pin is a tri-state output. EXTENSION ADAPTER MODE:

This pin is the I/O write command for the Extension Adapter. When the Extension Adapter base address is written to the

Extension Adapter address register, simultaneously so that the command register on the Extension Adapter can latch the same base address.

12t

and

go low

EXTENSION 2FDD MODE: This pin is a tri-state output. JOYSTICK MODE: VDD for joystick. PRINTER MODE: PD0

24t

Parallel port data bus bit 0. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE:

This pin is for Extension FDD B; the function of this pin is the same as that of the

EXTENSION ADAPTER MODE: XD0

24t

pin. This pin is pulled high internally.

This pin is system data bus D0 for the Extension Adapter.

EXTENSION 2FDD MODE: This pin is for Extension FDD A and B; this function of this pin is

the same as JOYSTICK MODE: JP0

24t

pin. This pin is pulled high internally.

This pin is the paddle 0 input for joystick.

Publication Release Date: January 1996

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1.4 Multi-Mode Parallel Port, continued

TRAK

SYMBOL PIN I/O FUNCTION

W83877F

PD1 10 I/O

I/O

PD2 11 I/O

I/O

PRINTER MODE: PD1

24t

Parallel port data bus bit 1. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE:

This pin is for Extension FDD B; the function of this pin is the same as that of the

EXTENSION ADAPTER MODE: XD1

24t

pin. This pin is pulled high internally.

This pin is system data bus D1 for the Extension Adapter.

EXTENSION. 2FDD MODE: This pin is for Extension FDD A and B; this function of this pin is

the same as

24t

JOYSTICK MODE: JP1

pin. This pin is pulled high internally.

This pin is the paddle 1 input for joystick. PRINTER MODE: PD2

24t

Parallel port data bus bit 2. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE:

This pin is for Extension FDD B; the function of this pin is the same as that of the WP pin. This pin is pulled high internally.

EXTENSION ADAPTER MODE: XD2

24t

This pin is system data bus D2 for the Extension Adapter.

EXTENSION. 2FDD MODE: This pin is for Extension FDD A and B; this function of this pin is

the same as that of the WP pin. This pin is pulled high

internally. JOYSTICK MODE: NC pin

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1.4 Multi-Mode Parallel Port, continued

RDATA

DSKCHG

SYMBOL PIN I/O FUNCTION

PD3 12 I/O

PRINTER MODE: PD3

24t

Parallel port data bus bit 3. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: Motor on B for Extension FDD B; the function of this pin is the

I/O

same as that of the

24t

EXTENSION ADAPTER MODE: XD3

pin. This pin is pulled high internally.

This pin is system data bus D3 for the Extension Adapter.

EXTENSION 2FDD MODE: This pin is for Extension FDD A and B; this function of this pin is

the same as that of the internally.

JOYSTICK MODE: NC pin

PD4 13 I/O

PRINTER MODE: PD4

24t

Parallel port data bus bit 4. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: Drive select B for Extension FDD B; the function of this pin is the

I/O

same as that of EXTENSION ADAPTER MODE: XD4

24t

pin. This pin is pulled high internally.

This pin is system data bus D4 for the Extension Adapter.

EXTENSION 2FDD MODE: This pin is for Extension FDD A and B; this function of this pin is the same as that of the

internally.

JOYSTICK MODE: JB0 This pin is the button 0 input for the joystick.

PD5 14 I/O

PRINTER MODE: PD5

24t

Parallel port data bus bit 5. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: This pin is a tri-state output.

I/O

24t

EXTENSION ADAPTER MODE: XD5 This pin is system data bus D5 for the Extension Adapter

EXTENSION 2FDD MODE: This pin is a tri-state output.

JOYSTICK MODE: JB1 This pin is the button 1 input for the joystick.

W83877F

pin. This pin is pulled high

Publication Release Date: January 1996

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1.4 Multi-Mode Parallel Port, continued

MOA

DSA

SYMBOL PIN I/O FUNCTION

W83877F

PD6 16 I/O

I/O

PD7 17 I/O

I/O

PRINTER MODE: PD6

24t

Parallel port data bus bit 6. Refer to the description of the

parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output.

24t

EXTENSION ADAPTER MODE: XD6 This pin is system data bus D6 for the Extension Adapter

EXTENSION. 2FDD MODE: This pin is for Extension FDD A; its function is the same as that

of the

pin. JOYSTICK MODE: NC pin PRINTER MODE: PD7

24t

Parallel port data bus bit 7. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION ADAPTER MODE: XD7

24t

This pin is system data bus D7 for the Extension Adapter.

EXTENSION 2FDD MODE:

This pin is for Extension FDD A; its function is the same as that of the

JOYSTICK MODE: NC pin

pin.

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Page 17

1.5 IDE and FDC Interface

RESIDE

IDBEN

CS1

DIR

HEAD

RWC

STEP

INDEX

SYMBOL PIN I/O FUNCTION

IRQ_G

IRQ_H

IRTX2

IRRX2

1 OUT

OUT

91 OUT

OUT

95 OUT

OUT

94 OUT

85 OD 89

When CR16 Bit 1 (IRIDE) = 0: Active low reset signal for IDE;

12t

When CR16 Bit 1 (IRIDE) = 1: Interrupt request signal G.

12t

When CR16 Bit 1 (IRIDE) = 0: Active low enable signal for IDE;

12t

When CR16 Bit 1 (IRIDE) = 1: Interrupt request signal H.

12t

When CR16 Bit 1 (IRIDE) = 0: This pin is used to select the IDE

12t

controller. CR22.

decodes the HDC addresses specified in

When CR16 Bit 1 (IRIDE) = 1: Function as a InfraRed transmission data line.

When CR16 Bit 1 (IRIDE) = 0: This pin is used to select the IDE

12t

controller.

When CR16 Bit 1 (IRIDE) = 1: Function as a InfraRed receiving

decodes HDC addresses specified in CR21.

line. Write enable. An open drain output.

Direction of the head step motor. An open drain output.

W83877F

88 OD

87 OD

86 OD

82 OD

81 IN

Logic 0 = inward motion Head select. This open drain output determines which disk drive

head is active. Logic 1 = side 0 Logic 0 = side 1 Reduced write current. This signal can be used on two-speed

disk drives to select the transfer rate. An open drain output. Logic 0 = 250 Kb/s Logic 1 = 500 Kb/s When bit 5 of CR9 (EN3MODE) is set to high, the three-mode

FDD function is enabled, and the pin will have a different definition. Refer to the EN3MODE bit in CR9.

Write data. This logic low open drain writes precompensation

serial data to the selected FDD. An open drain output. Step output pulses. This active low open drain output produces a

pulse to move the head to another track. This schmitt input from the disk drive is active low when the

head is positioned over the beginning of a track marked by an index hole. This input pin is pulled up internally by an approximately 1K ohm resistor. The resistor can be disabled by bit 4 of CR6 (FIPURDWN).

Publication Release Date: January 1996

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Page 18

1.5 IDE and FDC Interface, continued

TRAK

RDATA

DSKCHG

MOA

MOB

DSA

DSB

SYMBOL PIN I/O FUNCTION

W83877F

78 IN

77 IN

74 IN

76 IN

79 OD

80 OD

83 OD

84 OD

Track 0. This schmitt input from the disk drive is active low when

the head is positioned over the outermost track. This input pin is pulled up internally by an approximately 1K ohm resistor. The resistor can be disabled by bit 4 of CR6 (FIPURDWN).

Write protected. This active low schmitt input from the disk drive

indicates that the diskette is write-protected. This input pin is pulled up internally by an approximately 1K ohm resistor. The resistor can be disabled by bit 4 of CR6 (FIPURDWN).

The read data input signal from the FDD. This input pin is pulled

up internally by an approximately 1K ohm resistor. The resistor can be disabled by bit 4 of CR6 (FIPURDWN).

Diskette change. This signal is active low at power on and

whenever the diskette is removed. This input pin is pulled up internally by an approximately 1K ohm resistor. The resistor can be disabled by bit 4 of CR6 (FIPURDWN).

Motor A On. When set to 0, this pin enables disk drive 0. This is

an open drain output. Motor B On. When set to 0, this pin enables disk drive 1. This is

an open drain output. Drive Select A. When set to 0, this pin enables disk drive A. This

is an open drain output. Drive Select B. When set to 0, this pin enables disk drive B. This

is an open drain output.

VDD 15,

+5 power supply for the digital circuitry

GND 25,

Ground

65,

2.0 FDC FUNCTIONAL DESCRIPTION

2.1 W83877F FDC

The floppy disk controller of the W83877F integrates all of the logic required for floppy disk control. The FDC implements a PC/AT or PS/2 solution. All programmable options default to compatible values. The FIFO provides better system performance in multi-master systems. The digital data separator supports up to 1 M bits/sec data rate.

The FDC includes the following blocks: AT interface, Precompensation, Data Rate Selection, Digital Data Separator, FIFO, and FDC Core.

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2.1.1 AT interface

DACK

W83877F

The interface consists of the standard asynchronous signals: RD, and a data bus. The address lines select between the configuration registers, the FIFO and control/status registers. This interface can be switched between PC/AT, Model 30, or PS/2 normal modes. The PS/2 register sets are a superset of the registers found in a PC/AT.

2.1.2 FIFO (Data)

The FIFO is 16 bytes in size and has programmable threshold values. All command parameter information and disk data transfers go through the FIFO. Data transfers are governed by the RQM and DIO bits in the Main Status Register.

The FIFO defaults to disabled mode after any form of reset. This maintains PC/AT hardware compatibility. The default values can be changed through the CONFIGURE command. The advantage of the FIFO is that it allows the system a larger DMA latency without causing disk errors. The following tables give several examples of the delays with a FIFO. The data are based upon the following formula:

THRESHOLD # × (1/DATA/RATE) *8 - 1.5 µS = DELAY

FIFO THRESHOLD MAXIMUM DELAY TO SERVICING AT 500K BPS

Data Rate

1 Byte 2 Byte 8 Byte

15 Byte

1 × 16 µS - 1.5 µS = 14.5 µS 2 × 16 µS - 1.5 µS = 30.5 µS 8 × 16 µS - 1.5 µS = 6.5 µS 15 × 16 µS - 1.5 µS = 238.5 µS

, A0-A3, IRQ, DMA control,

FIFO THRESHOLD MAXIMUM DELAY TO SERVICING AT 1M BPS

Data Rate

1 Byte 2 Byte 8 Byte

15 Byte

At the start of a command the FIFO is always disabled and command parameters must be sent based upon the RQM and DIO bit settings in the main status register. When the FDC enters the command execution phase, it clears the FIFO of any data to ensure that invalid data are not transferred.

An overrun and underrun will terminate the current command and the data transfer. Disk writes will complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result phase may be entered.

DMA transfers are enabled with the SPECIFY command and are initiated by the FDC by activating the DRQ pin during a data transfer command. The FIFO is enabled directly by asserting

addresses need not be valid. Note that if the DMA controller is programmed to function in verify mode a pseudo read is performed

by the FDC based only on

. This mode is only available when the FDC has been configured

1 × 8 µS - 1.5 µS = 6.5 µS 2 × 8 µS - 1.5 µS = 14.5 µS 8 × 8 µS - 1.5 µS = 62.5 µS 15 × 8 µS - 1.5 µS = 118.5 µS

and

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W83877F

into byte mode (FIFO disabled) and is programmed to do a read. With the FIFO enabled the above operation is performed by using the new VERIFY command. No DMA operation is needed.

2.1.3 Data Separator

The function of the data separator is to lock onto the incoming serial read data. When a lock is achieved the serial front end logic of the chip is provided with a clock which is synchronized to the read data. The synchronized clock, called the Data Window, is used to internally sample the serial data portion of the bit cell, and the alternate state samples the clock portion. Serial to parallel conversion logic separates the read data into clock and data bytes.

The Digital Data Separator (DDS) has three parts: control logic, error adjustment, and speed tracking. The DDS circuit cycles once every 12 clock cycles ideally. Any data pulse input will be synchronized and then adjusted by immediate error adjustment. The control logic will generate RDD and RWD for every pulse input. During any cycle where no data pulse is present, the DDS cycles are based on speed. A digital integrator is used to keep track of the speed changes in the input data stream.

2.1.4 Write Precompensation

The write precompensation logic is used to minimize bit shifts in the RDDATA stream from the disk drive. Shifting of bits is a known phenomenon in magnetic media and is dependent on the disk media and the floppy drive.

The FDC monitors the bit stream that is being sent to the drive. The data patterns that require precompensation are well known. Depending upon the pattern, the bit is shifted either early or late relative to the surrounding bits.

¡@

2.1.5 Perpendicular Recording Mode

The FDC is also capable of interfacing directly to perpendicular recording floppy drives. Perpendicular recording differs from the traditional longitudinal method in that the magnetic bits are oriented vertically. This scheme packs more data bits into the same area.

FDCs with perpendicular recording drives can read standard 3.5" floppy disks and can read and write perpendicular media. Some manufacturers offer drives that can read and write standard and perpendicular media in a perpendicular media drive.

A single command puts the FDC into perpendicular mode. All other commands operate as they normally do. The perpendicular mode requires a 1 Mbps data rate for the FDC. At this data rate the FIFO eases the host interface bottleneck due to the speed of data transfer to or from the disk.

2.1.6 FDC Core

The W83877F FDC is capable of performing twenty commands. Each command is initiated by a multi-byte transfer from the microprocessor. The result can also be a multi-byte transfer back to the microprocessor. Each command consists of three phases: command, execution, and result.

Command The microprocessor issues all required information to the controller to perform a specific operation. Execution The controller performs the specified operation. Result After the operation is completed, status information and other housekeeping information is provided

to the microprocessor.

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Page 21

2.1.7 FDC Commands

Command Symbol Descriptions: C: Cylinder number 0 - 256 D: Data Pattern DIR: Step Direction DIR = 0, step out DIR = 1, step in DS0: Disk Drive Select 0 DS1: Disk Drive Select 1 DTL: Data Length EC: Enable Count EOT: End of Track EFIFO: Enable FIFO EIS: Enable Implied Seek EOT: End of track FIFOTHR: FIFO Threshold GAP: Gap length selection GPL: Gap Length H: Head number HDS: Head number select HLT: Head Load Time HUT: Head Unload Time LOCK: Lock EFIFO, FIFOTHR, PTRTRK bits prevent affected by software reset MFM: MFM or FM Mode MT: Multitrack N: The number of data bytes written in a sector NCN: New Cylinder Number ND: Non-DMA Mode OW: Overwritten PCN: Present Cylinder Number POLL: Polling Disable PRETRK: Precompensation Start Track Number R: Record RCN: Relative Cylinder Number R/W: Read/Write SC: Sector/per cylinder SK: Skip deleted data address mark

W83877F

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W83877F

SRT: Step Rate Time ST0: Status Register 0 ST1: Status Register 1 ST2: Status Register 2 ST3: Status Register 3 WG: Write gate alters timing of WE

(1) Read Data

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W MT MFM SK 0 0 1 1 0 Command codes

W 0 0 0 0 0 HDS DS1 DS0 W W W W W W W -------------------- DTL -----------------------

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

-------------------- EOT -----------------------

-------------------- GPL -----------------------

Sector ID information prior to command execution

Execution Data transfer between the

FDD and system

Result R

R R

R R R R

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Status information after command execution

Sector ID information after command execution

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W83877F

(2) Read Deleted Data

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W MT MFM SK 0 1 1 0 0 Command codes

W 0 0 0 0 0 HDS DS1 DS0 W W W W W W W -------------------- DTL -----------------------

Execution Data transfer between the

Result R

R R R R R R

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

-------------------- EOT -----------------------

-------------------- GPL -----------------------

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID information prior to command execution

FDD and system Status information after

command execution

Sector ID information after command execution

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W83877F

(3) Read A Track

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 MFM 0 0 0 0 1 0 Command codes

W 0 0 0 0 0 HDS DS1 DS0 W W W W W W W -------------------- DTL -----------------------

Execution Data transfer between the

Result R

R R R R R

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

-------------------- EOT -----------------------

-------------------- GPL -----------------------

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

Sector ID information prior to command execution

FDD and system; FDD reads contents of all cylinders from index hole to EOT

Status information after command execution

Sector ID information after command execution

---------------------- N ------------------------

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W83877F

(4) Read ID

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 MFM 0 0 1 0 1 0 Command codes

W 0 0 0 0 0 HDS DS1 DS0

Execution The first correct ID

information on the cylinder is stored in Data Register

Result R

R R R

(5) Verify

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W MT MFM SK 1 0 1 1 0 Command codes

W EC 0 0 0 0 HDS DS1 DS0 W W W W W W

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

-------------------- EOT -----------------------

-------------------- GPL -----------------------

-------------------- DTL/SC -------------------

Status information after command execution

Disk status after the command has been completed

Sector ID information prior to command execution

Execution No data transfer takes

place

Result R

R R R R R R

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

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Status information after command execution

Sector ID information after command execution

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Page 26

W83877F

(6) Version

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 1 0 0 0 0 Command code Result R 1 0 0 1 0 0 0 0 Enhanced controller

(7) Write Data

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W MT MFM 0 0 0 1 0 1 Command codes

W 0 0 0 0 0 HDS DS1 DS0 W W W W W W W -------------------- DTL -----------------------

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

-------------------- EOT -----------------------

-------------------- GPL -----------------------

Sector ID information prior to Command execution

Execution Data transfer between the

FDD and system

Result R

R R R R R R

(8) Write Deleted Data

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W MT MFM 0 0 1 0 0 1 Command codes

W 0 0 0 0 0 HDS DS1 DS0 W W W W

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Status information after Command execution

Sector ID information after Command execution

Sector ID information prior to command execution

- 26 -

Page 27

Write deleted data, continued

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

W83877F

W W W

Execution Data transfer between the

Result R

R R R R R R

(9) Format A Track

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 MFM 0 0 1 1 0 1 Command codes

W 0 0 0 0 0 HDS DS1 DS0 W W W W

-------------------- EOT -----------------------

-------------------- GPL -----------------------

-------------------- DTL -----------------------

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

--------------------- SC -----------------------

--------------------- GPL ---------------------

---------------------- D ------------------------

FDD and system Status information after

command execution

Sector ID information after command execution

Bytes/Sector Sectors/Cylinder Gap 3 Filler Byte

Execution for Each Sector Repeat:

Result R

W W W W

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

-------------------- ST0 ----------------------R R R

R R R

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

---------------- Undefined -------------------

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Input Sector Parameters

Status information after command execution

Page 28

W83877F

(10) Recalibrate

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 0 1 1 1 Command codes

W 0 0 0 0 0 0 DS1 DS0

Execution Head retracted to Track 0

Interrupt

(11) Sense Interrupt Status

PHASE R/W D7 76 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 1 0 0 0 Command code Result R

(12) Specify

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 0 0 1 1 Command codes

W W

(13) Seek

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 1 1 1 1 Command codes

W W

Execution R Head positioned over proper

(14) Configure

---------------- ST0 -------------------------

---------------- PCN -------------------------

| ---------SRT ----------- | --------- HUT ---------- |

|------------ HLT ----------------------------------| ND

0 0 0 0 0 HDS DS1 DS0

-------------------- NCN -----------------------

Status information at the end of each seek operation

cylinder on diskette

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 1 0 0 1 1 Configure information

W W W

Execution Internal registers written

0 0 0 0 0 0 0 0

0 EIS EFIFO POLL | ------ FIFOTHR ----|

| --------------------PRETRK ---------------------- |

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Page 29

W83877F

(15) Relative Seek

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 1 DIR 0 0 1 1 1 1 Command codes

W W

(16) Dumpreg

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 1 1 1 0 Registers placed in FIFO Result R

R R R R R R R R R

0 0 0 0 0 HDS DS1 DS0

| -------------------- RCN ---------------------------- |

-------------------- PCN-Drive 0-----------------

-------------------- PCN-Drive 1 ----------------

-------------------- PCN-Drive 2-----------------

-------------------- PCN-Drive 3 ----------------

-------SRT ----------------- | --------- HUT --------

------------ HLT -------------------------------------| ND

-------------------- SC/EOT --------------------

LOCK 0 D3 D2 D1 D0 GAP WG

0 EIS EFIFO POLL | ------ FIFOTHR --------

--------------------PRETRK ---------------------

(17) Perpendicular Mode

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 1 0 0 1 0 Command Code

W OW 0 D3 D2 D1 D0 GAP WG

(18) Lock

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W LOCK 0 0 1 0 1 0 0 Command Code Result R 0 0 0 LOCK 0 0 0 0

(19) Sense Drive Status

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 0 1 0 0 Command Code

W 0 0 0 0 0 HDS DS1 DS0

Result R ---------------- ST3 ------------------------- Status information about

disk drive

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W83877F

DRV

(20) Invalid

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W ------------- Invalid Codes ----------------- Invalid codes (no operation

- FDC goes into standby state)

Result R -------------------- ST0 ---------------------- ST0 = 80H

2.2 Register Descriptions

There are several status, data, and control registers in W83877F. These registers are defined below:

ADDRESS REGISTER

OFFSET READ WRITE

base address + 0 base address + 1 base address + 2 base address + 3 base address + 4 MS REGISTER DR REGISTER base address + 5 DT (FIFO) REGISTER DT (FIFO) REGISTER base address + 7 DI REGISTER CC REGISTER

SA REGISTER

SB REGISTER

TD REGISTER

DO REGISTER

TD REGISTER

2.2.1 Status Register A (SA Register) (Read base address + 0)

This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode, the bit definitions for this register are as follows:

34567

DIR

INDEX

HEAD TRAK0

STEP

DRV2

INIT PENDING

INIT PENDING (Bit 7): This bit indicates the value of the floppy disk interrupt output.

(Bit 6): 0 A second drive has been installed 1 A second drive has not been installed

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Page 31

STEP (Bit 5):

STEP

TRAK

HEAD

INDEX

W83877F

This bit indicates the complement of

(Bit 4):

This bit indicates the value of HEAD (Bit 3):

This bit indicates the complement of 0 side 0 1 side 1

(Bit 2):

This bit indicates the value of

(Bit 1): 0disk is write-protected 1disk is not write-protected

DIR (Bit 0) This bit indicates the direction of head movement. 0 outward direction 1 inward direction

output.

input.

output.

In PS/2 Model 30 mode, the bit definitions for this register are as follows:

34567

INIT PENDING (Bit 7): This bit indicates the value of the floppy disk interrupt output.

DRQ (Bit 6): This bit indicates the value of DRQ output pin. STEP F/F (Bit 5):

DIR

WP INDEX

HEAD TRAK0 STEP F/F

DRQ

INIT PENDING

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W83877F

STEP

TRAK

HEAD

INDEX

DIR

WDATA Toggle

RDATA

This bit indicates the complement of latched TRAK0 (Bit 4):

This bit indicates the complement of

(Bit 3):

This bit indicates the value of 0 side 1 1 side 0

INDEX (Bit 2): This bit indicates the complement of

WP (Bit 1): 0 disk is not write-protected 1 disk is write-protected

(Bit 0) This bit indicates the direction of head movement. 0 inward direction 1 outward direction

output.

input.

output.

2.2.2 Status Register B (SB Register) (Read base address + 1)

This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode, the bit definitions for this register are as follows:

34567

Drive SEL0 (Bit 5): This bit indicates the status of DO REGISTER bit 0 (drive select bit 0).

WDATA Toggle (Bit 4): This bit changes state at every rising edge of the WD output pin.

RDATA Toggle (Bit 3): This bit changes state at every rising edge of the

output pin.

MOT EN A MOT EN B

RDATA Toggle

Drive SEL0

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Page 33

WE (Bit 2):

MOB

MOA

DRV

DSB

DSA

RDATA

DSD

This bit indicates the complement of the WE output pin. MOT EN B (Bit 1)

This bit indicates the complement of the

output pin.

MOT EN A (Bit 0) This bit indicates the complement of the

output pin.

In PS/2 Model 30 mode, the bit definitions for this register are as follows:

34567

DSC DSD

WE F/F RDATA F/F

WD F/F

DSA DSB

DRV2

W83877F

(Bit 7): 0 A second drive has been installed 1 A second drive has not been installed

(Bit 6):

This bit indicates the status of

output pin.

(Bit 5):

This bit indicates the status of

output pin.

WD F/F(Bit 4): This bit indicates the complement of the latched WD output pin at every rising edge of the

output pin. RDATA F/F(Bit 3):

This bit indicates the complement of the latched

output pin .

WE F/F (Bit 2): This bit indicates the complement of latched WE output pin.

(Bit 1): 0 Drive D has been selected 1 Drive D has not been selected

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W83877F

DSC

Floppy boot drive 0

Floppy boot drive 1

(Bit 0): 0 Drive C has been selected 1 Drive C has not been selected

2.2.3 Digital Output Register (DO Register) (Write base address + 2)

The Digital Output Register is a write-only register controlling drive motors, drive selection, DRQ/IRQ enable, and FDC resetting. All the bits in this register are cleared by the MR pin. The bit definitions are as follows:

7 6

5 4

1-0

Drive Select: 00 select drive A

Floppy Disk Controller Reset Active low resets FDC DMA and INT Enable Active high enable DRQ/IRQ Motor Enable A. Motor A on when active high Motor Enable B. Motor B on when active high Motor Enable C. Motor C on when active high Motor Enable D. Motor D on when active high

01 select drive B 10 select drive C 11 select drive D

2.2.4 Tape Drive Register (TD Register) (Read base address + 3)

This register is used to assign a particular drive number to the tape drive support mode of the data separator. This register also holds the media ID, drive type, and floppy boot drive information of the floppy disk drive. In normal floppy mode, this register includes only bit 0 and 1. The bit definitions are as follows:

Tape sel 0

Tape sel 1

X X

34567

X X X X

If three mode FDD function is enabled (EN3MODE = 1 in CR9), the bit definitions are as follows:

34567

Tape Sel 0

Tape Sel 1

Drive type ID0 Drive type ID1 Media ID0 Media ID1

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W83877F

Media ID1 Media ID0 (Bit 7, 6): These two bits are read only. These two bits reflect the value of CR8 bit 3, 2.

Drive type ID1 Drive type ID0 (Bit 5, 4): These two bits reflect two of the bits of CR7. Which two bits are reflected depends on the last drive

selected in the DO REGISTER. Floppy Boot drive 1, 0 (Bit 3, 2):

These two bits reflect the value of CR8 bit 1, 0. Tape Sel 1, Tape Sel 0 (Bit 1, 0):

These two bits assign a logical drive number to the tape drive. Drive 0 is not available as a tape drive and is reserved as the floppy disk boot drive.

TAPE SEL 1 TAPE SEL 0 DRIVE SELECTED

0 0 None 0 1 1 1 0 2 1 1 3

2.2.5 Main Status Register (MS Register) (Read base address + 4)

The Main Status Register is used to control the flow of data between the microprocessor and the controller. The bit definitions for this register are as follows:

3 2 1

FDD 0 Busy, (D0B = 1), FDD number 0 is in the SEEK mode. FDD 1 Busy, (D1B = 1), FDD number 1 is in the SEEK mode. FDD 2 Busy, (D2B = 1), FDD number 2 is in the SEEK mode. FDD 3 Busy, (D3B = 1), FDD number 3 is in the SEEK mode. FDC Busy, (CB). A read or write command is in the process when CB = HIGH.

Non-DMA mode, the FDC is in the non-DMA mode, this bit is set only during the execution phase in non-DMA mode. Transition to LOW state indicates execution phase has ended.

DATA INPUT/OUTPUT, (DIO). If DIO= HIGH then transfer is from Data Register to the processor. If DIO = LOW then transfer is from processor to Data Register. Request for Master (RQM). A high on this bit indicates Data Register is ready to send or receive data to or from the processor.

2.2.6 Data Rate Register (DR Register) (Write base address + 4)

The Data Rate Register is used to set the transfer rate and write precompensation. The data rate of the FDC is programmed by the CC REGISTER for PC-AT and PS/2 Model 30 and PS/2 mode, and not by the DR REGISTER. The real data rate is determined by the most recent write to either of the DR REGISTER or CC REGISTER.

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W83877F

POWER DOWN

34567

DRATE0 DRATE1 PRECOMP0

PRECOMP1 PRECOMP2

S/W RESET

S/W RESET (Bit 7): This bit is the software reset bit.

POWER-DOWN (Bit 6): 0 FDC in normal mode 1 FDC in power-down mode

PRECOMP2 PRECOMP1 PRECOMP0 (Bit 4, 3, 2): These three bits select the value of write precompensation. The following tables show the

precompensation values for the combination of these bits.

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PRECOM

RWC

2 1 0

0 0 0 Default Delays 0 0 1 41.67 nS 0 1 0 83.34 nS 0 1 1 125.00 nS 1 0 0 166.67 nS 1 0 1 208.33 nS 1 1 0 250.00 nS 1 1 1 0.00 nS (disabled)

DATA RATE DEFAULT PRECOMPENSATION DELAYS

250 KB/S 125 nS

W83877F

300 KB/S 125 nS 500 KB/S 125 nS

1 MB/S 41.67 nS

DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC and reduced write current control.

00 500 KB/S (MFM), 250 KB/S (FM), 01 300 KB/S (MFM), 150 KB/S (FM), 10 250 KB/S (MFM), 125 KB/S (FM), 11 1 MB/S (MFM), Illegal (FM),

2.2.7 FIFO Register (R/W base address + 5)

The Data Register consists of four status registers in a stack with only one register presented to the data bus at a time. This register stores data, commands, and parameters and provides diskette-drive status information. Data bytes are passed through the data register to program or obtain results after a command. In the W83877F, this register defaults to FIFO disabled mode after reset. The FIFO can change its value and enable its operation through the CONFIGURE command.

= 1. = 0. = 0.

= 1.

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Page 38

Status Register 0 (ST0)

11 Abnormal termination because the ready signal from FDD changed state during command execution

OR (Over Rum). 1 If the FDC is not serviced by the host system within a certain time interval during data transfer.

W83877F

7-6 5

3 2 1-0

Status Register 1 (ST1)

US1, US0 Drive Select:

00 Drive A selected 01 Drive B selected 10 Drive C selected 11 Drive D selected

HD Head address:

1 Head selected 0 Head selected

NR Not Ready:

1 Drive is not ready 0 Drive is ready

EC Equipment Check:

1 When a fault signal is received from the FDD or the track 0 signal fails to occur after 77 step pulses 0 No error

SE Seek end:

1 seek end 0 seek error

IC Interrupt Code:

00 Normal termination of command 01 Abnormal termination of command 10 Invalid command issue

234567

Missing Address Mark. 1 When the FDC cannot detect the data address mark or the data address mark has been deleted.

NW (Not Writable). 1 If a write Protect signal is detected from the diskette drive during execution of write data.

ND (No DATA). 1 If specified sector cannot be found during execution of a read, write or verifly data. Not used. This bit is always 0.

DE (data Error).1 When the FDC detects a CRC error in either the ID field or the data field. Not used. This bit is always 0. EN (End of track). 1 When the FDC tries to access a sector beyond the final sector of a cylinder.

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Page 39

Status Register 2 (ST2)

WP Write Protected

DSKCHG

W83877F

7 0

Status Register 3 (ST3)

234

MD (Missing Address Mark in Data Field). 1 If the FDC cannot find a data address mark (or the address mark has been deleted) when reading data from the media 0 No error BC (Bad Cylinder) 1 Bad Cylinder 0 No error SN (Scan Not satisfied) 1 During execution of the Scan command 0 No error SH (Scan Equal Hit) 1 During execution of the Scan command, if the equal condition is satisfied 0 No error WC (Wrong Cylinder) 1 Indicates wrong Cylinder DD (Data error in the Data field)

1 If the FDC detects a CRC error in the data field

0 No error CM (Control Mark) 1 During execution of the read data or scan command 0 No error Not used. This bit is always 0

US0 Unit Select 0 US1 Unit Select 1 HD Head Address TS Two-Side TO Track 0 RY Ready

FT Fault

2.2.8 Digital Input Register (DI Register) (Read base address + 7)

The Digital Input Register is an 8-bit read-only register used for diagnostic purposes. In a PC/XT or AT only Bit 7 is checked by the BIOS. When the register is read, Bit 7 shows the complement of

, while other bits of the data bus remain in tri-state. Bit definitions are as follows:

567

xxx

In the PS/2 mode, the bit definitions are as follows:

01234

xxx

Reserved for the hard disk controller During a read of this register, these bits are in tri-state

DSKCHG

Publication Release Date: January 1996

- 39 - Revision A2

Page 40

DSKCHG (Bit 7):

DSKCHG

HIGH DENS

DSKCHG

1 111

W83877F

34567

HIGH DENS DRATE0

DRATE1

DSKCHG

This bit indicates the complement of the

input.

Bit 6-3: These bits are always a logic 1 during a read. DRATE1 DRATE0 (Bit 2, 1):

These two bits select the data rate of the FDC. Refer to the DR register bits 1 and 0 for the settings corresponding to the individual data rates.

(Bit 0): 0 500 KB/S or 1 MB/S data rate (high density FDD) 1 250 KB/S or 300 KB/S data rate

In the PS/2 Model 30 mode, the bit definitions are as follows:

34567

0 00

DRATE0

DRATE1

NOPREC DMAEN

DSKCHG

DSKCHG (Bit 7): This bit indicates the status of

input. Bit 6-4: These bits are always a logic 1 during a read. DMAEN (Bit 3):

This bit indicates the value of DO REGISTER bit 3.

NOPREC (Bit 2):

- 40 -

Page 41

W83877F

This bit indicates the value of CC REGISTER NOPREC bit. DRATE1 DRATE0 (Bit 1, 0):

These two bits select the data rate of the FDC.

2.2.9 Configuration Control Register (CC Register) (Write base address + 7)

This register is used to control the data rate. In the PC/AT and PS/2 mode, the bit definitions are as follows:

x x x x x x

X: Reserved

Bit 7-2: Reserved. These bits should be set to 0. DRATE1 DRATE0 (Bit 1, 0):

These two bits select the data rate of the FDC. In the PS/2 Model 30 mode, the bit definitions are as follows:

X X

X X X

X: Reserved

Bit 7-3: Reserved. These bits should be set to 0.

34567

DRATE0 DRATE1

DRATE0

DRATE1

NOPREC

NOPREC (Bit 2): This bit indicates no precompensation. It has no function and can be set by software.

DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC.

Publication Release Date: January 1996

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W83877F

CS0

CS1

3.0 IDE

The IDE interface is essentially the AT bus ported to the hard disk drive. The hard disk controller resides on the IDE hard disk drive. So the IDE interface provides only chip select signals and AT bus signals between the IDE hard disk drive and ISA slot. Table 3-1 shows the IDE registers and their ISA addresses.

Table 3-1

I/O ADDRESS REGISTERS

OFFSET READ WRITE

base address + 0 base address + 1 base address + 2 base address + 3 base address + 4 base address + 5 base address + 6 base address + 7

base address + 6

Data Register Data Register

Error Register Write-Precomp

Sector Count Sector Count

Sector Number Sector Number

Cylinder LOW Cylinder LOW

Cylinder HIGH Cylinder HIGH

SDH Register SDH Register

Status Register Command Register

Alternate Status Fixed Disk Control

3.1 IDE Decode Description

When the processor selects the addresses which match the ones specified in CR 21, the chip system enables

matches the one specified in CR22, the chip system enables

= LOW; otherwise,

= HIGH. When the processor selects the address which

= LOW; otherwise,

= HIGH.

4.0 UART PORT

4.1 Universal Asynchronous Receiver/Transmitter (UART A, UART B)

The UARTs are used to convert parallel data into serial format on the transmit side and convert serial data to parallel format on the receiver side. The serial format, in order of transmission and reception, is a start bit, followed by five to eight data bits, a parity bit (if programmed) and one, one and half (five-bit format only) or two stop bits. The UARTs are capable of handling divisors of 1 to 65535 and producing a 16x clock for driving the internal transmitter logic. Provisions are also included to use this 16x clock to drive the receiver logic. The UARTs also support the MIDI data rate. Furthermore, the UARTs also include complete modem control capability and a processor interrupt system that may be software trailed to the computing time required to handle the communication link. The UARTs have a FIFO mode to reduce the number of interrupts presented to the CPU. In each UART, there are 16byte FIFOs for both receive and transmit mode.

4.2 Register Address

- 42 -

Page 43

W83877F

TABLE 4-1 UART Register Bit Map

Bit Number

BDLAB = 0

A Interrupt Status

A UART FIFO

B UART Control

C Handshake

D UART Status

E Handshake

F User Defined

BDLAB = 1

Receiver

Buffer

(Read Only)

Transmitter

Buffer Register

(Write Only)

Interrupt Control

(Read Only)

Control

(Write Only)

Control

Status Register

Baudrate Divisor

Latch Low

Baudrate

Divisor Latch

High

*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received. **: These bits are always 0 in 16450 Mode.

RBR RX Data

Bit 0

TBR TX Data

Bit 0

ICR RBR Data

Ready

Interrupt

Enable

(ERDRI)

ISR "0" if

Interrupt

Pending

UFR FIFO

Enable

UCR Data

Length

Select

Bit 0

(DLS0)

HCR Data

Terminal

Ready (DTR)

USR RBR Data

Ready

(RDR)

HSR CTS

Toggling

(TCTS)

UDR Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

BLL Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

BHL Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15

RX Data

Bit 1

TX Data

Bit 1 TBR

Empty

Interrupt

Enable

(ETBREI)

Interrupt

Status

Bit (0)

RCVR

FIFO

Reset

Data

Length

Select

Bit 1

(DLS1)

Request

Send

(RTS)

Overrun

Error

(OER)

DSR

Toggling

(TDSR)

RX Data

Bit 2

TX Data

Bit 2

USR

Interrupt

Enable

(EUSRI) Interrupt

Status

Bit (1)

XMIT FIFO

Reset

Multiple

Stop Bits

Enable

(MSBE)

Loopback

Input

Parity Bit

Error

(PBER)

RI Falling

Edge

(FERI)

RX Data

Bit 3

TX Data

Bit 3

HSR

Interrupt

Enable

(EHSRI) Interrupt

Status

Bit (2)**

DMA

Mode

Select

Parity

Bit

Enable

(PBE)

IRQ

Enable

No Stop

Bit

Error

(NSER)

DCD

Toggling

(TDCD)

RX Data

Bit 4

TX Data

Bit 4

0 0 0 0

0 0 FIFOs

Reserved Reversed RX

Even

Parity

Enable

(EPE)

Internal

Loopback

Enable

Silent

Byte

Detected

(SBD)

Clear

to Send

(CTS)

RX Data

Bit 5

TX Data

Bit 5

Parity

Bit Fixed

Enable PBFE)

0 0 0

TBR

Empty

(TBRE)

Data Set

Ready

(DSR)

RX Data

Bit 6

TX Data

Bit 6

Enabled

Interrupt

Active Level

(LSB)

Set

Silence

Enable

(SSE)

TSR

Empty

(TSRE)

Ring

Indicator

(RI)

Active Level

Access Bit

Data Carrier

RX Data

Bit 7

TX Data

Bit 7

FIFOs

Enabled

Interrupt

(MSB)

Baudrate

Divisor

Latch

(BDLAB)

RX FIFO

Error Indication (RFEI) **

Detect

(DCD)

Publication Release Date: January 1996

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Page 44

W83877F

Baudrate divisor latch access bit (BDLAB)

4.2.1 UART Control Register (UCR) (Read/Write)

The UART Control Register controls and defines the protocol for asynchronous data communications, including data length, stop bit, parity, and baud rate selection.

7 0

Data length select bit 0 (DLS0) Data length select bit 1(DLS1) Multiple stop bits enable (MSBE) Parity bit enable (PBE) Even parity enable (EPE) Parity bit fixed enable (PBFE) Set silence enable (SSE)

Bit 7: BDLAB. When this bit is set to a logical 1, designers can access the divisor (in 16-bit

binary format) from the divisor latches of the baudrate generator during a read or write operation. When this bit is reset, the Receiver Buffer Register, the Transmitter Buffer Register, or the Interrupt Control Register can be accessed.

Bit 6: SSE. A logical 1 forces the Serial Output (SOUT) to a silent state (a logical 0). Only SOUT

is affected by this bit; the transmitter is not affected.

Bit 5: PBFE. When PBE and PBFE of UCR are both set to a logical 1, (1) if EPE is a logical 1, the parity bit is fixed as a logical 0 to transmit and check. (2) if EPE is a logical 0, the parity bit is fixed as a logical 1 to transmit and check.

Bit 4: EPE. This bit describes the number of logic 1's in the data word bits and parity bit only when

bit 3 is programmed. When this bit is set, an even number of logic 1's are sent or checked. When the bit is reset, an odd number of logic 1's are sent or checked.

Bit 3: PBE. When this bit is set, the position between the last data bit and the stop bit of the SOUT

will be stuffed with the parity bit at the transmitter. For the receiver, the parity bit in the same position as the transmitter will be detected.

Bit 2: MSBE. This bit defines the number of stop bits in each serial character that is transmitted or

received. (1) If MSBE is set to a logical 0, one stop bit is sent and checked. (2) If MSBE is set to a logical 1, and data length is 5 bits, one and a half stop bits are sent and

checked.

(3) If MSBE is set to a logical 1, and data length is 6, 7, or 8 bits, two stop bits are sent and

checked.

Bits 0 and 1: DLS0, DLS1. These two bits define the number of data bits that are sent or checked in

each serial character.

TABLE 4-2 WORD LENGTH DEFINITION

- 44 -

Page 45

W83877F

DLS1 DLS0 DATA LENGTH

0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits

4.2.2 UART Status Register (USR) (Read/Write)

This 8-bit register provides information about the status of the data transfer during communication.

67 0

RBR Data ready (RDR) Overrun error (OER) Parity bit error (PBER) No stop bit error (NSER) Silent byte detected (SBD) Transmitter Buffer Register empty (TBRE)

Transmitter Shift Register empty (TSRE)

RX FIFO Error Indication (RFEI)

Bit 7: RFEI. In 16450 mode, this bit is always set to a logic 0. In 16550 mode, this bit is set to a logic

1 when there is at least one parity bit error, no stop bit error or silent byte detected in the FIFO. In 16550 mode, this bit is cleared by reading from the USR if there are no remaining errors left in the FIFO.

Bit 6: TSRE. In 16450 mode, when TBR and TSR are both empty, this bit will be set to a logical 1. In

16550 mode, if the transmit FIFO and TSR are both empty, it will be set to a logical 1. Other thanthese two cases, this bit will be reset to a logical 0.

Bit 5: TBRE. In 16450 mode, when a data character is transferred from TBR to TSR, this bit will be

set to a logical 1. If ETREI of ICR is a logical 1, an interrupt will be generated to notify the CPU to write the next data. In 16550 mode, this bit will be set to a logical 1 when the transmit FIFO is empty. It will be reset to a logical 0 when the CPU writes data into TBR or FIFO.

Bit 4: SBD. This bit is set to a logical 1 to indicate that received data are kept in silent state for a full

word time, including start bit, data bits, parity bit, and stop bits. In 16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a logical 0.

Bit 3: NSER. This bit is set to a logical 1 to indicate that the received data have no stop bit. In 16550

mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a logical 0.

Bit 2: PBER. This bit is set to a logical 1 to indicate that the parity bit of received data is wrong. In

16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a logical 0.

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W83877F

DSR

CTS

DCD

RTS

DTR

Bit 1: OER. This bit is set to a logical 1 to indicate received data have been overwritten by the next

received data before they were read by the CPU. In 16550 mode, it indicates the same condition instead of FIFO full. When the CPU reads USR, it will clear this bit to a logical 0.

Bit 0: RDR. This bit is set to a logical 1 to indicate received data are ready to be read by the CPU in

the RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical 0.

4.2.3 Handshake Control Register (HCR) (Read/Write)

This register controls the pins of the UART used for handshaking peripherals such as modem, and controls the diagnostic mode of the UART.

345

Data terminal ready (DTR) Request to send (RTS) Loopback RI input IRQ enable

Internal loopback enable

Bit 4: When this bit is set to a logical 1, the UART enters diagnostic mode by an internal loopback, as

follows:

(1) SOUT is forced to a logical 1, and SIN is isolated from the communication link instead of

the TSR.

(2) Modem output pins are set to their inactive state. (3) Modem input pins are isolated from the communication link and connect internally as DTR

(bit 0 of HCR) →

and IRQ enable ( bit 3 of HCR) →

, RTS ( bit 1 of HCR) →

, Loopback RI input ( bit 2 of HCR) →

Aside from the above connections, the UART operates normally. This method allows the CPU to test the UART in a convenient way.

Bit 3: The UART interrupt output is enabled by setting this bit to a logic 1. In the diagnostic mode this

bit is internally connected to the modem control input

Bit 2: This bit is used only in the diagnostic mode. In the diagnostic mode this bit is internally

connected to the modem control input RI.

Bit 1: This bit controls the

Bit 0: This bit controls the

output. The value of this bit is inverted and output to

- 46 -

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W83877F

DCD

DSR

CTS

DCD

DSR

CTS

4.2.4 Handshake Status Register (HSR) (Read/Write) This register reflects the current state of four input pins for handshake peripherals such as a modem

and records changes on these pins.

1234567 0

toggling (TCTS)

CTS

toggling (TDSR)

DSR

RI falling edge (FERI)

toggling (TDCD)

DCD Clear to send (CTS) Data set ready (DSR) Ring indicator (RI) Data carrier detect (DCD)

Bit 7: This bit is the opposite of the

input. This bit is equivalent to bit 3 of HCR in loopback

mode.

Bit 6: This bit is the opposite of the RI input. This bit is equivalent to bit 2 of HCR in loopback mode. Bit 5: This bit is the opposite of the

input. This bit is equivalent to bit 0 of HCR in loopback

mode. Bit 4: This bit is the opposite of the

input. This bit is equivalent to bit 1 of HCR in loopback

mode. Bit 3: TDCD. This bit indicates that the

pin has changed state after HSR was read by the CPU.

Bit 2: FERI. This bit indicates that the RI pin has changed from low to high state after HSR was read

by the CPU. Bit 1: TDSR. This bit indicates that the Bit 0: TCTS. This bit indicates that the

pin has changed state after HSR was read by the CPU.

4.2.5 UART FIFO Control Register (UFR) (Write only)

This register is used to control the FIFO functions of the UART.

Publication Release Date: January 1996

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W83877F

34567 0

FIFO enable Receiver FIFO reset Transmitter FIFO reset

DMA mode select Reserved Reserved RX interrupt active level (LSB) RX interrupt active level (MSB)

Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if

the interrupt active level is set as 4 bytes, once there are more than 4 data characters in the

receiver FIFO, the interrupt will be activated to notify the CPU to read the data from the FIFO.

TABLE 4-3 FIFO TRIGGER LEVEL

BIT 7 BIT 6 RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)

0 0 01 0 1 04 1 0 08 1 1 14

Bit 4, 5: Reserved Bit 3: When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if

UFR bit 0 = 1. Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to initial state. This bit will clear to

a logical 0 by itself after being set to a logical 1. Bit 1: Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will clear to

a logical 0 by itself after being set to a logical 1. Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1

before other bits of UFR are programmed.

4.2.6 Interrupt Status Register (ISR) (Read only)

This register reflects the UART interrupt status, which is encoded by different interrupt sources into 3 bits.

- 48 -

Page 49

W83877F

1234567

0 0

0 if interrupt pending Interrupt Status bit 0

Interrupt Status bit 1 Interrupt Status bit 2 FIFOs enabled

FIFOs enabled

Bit 7, 6: These two bits are set to a logical 1 when UFR bit 0 = 1. Bit 5, 4: These two bits are always logic 0. Bit 3: In 16450 mode, this bit is 0. In 16550 mode, both bit 3 and 2 are set to a logical 1 when a

time-out interrupt is pending. Bit 2, 1: These two bits identify the priority level of the pending interrupt, as shown in the table below. Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has

occurred, this bit will be set to a logical 0.

TABLE 4-4 INTERRUPT CONTROL FUNCTION

ISR INTERRUPT SET AND FUNCTION

Bit3Bit2Bit1Bit0Interrupt

priority

0 0 0 1 - - No Interrupt pending 0 1 1 0 First UART Receive

0 1 0 0 Second RBR Data Ready 1. RBR data ready

1 1 0 0 Second FIFO Data Timeout Data present in RX FIFO for 4

0 0 1 0 Third TBR Empty TBR empty 1. Write data into TBR

0 0 0 0 Fourth Handshake status 1. TCTS = 1 2. TDSR = 1

** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.

Interrupt Type Interrupt Source Clear Interrupt

Status

1. OER = 1 2. PBER =1

3. NSER = 1 4. SBD = 1

2. FIFO interrupt active level reached

characters period of time since last access of RX FIFO.

3. FERI = 1 4. TDCD = 1

Read USR

1. Read RBR

2. Read RBR until FIFO data under active level

Read RBR

2. Read ISR (if priority is third)

Read HSR

Publication Release Date: January 1996

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W83877F

4.2.7 Interrupt Control Register (ICR) (Read/Write)

This 8-bit register allows the five types of controller interrupts to activate the interrupt output signal separately. The interrupt system can be totally disabled by resetting bits 0 through 3 of the Interrupt Control Register (ICR). A selected interrupt can be enabled by setting the appropriate bits of this register to a logical 1.

0 0 0

Bit 7-4: These four bits are always logic 0.

Bit 3: EHSRI. Setting this bit to a logical 1 enables the handshake status register interrupt.

Bit 2: EUSRI. Setting this bit to a logical 1 enables the UART status register interrupt.

Bit 1: ETBREI. Setting this bit to a logical 1 enables the TBR empty interrupt.

Bit 0: ERDRI. Setting this bit to a logical 1 enables the RBR data ready interrupt.

4.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write)

Two 8-bit registers, BLL and BHL, compose a programmable baud generator that uses 24 MHz to generate a 1.8461 MHz frequency and divides it by a divisor from 1 to 216-1. The output frequency of the baud generator is the baud rate multiplied by 16, and this is the base frequency for the transmitter and receiver. The table below illustrates the use of the baud generator with a frequency of 1.8461 MHz. In high-speed UART mode (refer to CR0C bit7 and CR0C bit6), the programmable baud generator directly uses 24 MHz and the same divisor as the normal speed divisor. In high-speed mode, the data transmission rate can be as high as 1.5M bps.

RBR data ready interrupt enable (ERDRI) TBR empty interrupt enable (ETBREI) UART receive status interrupt enable (EUSRI) Handshake status interrupt enable (EHSRI)

4.2.9 User-defined Register (UDR) (Read/Write)

This is a temporary register that can be accessed and defined by the user.

- 50 -

Page 51

TABLE 4-5 BAUD RATE TABLE

BAUD RATE USING 24 MHZ TO GENERATE 1.8461 MHZ

Desired Baud Rate Decimal divisor used to

generate 16X clock 50 2304 ** 75 1536 **

110 1047 0.18%

134.5 857 0.099% 150 768 ** 300 384 ** 600 192 **

1200 96 ** 1800 64 ** 2000 58 0.53% 2400 48 ** 3600 32 ** 4800 24 ** 7200 16 **

9600 12 ** 19200 6 ** 38400 3 ** 57600 2 **

115200 1 **

W83877F

Percent error difference between

desired and actual

230400 104* ** 460800 52* ** 921600 26* **

1.5M 1* 0%

* Only use in high speed mode (refer CR0C bit7 and CR0C bit6). ** The percentage error for all baud rates, except where indicated otherwise, is 0.16%.

- 51 - Revision A2

Publication Release Date: January 1996

Page 52

W83877F

INDEX

2IINDEX

TRAK

02ITRAK

2IWP

RDATA

2IRDATA

DSKCHG

2IDSKCHG

MOA

5.0 PARALLEL PORT

5.1 Printer Interface Logic

The parallel port of the W83877F makes possible the attachment of various devices that accept eight bits of parallel data at standard TTL level. The W83877F supports an IBM XT/AT compatible parallel port (SPP), bi-directional parallel port (BPP), Enhanced Parallel Port (EPP), Extended Capabilities Parallel Port (ECP), Extension FDD mode (EXTFDD), Extension 2FDD mode (EXT2FDD), Extension Adapter mode (EXTADP), and JOYSTICK mode on the parallel port. Refer to the configuration registers for more information on disabling, power-down, and on selecting the mode of operation.

Table 5-1 shows the pin definitions for different modes of the parallel port. TABLE 5-1 PARALLEL PORT CONNECTOR AND PIN DEFINITIONS

HOST

CONNECTOR

1 19 O nSTB nWrite nSTB

2−9 9−14, 16−17

10 26 I nACK Intr nACK 11 24 I BUSY nWait BUSY, PeriphAck 12 27 I PE PE PEerror, nAckReverse 13 28 I SLCT Select SLCT 14 20 O nAFD nDStrb nAFD, HostAck 15 29 I nERR nError nFault1, nPeriphRequest 16 21 O nINIT nInit nINIT1, nReverseRqst 17 22 O nSLIN nAStrb nSLIN

Notes: n<name > : Active Low

1. Compatible Mode

2. High Speed Mode

3. For more information, refer to the IEEE 1284 standard.

PIN NUMBER

OF W83877F

ATTRIBUTE

I/O PD<0:7> PD<0:7> PD<0:7>

SPP EPP ECP

1, 2

HOST

CONNECTOR

1 19 O nSTB --- --- --- --2 9 I/O PD0 I

3 10 I/O PD1 I 4 11 I/O PD2 I 5 12 I/O PD3 I 6 13 I/O PD4 I

7 14 I/O PD5 --- --- --- --8 15 I/O PD6 OD

PIN NUMBER

OF W83877

ATTRIBUTE

SPP PIN

ATTRIBUTE

EXT2FDD PIN

ATTRIBUTE

--- ---

- 52 -

EXTFDD

Page 53

TABLE 5-1, continued

DSA

DSB

2ODDSB

MOB

2ODMOB

2ODWD

2ODWE

RWC

2ODRWC

NERR

2ODNERR

DIR

2ODDIR

STEP

2ODSTEP

XWR

XRD

XDACK

HOST

CONNECTOR

9 16 I/O PD7 OD 10 26 I nACK OD 11 24 I BUSY OD 12 27 I PE OD 13 28 I SLCT OD 14 20 O nAFD OD 15 29 I nERR OD 16 21 O nINIT OD 17 22 O nSLIN OD

PIN NUMBER

OF W83877

ATTRIBUTE

SPP PIN

ATTRIBUTE

EXT2FDD PIN

ATTRIBUTE

--- ---

W83877F

EXTFDD

HOST

CONNECTOR

1 19 O nSTB O 2 9 I/O PD0 I/O XD0 I JP0

3 10 I/O PD1 I/O XD1 I JP1 4 11 I/O PD2 I/O XD2 I --5 12 I/O PD3 I/O XD3 I --6 13 I/O PD4 I/O XD4 I JB0 7 14 I/O PD5 I/O XD5 I JB1 8 15 I/O PD6 I/O XD6 I ---

9 16 I/O PD7 I/O XD7 I --10 26 I nACK I XDRQ I --11 24 I BUSY I XIRQ I --12 27 I PE O XA0 I --13 28 I SLCT O XA1 I --14 20 O nAFD O

15 29 I nERR O XA2 I --16 21 O nINIT O

17 22 O nSLIN O TC O VDD

PIN NUMBER

OF W83877

ATTRIBUTE

SPP PIN

ATTRIBUTE

EXTADP

MODE

ATTRIBUTE

O VDD

JOYSTICK

MODE

Publication Release Date: January 1996

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Page 54

W83877F

ACK

BUSY

5.2 Enhanced Parallel Port (EPP)

TABLE 5-2 PRINTER MODE AND EPP REGISTER ADDRESS

A2 A1 A0 REGISTER NOTE

0 0 0 Data port (R/W) 1 0 0 1 Printer status buffer (Read) 1 0 1 0 Printer control latch (Write) 1 0 1 0 Printer control swapper (Read) 1 0 1 1 EPP address port (R/W) 2 1 0 0 EPP data port 0 (R/W) 2 1 0 1 EPP data port 1 (R/W) 2 1 1 0 EPP data port 2 (R/W) 2 1 1 1 EPP data port 2 (R/W) 2

Notes:

1. These registers are available in all modes.

2. These registers are available only in EPP mode.

5.2.1 Data Swapper

The system microprocessor can read the contents of the printer's data latch by reading the data swapper.

5.2.2 Printer Status Buffer

The system microprocessor can read the printer status by reading the address of the printer status buffer. The bit definitions are as follows:

235 467 0

1 1

TMOUT ERROR

SLCT PE

ACK

BUSY

Bit 7: This signal is active during data entry, when the printer is off-line during printing, when the print

head is changing position, or during an error state. When this signal is active, the printer is

busy and cannot accept data. Bit 6: This bit represents the current state of the printer's

signal. A 0 means the printer has

received a character and is ready to accept another. Normally, this signal will be active for

approximately 5 microseconds before

stops.

Bit 5: A 1 means the printer has detected the end of paper. Bit 4: A 1 means the printer is selected.

Bit 3: A 0 means the printer has encountered an error condition.

- 54 -

Page 55

W83877F

PRTOE

ACK

Bit 1, 2: These two bits are not implemented and are logic one during a read of the status register. Bit 0: This bit is valid in EPP mode only. It indicates that a 10 µS timeout has occurred on the EPP

bus. A logic 0 means that no time-out error has occurred; a logic 1 means that a time-out error has been detected. Writing a logic 1 to this bit will clear the time-out status bit; writing a logic 0 has no effect.

5.2.3 Printer Control Latch and Printer Control Swapper

The system microprocessor can read the contents of the printer control latch by reading the printer control swapper. Bit definitions are as follows:

234567 0

111

STROBE AUTO FD

INIT SLCT IN IRQ ENABLE DIR

Bit 7, 6: These two bits are a logic one during a read. They can be written. Bit 5: Direction control bit

W83757 (SPP) mode: When this bit is a logic 1, pin

is high, and PRTBEN (CR3 bit 7) is low, the parallel port is in input mode (read); when this bit is a logic 0, the parallel port is in output mode (write). This bit is write-only.

BPP mode: When this bit is a logic 1, the parallel port is in input mode (read); when it is a logic 0, the parallel port is in output mode (write). This bit can be read and written.

Bit 4: A 1 in this position allows an interrupt to occur when

changes from low to high.

Bit 3: A 1 in this bit position selects the printer. Bit 2: A 0 starts the printer (50 microsecond pulse, minimum). Bit 1: A 1 causes the printer to line-feed after a line is printed. Bit 0: A 0.5 microsecond minimum high active pulse clocks data into the printer. Valid data must be

present for a minimum of 0.5 microseconds before and after the strobe pulse.

5.2.4 EPP Address Port

The address port is available only in EPP mode. Bit definitions are as follows:

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W83877F

IOW

IOR

IOW

IOR

1234567 0

PD0 PD1

PD2 PD3 PD4

PD5 PD6 PD7

The contents of DB0-DB7 are buffered (non-inverting) and output to ports PD0-PD7 during a write operation. The leading edge of trailing edge of

latches the data for the duration of the EPP write cycle.

causes an EPP address write cycle to be performed, and the

PD0-PD7 ports are read during a read operation. The leading edge of

causes an EPP address

read cycle to be performed and the data to be output to the host CPU.

5.2.5 EPP Data Port 0-3

These four registers are available only in EPP mode. Bit definitions of each data port are as follows:

123456

PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7

When accesses are made to any EPP data port, the contents of DB0-DB7 are buffered (noninverting) and output to the ports PD0-PD7 during a write operation. The leading edge of an EPP data write cycle to be performed, and the trailing edge of

latches the data for the

causes

duration of the EPP write cycle. During a read operation, ports PD0-PD7 are read, and the leading edge of

causes an EPP read

cycle to be performed and the data to be output to the host CPU.

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W83877F

BUSY

ACK

ERROR

INIT

AUTOFD

STROBE

INIT

AUTOFD

STROBE

5.2.6 Bit Map of Parallel Port and EPP Registers

Data Port (R/W) PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Status Buffer (Read)

Control Swapper (Read) 1 1 1 IRQEN SLIN

Control Latch (Write) 1 1 DIR IRQ SLIN

EPP Address Port (R/W)

EPP Data Port 0 (R/W) PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 EPP Data Port 1 (R/W) PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 EPP Data Port 2 (R/W) PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 EPP Data Port 3 (R/W) PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

5.2.7 EPP Pin Descriptions

EPP NAME TYPE EPP DESCRIPTION

nWrite O Denotes an address or data read or write operation. PD<0:7> I/O Bi-directional EPP address and data bus. Intr I Used by peripheral device to interrupt the host.

PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

PE SLCT

1 1 TMOUT

nWait I Inactive to acknowledge that data transfer is completed. Active to

indicate that the device is ready for the next transfer. PE I Paper end; same as SPP mode. Select I Printer selected status; same as SPP mode. nDStrb O This signal is active low. It denotes a data read or write operation. nError I Error; same as SPP mode. nInits O This signal is active low. When it is active, the EPP device is reset to its

initial operating mode. nAStrb O This signal is active low. It denotes an address read or write operation.

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WAIT

5.2.8 EPP Operation

When the EPP mode is selected in the configuration register, the standard and bi-directional modes are also available. The PDx bus is in the standard or bi-directional mode when no EPP read, write, or address cycle is currently being executed. In this condition all output signals are set by the SPP Control Port and the direction is controlled by DIR of the Control Port.

A watchdog timer is required to prevent system lockup. The timer indicates that more than 10 µS have elapsed from the start of the EPP cycle to the time

is aborted when a time-out occurs. The time-out condition is indicated in Status bit 0. EPP Operation

The EPP operates on a two-phase cycle. First, the host selects the register within the device for subsequent operations. Second, the host performs a series of read and/or write byte operations to the selected register. Four operations are supported on the EPP: Address Write, Data Write, Address Read, and Data Read. All operations on the EPP device are performed asynchronously.

EPP Version 1.9 Operation The EPP read/write operation can be completed under the following conditions: a. If the nWait is active low, when the read cycle (nWrite inactive high, nDStrb/nAStrb active low) or

write cycle (nWrite active low, nDStrb/nAStrb active low) starts, the read/write cycle proceeds normally and will be completed when nWait goes inactive high.

b. If nWait is inactive high, the read/write cycle will not start. It must wait until nWait changes to active low, at which time it will start as described above.

is deasserted. The current EPP cycle

EPP Version 1.7 Operation The EPP read/write cycle can start without checking whether nWait is active or inactive. Once the

read/write cycle starts, however, it will not terminate until nWait changes from active low to inactive high.

5.3 Extended Capabilities Parallel (ECP) Port

This port is software and hardware compatible with existing parallel ports, so it may be used as a

standard printer mode if ECP is not required. It provides an automatic high burst-bandwidth channel that supports DMA for ECP in both the forward (host to peripheral) and reverse (peripheral to host) directions.

Small FIFOs are used in both forward and reverse directions to improve the maximum bandwidth requirement. The size of the FIFO is 16 bytes. The ECP port supports an automatic handshake for the standard parallel port to improve compatibility mode transfer speed.

The ECP port supports run-length-encoded (RLE) decompression (required) in hardware. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated. Hardware support for compression is optional.

For more information about the ECP Protocol, refer to the Extended Capabilities Port Protocol and ISA Interface Standard.

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W83877F

5.3.1 ECP Register and Mode Definitions

NAME ADDRESS I/O ECP MODES FUNCTION

data Base+000h R/W 000-001 Data Register ecpAFifo Base+000h R/W 011 ECP FIFO (Address) dsr Base+001h R All Status Register dcr Base+002h R/W All Control Register cFifo Base+400h R/W 010 Parallel Port Data FIFO ecpDFifo Base+400h R/W 011 ECP FIFO (DATA) tFifo Base+400h R/W 110 Test FIFO cnfgA Base+400h R 111 Configuration Register A cnfgB Base+401h R/W 111 Configuration Register B ecr Base+402h R/W All Extended Control Register

Note: The base addresses are specified by CR23, which are determined by configuration register or hardware setting.

MODE DESCRIPTION

000 SPP mode 001 PS/2 Parallel Port mode 010 Parallel Port Data FIFO mode 011 ECP Parallel Port mode 100 EPP mode (If this option is enabled in the CR9 and CR0 to select ECP/EPP mode) 101 Reserved 110 Test mode 111 Configuration mode

Note: The mode selection bits are bit 7-5 of the Extended Control Register.

5.3.2 Data and ecpAFifo Port

Modes 000 (SPP) and 001 (PS/2) (Data Port) During a wite operation, the Data Register latches the contents of the data bus on the rising edge of

the input. The contents of this register are output to the PD0-PD7 ports. During a read operation, ports PD0-PD7 are read and output to the host. The bit definitions are as follows:

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Address or RLE

7 6 5 4 3 2 1 0

PD0 PD1

PD2 PD3 PD4 PD5 PD6 PD7

Mode 011 (ECP FIFO-Address/RLE) A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The

hardware at the ECP port transmits this byte to the peripheral automatically. The operation of this register is defined only for the forward direction. The bit definitions are as follows:

7 6 5 4 3 2 1 0

Address/RLE

5.3.3 Device Status Register (DSR)

These bits are at low level during a read of the Printer Status Register. The bits of this status register are defined as follows:

7 6 5 4 3 2 1 0

11 1

nFault Select PError nAck nBusy

Bit 7: This bit reflects the complement of the Busy input. Bit 6: This bit reflects the nAck input. Bit 5: This bit reflects the PError input. Bit 4: This bit reflects the Select input. Bit 3: This bit reflects the nFault input. Bit 2-0: These three bits are not implemented and are always logic one during a read.

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W83877F

ACK

SLIN

INIT

AFD

STB

5.3.4 Device Control Register (DCR)

The bit definitions are as follows:

7 6 5 4 3 2 1 0

1 1

strobe autofd nInit SelectIn ackIntEn Direction

Bit 6, 7: These two bits are logic one during a read and cannot be written. Bit 5: This bit has no effect and the direction is always out if mode = 000 or mode = 010. Direction is

valid in all other modes.

0 the parallel port is in output mode. 1 the parallel port is in input mode.

Bit 4: Interrupt request enable. When this bit is set to a high level, it may be used to enable interrupt

requests from the parallel port to the CPU due to a low to high transition on the

Bit 3: This bit is inverted and output to the

0 The printer is not selected. 1 The printer is selected.

Bit 2: This bit is output to the Bit 1: This bit is inverted and output to the Bit 0: This bit is inverted and output to the

5.3.5 cFifo (Parallel Port Data FIFO) Mode = 010

This mode is defined only for the forward direction. The standard parallel port protocol is used by a hardware handshake to the peripheral to transmit bytes written or DMAed from the system to this FIFO. Transfers to the FIFO are byte aligned.

5.3.6 ecpDFifo (ECP Data FIFO) Mode = 011

When the direction bit is 0, bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are byte aligned.

output.

output. output.

input.

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W83877F

When the direction bit is 1, data bytes from the peripheral are read under automatic hardware handshake from ECP into this FIFO. Reads or DMAs from the FIFO will return bytes of ECP data to the system.

5.3.7 tFifo (Test FIFO Mode) Mode = 110

Data bytes may be read, written, or DMAed to or from the system to this FIFO in any direction. Data in the tFIFO will not be transmitted to the parallel port lines. However, data in the tFIFO may be

displayed on the parallel port data lines.

5.3.8 cnfgA (Configuration Register A) Mode = 111

This register is a read-only register. When it is read, 10H is returned. This indicates to the system that this is an 8-bit implementation.

5.3.9 cnfgB (Configuration Register B) Mode = 111

The bit definitions are as follows:

7 6 5 4 3 2 1 0

1 1 1

IRQx 0 IRQx 1 IRQx 2

intrValue

compress

Bit 7: This bit is read-only. It is at low level during a read. This means that this chip does not support

hardware RLE compression. Bit 6: Returns the value on the ISA IRQ line to determine possible conflicts. Bit 5-3: Reflect the IRQ resource assigned for ECP port.

cnfgB[5:3] IRQ resource

000 reflect other IRQ resources selected by PnP register (default) 001 IRQ7 010 IRQ9 011 IRQ10 100 IRQ11 101 IRQ14 110 IRQ15 111 IRQ5

Bit 2-0: These five bits are at high level during a read and can be written.

5.3.11 ecr (Extended Control Register) Mode = all

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W83877F

This register controls the extended ECP parallel port functions. The bit definitions are follows:

7 6 5 4 3 2 1 0

empty full service Intr dmaEn nErrIntrEn MODE MODE

MODE

Bit 7-5: These bits are read/write and select the mode.

000 Standard Parallel Port mode. The FIFO is reset in this mode. 001 PS/2 Parallel Port mode. This is the same as 000 except that direction may be

used to tri-state the data lines and reading the data register returns the value on the data lines and not the value in the data register.

010 Parallel Port FIFO mode. This is the same as 000 except that bytes are written or

DMAed to the FIFO. FIFO data are automatically transmitted using the standard parallel port protocol. This mode is useful only when direction is 0.

011 ECP Parallel Port Mode. When the direction is 0 (forward direction), bytes placed

into the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and transmitted automatically to the peripheral using ECP Protocol. When the direction is 1 (reverse direction) bytes are moved from the ECP parallel port and packed into bytes in the ecpDFifo.

100 Selects EPP Mode. In this mode, EPP is selected if the EPP supported option is

selected. 101 Reserved. 110 Test Mode. The FIFO may be written and read in this mode, but the data will not be

transmitted on the parallel port. 111 Configuration Mode. The confgA and confgB registers are accessible at 0x400 and

0x401 in this mode.

Bit 4: Read/Write (Valid only in ECP Mode)

1 Disables the interrupt generated on the asserting edge of nFault. 0 Enables an interrupt pulse on the high to low edge of nFault. If nFault is asserted

(interrupt) an interrupt will be generated and this bit is written from a 1 to 0.

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Bit 3: Read/Write

1 Enables DMA. 0 Disables DMA unconditionally.

Bit 2: Read/Write

1 Disables DMA and all of the service interrupts. 0 Enables one of the following cases of interrupts. When one of the service interrupts

W83877F

has occurred, the serviceIntr bit is set to a 1 by hardware. This bit must be reset to 0 to re-enable the interrupts. Writing a 1 to this bit will not cause an interrupt.

(a) dmaEn = 1: During DMA this bit is set to a 1 when terminal count is reached. (b) dmaEn = 0 direction = 0: This bit is set to 1 whenever there are writeIntr Threshold or more bytes free in the

FIFO. (c) dmaEn = 0 direction = 1: This bit is set to 1 whenever there are readIntr Threshold or more valid bytes to be

read from the FIFO.

Bit 1: Read only

0 The FIFO has at least 1 free byte. 1 The FIFO cannot accept another byte or the FIFO is completely full.

Bit 0: Read only

0 The FIFO contains at least 1 byte of data. 1 The FIFO is completely empty.

5.3.11 Bit Map of ECP Port Registers

D7 D6 D5 D4 D3 D2 D1 D0 NOTE

data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr

Notes:

1. These registers are available in all modes.

2. All FIFOs use one common 16-byte FIFO.

PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Addr/RLE Address or RLE field 2

nBusy nAck PError Select nFault 1 1 1 1

1 1 Directio ackIntEn SelectIn nInit autofd strobe 1 Parallel Port Data FIFO 2 ECP Data FIFO 2 Test FIFO 2

0 0 0 1 0 0 0 0

compress intrValue 1 1 1 1 1 1

MODE nErrIntrEn dmaEn serviceIntr full empty

5.3.12 ECP Pin Descriptions

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W83877F

NAME TYPE DESCRIPTION

nStrobe (HostClk) O The nStrobe registers data or address into the slave on the

asserting edge during write operations. This signal

handshakes with Busy. PD<7:0> I/O These signals contains address or data or RLE data. nAck (PeriphClk) I This signal indicates valid data driven by the peripheral when

asserted. This signal handshakes with nAutoFd in reverse. Busy (PeriphAck) I This signal deasserts to indicate that the peripheral can

accept data. It indicates whether the data lines contain ECP

command information or data in the reverse direction. When

in reverse direction, normal data are transferred when Busy

(PeriphAck) is high and an 8-bit command is transferred when

it is low. PError (nAckReverse) I This signal is used to acknowledge a change in the direction

of the transfer (asserted = forward). The peripheral drives this

signal low to acknowledge nReverseRequest. The host relies

upon nAckReverse to determine when it is permitted to drive

the data bus. Select (Xflag) I Indicates printer on line. nAutoFd (HostAck) O Requests a byte of data from the peripheral when it is

asserted. This signal indicates whether the data lines contain

ECP address or data in the forward direction. When in forward

direction, normal data are transferred when nAutoFd

(HostAck) is high and an 8-bit command is transferred when it

is low. nFault (nPeriphRequest) I Generates an error interrupt when it is asserted. This signal is

valid only in the forward direction. The peripheral is permitted

(but not required) to drive this pin low to request a reverse

transfer during ECP Mode. nInit (nReverseRequest) O This signal sets the transfer direction (asserted = reverse,

deasserted = forward). This pin is driven low to place the

channel in the reverse direction. nSelectIn (ECPMode) O This signal is always deasserted in ECP mode.

5.3.13 ECP Operation

The host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol before ECP operation. After negotiation, it is necessary to initialize some of the port bits. The following are required:

(a) Set direction = 0, enabling the drivers. (b) Set strobe = 0, causing the nStrobe signal to default to the deasserted state. (c) Set autoFd = 0, causing the nAutoFd signal to default to the deasserted state.

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(d) Set mode = 011 (ECP Mode)

ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo, respectively.

Mode Switching Software will execute P1284 negotiation and all operation prior to a data transfer phase under

programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ECP port only in the data transfer phase (mode 011 or 010).

If the port is in mode 000 or 001 it may switch to any other mode. If the port is not in mode 000 or 001 it can only be switched into mode 000 or 001. The direction can be changed only in mode 001.

When in extended forward mode, the software should wait for the FIFO to be empty before switching back to mode 000 or 001. In ECP reverse mode the software waits for all the data to be read from the FIFO before changing back to mode 000 or 001.

Command/Data ECP mode allows the transfer of normal 8-bit data or 8-bit commands. In the forward direction,

normal data are transferred when HostAck is high and an 8-bit command is transferred when HostAck is low. The most significant bits of the command indicate whether it is a run-length count (for compression) or a channel address.

In the reverse direction, normal data are transferred when PeriphAck is high and an 8-bit command is transferred when PeriphAck is low. The most significant bit of the command is always zero.

Data Compression The W83877F supports run length encoded (RLE) decompression in hardware and can transfer

compressed data to a peripheral. Note that the odd (RLE) compression in hardware is not supported. In order to transfer data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo.

5.3.14 FIFO Operation

The FIFO threshold is set in configuration register 5. All data transfers to or from the parallel port can proceed in DMA or Programmed I/O (non-DMA) mode, as indicated by the selected mode. The FIFO is used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. After a reset, the FIFO is disabled.

5.3.15 DMA Transfers

DMA transfers are always to or from the ecpDFifo, tFifo, or CFifo. The DMA uses the standard PC DMA services. The ECP requests DMA transfers from the host by activating the PDRQ pin. The DMA will empty or fill the FIFO using the appropriate direction and mode. When the terminal count in the DMA controller is reached, an interrupt is generated and serviceIntr is asserted, which will disable the DMA.

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W83877F

MOB

DSB

DSKCHG

RDATA

TRAK

0, INDEX

MOA

MOB

DSB

DSKCHG

RDATA

TRAK

INDEX

5.3.16 Programmed I/O (NON-DMA) Mode

The ECP or parallel port FIFOs can also be operated using interrupt driven programmed I/O. Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo located at 400H, or to/from the tFifo at 400H. The host must set the direction, state, dmaEn = 0 and serviceIntr = 0 in the programmed I/O transfers.

The ECP requests programmed I/O transfers from the host by activating the IRQ pin. The programmed I/O will empty or fill the FIFO using the appropriate direction and mode.

5.4 Extension FDD Mode (EXTFDD)

In this mode, the W83877F changes the printer interface pins to FDC input/output pins, allowing the user to install a second floppy disk drive (FDD B) through the DB-25 printer connector. The pin assignments for the FDC input/output pins are shown in Table 5-1.

After the printer interface is set to EXTFDD mode, the following occur: (1) Pins (2) Pins

serve as input signals to the FDC.

(3) Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for

FDD open drain/collector output.

(4) If the parallel port is set to EXTFDD mode after the system has booted DOS or another operating

system, a warm reset is needed to enable the system to recognize the extension floppy drive.

and

will be forced to inactive state.

, WP,

will be logically ORed with pins PD4-PD0 to

5.5 Extension 2FDD Mode (EXT2FDD)

In this mode, the W83877F changes the printer interface pins to FDC input/output pins, allowing the user to install two external floppy disk drives through the DB-25 printer connector to replace internal floppy disk drives A and B. The pin assignments for the FDC input/output pins are shown in Table 5-

1. After the printer interface is set to EXTFDD mode, the following occur:

(1) Pins (2) Pins

serve as input signals to the FDC.

(3) Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for

FDD open drain/collector output.

(4) If the parallel port is set to EXT2FDD mode after the system has booted DOS or another operating

system, a warm reset is needed to enable the system to recognize the extension floppy drive.

, ,

, and

, WP,

, and

will be logically ORed with pins PD4-PD0 to

5.6 Extension Adapter Mode (EXTADP) (Patent pending)

In this mode, the W83877F redefines the printer interface pins for use as an extension adapter, allowing a pocket peripheral adapter card to be installed through the DB-25 printer connector. The pin assignments for the extension adapter are shown in table 5-1.

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XDO-XD7 are the system data bus for the extension adapter.

XWR

XRD

XDACK

PDACKX

XDACK

PDACKX

XWR

XRD

XWR

XRD

PDACKX

NSTB

AFD

NSLIN

INIT

XA0-XA2 are the system address bus.

W83877F

and

access mode.

, XTC, and XDRQ are used in conjunction with

a DMA cycle.

The extension adapter can issue a DMA request by setting pin XDRQ high, thus sending the W83877F output to the host system by pin PDRQX. The DMA controller should recognize the DMA

request and output a relative DACK to pin without any change from pin

a terminal count (TC) should be issued from the DMA controller to pin TC of W83877F and output to the extension adapter via pin XTC. XIRQ is the interrupt request of the extension adapter. The value of XIRQ coming from the extension adapter will directly pass through pin IRQ7 to the host system.

XIRQ and IRQ7, W83877F pins. Although these pins are defined as DMA and interrupt functions, they can be redefined by users for other specific functions.

5.6.1 Operation

The idea behind EXTADP mode is to treat the parallel port DB-25 connector as an ISA slot, except that its addresses are not issued to the extension adapter. The operation of EXTADP mode is described below:

1. Set the W83877F to EXTADP mode by programming bit 7 of CR7 as low and bit 3 and bit 2 of CR0 as high and low, respectively.

2. The W83877F CR2 is an address register that records the address of the extension adapter. When the desired address is written into CR2, pins

go low and the desired address will also appear on the printer data bus PD7-PD0. Users can logically OR these two signals as an initial reset.

3. After the above two steps, every time the host system issues an IOR or IOW command, the W83877F will compare the I/O address with the CR2 register. If the comparision matches, the

data, low bits addresses (XA2-XA0), and connector.

are the I/O read/write commands with address comparing match or in DMA

, TC, and PDRQX to execute

of the W83877F, which will output the DACK

to the extension adapter. Once the DMA transfer is completed,

and

, and XDRQ and PDRQX are three input/output pairs of

and

will be presented on the parallel port DB-25

of the W83877F will simultaneously

4. DMA operations are handled in the same way as item 3, except that the relevant PDRQX will be active on the DB-25 connector.

5.7 Joystick Mode (Patent pending)

The joystick mode allows users to plug a joystick into the parallel port DB-25 connector. The pin definitions are shown in Table 5-1.

Pins Pins PD5 and PD4 are the button input of the joystick. Pins PD1 and PD0 are the X/Y axis paddle input of the joystick.

, and

output high as a voltage supply to the joystick.

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There are two one-shot timers (556) inside the W83877F for use with the joystick.

GMRD

GMWR

IOR

GMRD

IOW

GMWR

6.0 Game Port Decoder

W83877F

The W83877F provides and I/O read/write commands.

If the host issues specified address, the

and the specified address, the

and

pins that decode game port address as specified in CR1E

pin is low active.

pin is low active; if it issues

and the

7.0 Plug and Play Configuration

A powerful new plug-and-play function has been built into the W83877F to help simplify the task of setting up a computer environment. With appropriate support from BIOS manufacturers, the system designer can freely allocate Winbond I/O devices (i.e., the FDC, PRT, UART, IDE, and game port) in the PC's I/O space (100H - 3FFH). In addition, the W83877F also provides 8 interrupt requests and 3 DMA pairs for designers to assign in interfacing FDCs, UARTs, and PRTs. Hence this powerful I/O chip offers greater flexibility for system designers.

The PnP feature is implemented through a set of Extended Function Registers (CR1E and CR20 to

29). Details on configuring these registers are given in Section 8. The default values of these PnP-

related registers set the system to a configuration compatible with environments designed with previous Winbond I/O chips.

8.0 Extended Function Registers

The W83877F provides many configuration registers for setting up different types of configurations. After power-on reset, the state of the hardware setting of each pin will be latched by the relevant configuration register to allow the W83877F to enter the proper operating configuration. To protect the chip from invalid reads or writes, the configuration registers cannot be accessed by the user.

There are four ways to enable the configuration registers to be read or written. HEFERE (CR0C bit 5) and HEFRAS (CR16 bit 0) can be used to select one out of these four methods of entering the Extended Function mode as follows:

HEFRAS HEFERE address and value

0 0 write 88H to the location 250H 0 1 write 89H to the location 250H (power-on default) 1 0 write 86H to the location 3F0H twice 1 1 write 87H to the location 3F0H twice

First, a specific value must be written once (88H/89H) or twice (86H/87H) to the Extended Functions Enable Register (I/O port address 250H or 3F0H). Second, an index value (00H-17H, 1EH, 20H-29H) must be written to the Extended Functions Index Register (I/O port address 251H or 3F0H) to identify which configuration register is to be accessed. The designer can then access the desired configuration register through the Extended Functions Data Register (I/O port address 252H or 3F1H).

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W83877F

After programming of the configuration register is finished, an additional value should be written to EFERs to exit the Extended Function mode to prevent unintentional access to those configuration registers. In the case of EFER at 250H, this additional value can be any value other than 88H if HEFERE = 0 and 89H if HEFERE = 1. While EFER is at 3F0H, this additional value must be AAH. The designer can also set bit 6 of CR9 (LOCKREG) to high to protect the configuration registers against accidental accesses.

The configuration registers can be reset to their default or hardware settings only by a cold reset (pin MR = 1). A warm reset will not affect the configuration registers.

8.1 Extended Functions Enable Registers (EFERs)

After a power-on reset, the W83877F enters the default operating mode. Before the W83877F enters the extended function mode, a specific value must be programmed into the Extended Function Enable Register (EFER) so that the extended function register can be accessed. The Extended Function Enable Registers are write-only registers. On a PC/AT system, their port addresses are 250H or 3F0H (as described in the above section).

8.2 Extended Function Index Registers (EFIRs), Extended Function Data Registers

(EFDRs)

After the extended function mode is entered, the Extended Function Index Register (EFIR) must be loaded with an index value (0H, 1H, 2H, ..., or 29H) to access Configuration Register 0 (CR0), Configuration Register 1 (CR1), Configuration Register 2 (CR2), and so forth through the Extended Function Data Register (EFDR). The EFIRs are write-only registers with port address 251H or 3F0H (as described in section 8.0) on PC/AT systems; the EFDRs are read/write registers with port address 252H or 3F1H (as described in section 8.0) on PC/AT systems. The function of each configuration register is described below.

8.2.1 Configuration Register 0 (CR0), default = 00H

When the device is in Extended Function mode and EFIR is 0H, the CR0 register can be accessed through EFDR. The bit definitions for CR0 are as follows:

7 6 5 4 3 2 1 0

OCSS0

OCSS1 PRTMODS0 PRTMODS1

reserved

Bit 7-Bit 4: Reserved. PRTMOD1 PRTMOD0 (Bit 3, Bit 2):

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W83877F

These two bits and PRTMOD2 (CR9 bit7) determine the parallel port mode of the W83877 (see Table 7-1 on next page ).

Table 7-1

PRTMODS2

(BIT 7 OF CR9)

0 0 0 W83757 0 0 1 EXTFDC 0 1 0 EXTADP 0 1 1 EXT2FDD 1 0 0 JOYSTICK 1 0 1 EPP/SPP 1 1 0 ECP 1 1 1 ECP/EPP

00 W83757 Mode (Default), PRTMOD2 = 0

Default state after power-on reset. In this mode, the W83877F is fully compatible with

the W83757F/W83757AF. 01 Extension FDD Mode (EXTFDD), PRTMOD2 = 0 10 Extension Adapter Mode (EXTADP), PRTMOD2 = 0 11 Extension 2FDD Mode (EXT2FDD), PRTMOD2 = 0 00 JOYSTICK Mode, PRTMOD2 = 1 01 EPP Mode and SPP Mode, PRTMOD2 = 1 10 ECP Mode, PRTMOD2 = 1 11 ECP Mode and EPP Mode, PRTMOD2 = 1

PRTMOD1

(BIT 3 OF CR0)

PRTMODS0

(BIT 2 OF CR0)

OSCS1, OSCS0 (Bit 1, Bit 0): These two bits and OSCS2 (CR6 bit 6) are used to select one of the W83877F's power-down

functions. These bits may be programmed in four different ways:

00 Default power-on state after power-on reset (OSCS2 = 0). 00 OSC on, 24 MHz clock is stopped internally (OSCS2 = 1). Clock can be restarted by

clearing OSCS2. 01 Immediate power-down (IPD) state, OSCS2 = 0

When bit 0 is 1 and bit 1 is set to 0, the W83877F will stop its oscillator and enter power-down mode immediately. The W83877F will not leave the power-down mode until either a system power-on reset from the MR pin or these two bits are used to program the chip back to power-on state. After leaving the power-down mode, the W83877F must wait 128 mS for the oscillator to stabilize.

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W83877F

10 Standby for automatic power-down (APD), OSCS2 = 0

When bit 1 is set to 1 and bit 0 is set to 0, the W83877F will stand by for automatic power-down. A power-down will occur when the following conditions obtain:

• FDC not busy

• FDD motor off

• Interrupt source of line status, modem status, and data ready is inactive (neglecting IER

enable/disable)

• Master Reset inactive

• SOUTA and SOUTB in idle state

• SINA and SINB in idle state

• No register read or write to chip

If all of these conditions are met, a counter begins to count down. While the timer is counting down, the W83877F remains in normal operating mode, and if any of the above conditions changes, the counter will be reset. If the set time (set by bit 7 and bit 6 of CR8) elapses without a change in any of the above conditions, bits 1 and 0 will be set to (1, 1) and the chip will enter automatic power-down mode. The oscillator of the W83877F will remain running, but the internal clock will be disabled to save power. Once the above conditions are no longer met, the internal clock will be resupplied and the chip will return to normal operation.

11 Automatic power-down (ADP) state, OSCS2 = 0

The W83877F enters this state automatically after the counter described above has counted down. If there is a change in any of the conditions listed above, the W83877F 's clock will be restarted and bits 1 and 0 will be set to (1, 0), i.e., standby for automatic power-down. When the clock is restarted, the chip is ready for normal operation, with no need to wait for the oscillator to stabilize.

8.2.2 Configuration Register 1 (CR1), default = 00H

When the device is in Extended Function mode and EFIR is 01H, the CR1 register can be accessed through EFDR. The bit definitions are as follows:

7 6 5 4 3 2 1 0

reserved reserved reserved reserved reserved reserved reserved ABCHG

Bit 0-bit 6: Reserved. ABCHG (Bit 7):

This bit enables the FDC AB Change Mode. Default to be enabled at power-on reset.

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W83877F

XRD

XWR

XRD

XWR

0 Drives A and B assigned as usual 1 Drive A and drive B assignments exchanged

8.2.3 Configuration Register 2 (CR2), default = 00H

When the device is in Extended Function mode and EFIR is 02H, the CR2 register can be accessed through EFDR. The bit definitions are as follows:

7 6 5 4 3 2 1 0

CEA EA3 EA4 EA5 EA6 EA7 EA8 EA9

When the W83877F is programmed into extension adapter mode, the contents of this register are a base address for the extension adapter. When base addresses EA3-EA9 are written into CR2, both

the

and

pins will be active low simultaneously and an adapter connected to the parallel

port can latch the same base address through pins XD1-XD7. After the base address is latched into CR2, a subsequent read/write cycle to this same base address will generate an

signal.

If CEA is set to 0, then the W83877F will compare system addresses SA9-SA3 with EA9-EA3 to generate a compare-equal signal for this read/write command to access the Extension adapter. If CEA is set to 1, then only EA9-EA4 are used in this comparison.

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W83877F

GMRD

GMWR

8.2.4 Configuration Register 3 (CR3), default = 30H

When the device is in Extended Function mode and EFIR is 03H, the CR3 register can be accessed through EFDR. The bit definitions are as follows:

7 6 5 4 3 2 1 0

SUBMIDI SUAMIDI reserved reserved GMODS EPPVER GMENL reserved

SUBMIDI (Bit 0): This bit selects the clock divide rate of UARTB.

0 disables MIDI support, UARTB clock = 24 MHz divided by 13 (default) 1 enables MIDI support, UARTB clock = 24 MHz divided by 12

SUAMIDI (Bit 1): This bit selects the clock divide rate of UARTA.

0 Disables MIDI support, UARTA clock = 24 MHz divided by 13 (default) 1 Enables MIDI support, UARTA clock = 24 MHz divided by 12

Bit 2-bit 3: Reserved.

GMODS (Bit 4): This bit selects the adapter mode or portable mode.

0 Selects the portable mode. Pins 41 and 39 will function as PFDCEN and PEXTEN 1 Selects the adapter mode. Pins 41 and 39 will function as

Note: GMDRQ (CR16 bit 3) has higher precedence over this bit. That is, GMODS selection is only valid when GMGRQ = 0.

and

EPPVER (Bit 5): This bit selects the EPP version of parallel port:

0 Selects the EPP 1.9 version 1 Selects the EPP 1.7 version (default)

Bit 7-bit 6: Reserved.

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W83877F

8.2.5 Configuration Register 4 (CR4), default = 00H

When the device is in Extended Function mode and EFIR is 04H, the CR4 register can be accessed through EFDR. The bit definitions are as follows:

7 6 5 4 3 2 1 0

URBTRI URATRI GMTRI PRTTRI URBPWD URAPWD GMPWD PRTPWD

PRTPWD (Bit 7):

0 Supplies power to the parallel port (default) 1 Puts the parallel port in power-down mode

GMPWD (Bit 6):

0 Supplies power to the game port (default) 1 Puts the game port in power-down mode

URAPWD (Bit 5):

0 Supplies power to COMA (default) 1 Puts COMA in power-down mode

URBPWD (Bit 4):

0 Supplies power to COMB (default) 1 Puts COMB in power-down mode

PRTTRI (Bit 3): This bit enables or disables the tri-state outputs of parallel port in power-down mode.

0 The output pins of the parallel port will not be tri-stated when parallel port is in power-

down mode. (default)

1 The output pins of the parallel port will be tri-stated when parallel port is in power-

down mode.

GMTRI (Bit 2): This bit enables or disables the tri-state outputs of the game port in power-down mode.

0 The output pins of the game port will not be tri-stated when game port is in power-

down mode. (default)

1 The output pins of the game port will be tri-stated when game port is in power-down

mode.

URATRI (Bit 1):

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W83877F

This bit enables or disables the tri-state outputs of UARTA in power-down mode.

0 The output pins of UARTA will not be tri-stated when UARTA is in power-down mode. 1 The output pins of UARTA will be tri-stated when UARTA is in power-down mode.

URBTRI (Bit 0): This bit enables or disables the tri-state outputs of UARTB in power-down mode.

0 The output pins of UARTB will not be tri-stated when UARTB is in power-down mode. 1 The output pins of UARTB will be tri-stated when UARTB is in power-down mode.

8.2.6 Configuration Register 5 (CR5), default = 00H

When the device is in Extended Function mode and EFIR is 05H, the CR5 register can be accessed through EFDR. The bit definitions are as follows:

7 6 5 4 3 2 1 0

ECPFTHR0 ECPFTHR1

ECPFTHR2

ECPFTHR3 Reserved Reserved Reserved

Reserved

Bit 7-4: Reserved ECPFTHR3-0 (bit 3-0): These four bits define the FIFO threshold for the ECP mode parallel port. The

default value is 0000 after power-up.

8.2.7 Configuration Register 6 (CR6), default = 00H

When the device is in Extended Function mode and EFIR is 06H, the CR6 register can be accessed through EFDR. The bit definitions are as follows:

7 6 5 4 3 2 1 0

IDETRI FDCTRI IDEPWD FDCPWD FIPURDWM

SEL4FDD OSCS2

Reserved

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W83877F

DSA

DSB

MOA

MOB

MOA

DSB

DSA

MOB

MOA

DSB

DSA

RDATA

INDEX

TRAK

0,DSKCHG

Bit 7: Reserved OSCS2 (Bit 6): This bit and OSCS1, OSCS0 (bit 1, 0 of CR0) select one of the W83877F's

power-down functions. Refer to descriptions of CR0. (Default to be 0)

SEL4FDD (Bit 5): Selects four FDD mode

0 Selects two FDD mode (default, see Table 7-2) 1 Selects four FDD mode

four drives.

Table 7-2

and

output pins are encoded as show in Table 7-3 to select

DO REGISTER ( 3F2H )

Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 SELECTED

0 0 0 0 0 0 1 1 1 1 -0 0 0 1 0 0 1 0 1 0 FDD A 0 0 1 0 0 1 0 1 0 1 FDD B 0 1 0 0 0 1 1 1 1 1 -1 0 0 0 1 1 1 1 1 1 --

Table 7-3

DO REGISTER ( 3F2H )

Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0

0 0 0 0 X X 1 1 x x -0 0 0 1 0 0 0 0 0 0 FDD A 0 0 1 0 0 1 0 0 0 1 FDD B 0 1 0 0 1 0 0 0 1 0 FDD C 1 0 0 0 1 1 0 0 1 1 FDD D

FIPURDWN (Bit 4):

DRIVE

SELECTED

This bit controls the internal pull-up resistors of the FDC input pins

, and WP. 0 The internal pull-up resistors of FDC are turned on. (default) 1 The internal pull-up resistors of FDC are turned off.

FDCPWD (Bit 3): This bit controls the power to the FDC.

0 Power is supplied to the FDC. (default)

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1 Puts the FDC in power-down mode.

RWC

IDEPWD (Bit 2): This bit controls the power of the IDE.

0 Power is supplied to the IDE. (default) 1 Puts the IDE in power-down mode.

FDCTRI (Bit 1): This bit enables or disables the tri-state outputs of the FDC in power-down mode.

0 The output pins of the FDC will not be tri-stated when FDC is in power-down mode. 1 The output pins of the FDC will be tri-stated when FDC is in power-down mode.

IDETRI (BIt 0): This bit enables or disables the tri-state outputs of the IDE in power-down mode.

0 The output pins of the IDE will not be tri-stated when IDE is in power-down mode. 1 The output pins of the IDE will be tri-stated when IDE is in power-down mode.

W83877F

8.2.8 Configuration Register 7 (CR7), default = 00H

When the device is in Extended Function mode and EFIR is 07H, the CR7 register can be accessed through EFDR. The bit definitions are as follows:

7 6 5 4 3 2 1 0

FDD A type 0 FDD A type 1 FDD B type 0 FDD B type 1 FDD C type 0 FDD C type 1 FDD D type 0 FDD D type 1

FDD A type 1, 0 (Bit 1, 0): These two bits select the type of FDD A.

00 Selects normal mode. When

= 1, the data transfer rate is 500 Kb/s.

Three mode FDD select (EN3MODE = 1):

= 0, selects 1.2 MB high-density FDD.

= 0, the data transfer rate is 250 Kb/s. When

10 11 Don't care

FDD B type 1, 0 (Bit 3, 2):

= 1, selects 1.44 MB high-density FDD.

, selects 720 KB double-density FDD.

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These two bits select the type of FDD B.

RWC

W83877F

00 Selects normal mode. When

= 1, the data transfer rate is 500 Kb/s.

Three mode FDD select (EN3MODE = 1):

01 10 11 Don't care

= 0, selects 1.2 MB high-density FDD. = 1, selects 1.44 MB high-density FDD.

, selects 720 KB double-density FDD.

FDD C type 1, 0 (Bit 5, 4): These two bits select the type of FDD C.

00 Selects normal mode. When

= 1, he data transfer rate is 500 kb/s.

Three mode FDD select (EN 3 MODE = 1):

01 10 11 Don't care

= 0, selects 1.2 MB high-density FDD. = 1, selects 1.44 MB high-density FDD.

, selects 720 KB double-density FDD.

FDD D type 1, 0 (Bit 7, 6): These two bits select the type of FDD D.

00 Selects normal mode. When

= 1, the data transfer rate is 500 Kb/s.

Three mode FDD select (EN3MODE = 1):

= 0, the data transfer rate is 250 Kb/s. When

= 0, the data transfer rate is 250 kb/s. When

= 0, the data transfer rate is 250 Kb/s. When

01 10 11 Don't care

= 0, selects 1.2 MB high-density FDD. = 1, selects 1.44 MB high-density FDD.

, selects 720 KB double-density FDD.

8.2.9 Configuration Register 8 (CR8), default = 00H

When the device is in Extended Function mode and EFIR is 08H, the CR8 register can be accessed through EFDR. The bit definitions are as follows:

7 6 5 4 3 2 1 0

Floppy Boot Drive 0 Floppy Boot Drive 1 Media ID 0 Media ID 1

SWWP DISFDDWR

APDTMS2 APDTMS1

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W83877F

DSKCHG

APDTMS2 APDTMS1 (Bit 6, 7): These two bits select the count-down time of the automatic power-down mode counter.

00 4 seconds 01 32 seconds 10 64 seconds 11 4 minutes

DISFDDWR (Bit 5): This bit enables or disables FDD write data.

0 Enables FDD write 1 Disables FDD write (forces pins WE, WD to stay high)

Once this bit is set high, the FDC operates normally, but because pin write data to diskettes. For example, if a diskette is formatted with DISFDDWR = 1, after the format command has been executed, messages will be displayed that appear to indicate that the format is complete. If the diskette is removed from the disk drive and inserted again, however, typing the DIR command will reveal that the contents of the diskette have not been modified and the diskette was not actually reformatted.

This is because as the operating system (e.g., DOS) reads the diskette files, it keeps the files in memory. If there is a write operation, DOS will write data to the diskette and memory simultaneously. When DOS wants to read the diskette, it will first search the files in memory. If DOS finds the file in memory, it will not issue a read command to read the diskette. When DISFDDWR = 1, DOS still writes data to the diskette and memory, but only the data in memory are updated. If a read operation is performed, data are read from memory first, and not from the diskette. The action of removing the

diskette from the drive and inserting it again forces the contents of the diskette and will show that the contents have not been modified. The same holds true with write commands.

The disable FDD write function allows users to protect diskettes against computer viruses by ensuring that no data are written to the diskette.

SWWP (Bit 4):

0 Normal, use WP to determine whether the FDD is write-protected or not 1 FDD is always write-protected

Media ID 1 Media ID 0 (Bit 3, 2): These two bits hold the media ID bit 1, 0 for three mode

pin active. DOS will then read the

is inactive, the FDD will not

Floppy Boot Drive 1 Floppy Boot Drive 0 (bit 1, 0) These two bits hold the value of floppy boot drive 1 and drive 0 for three mode

8.2.10 Configuration Register 9 (CR9), default = 0AH

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W83877F

RWC

When the device is in Extended Function mode and EFIR is 09H, the CR9 register can be accessed through EFDR. The bit definitions are as follows:

7 6 5 4 3 2 1 0

CHIP ID0 CHIP ID1 CHIP ID2 CHIP ID3

Reserved EN3MODE LOCKREG

PRTMODS2

PRTMODS2 (Bit 7): This bit and PRTMODS1, PRTMODS0 (bits 3, 2 of CR0) select the operating mode of the W83877.

Refer to the descriptions of CR0. LOCKREG (Bit 6):

This bit enables or disables the reading and writing of all configuration registers.

0 Enables the reading and writing of CR0-CR29 1 Disables the reading and writing of CR0-CR29 (locks W83877F extension functions)

EN3MODE (Bit 5): This bit enables or disables three mode FDD selection. When this bit is high, it enables the read/write

3F3H register.

0 Disables 3 mode FDD selection 1 Enables 3 mode FDD selection

When three mode FDD function is enabled, the value of TDR(3F3H). The values of

and their meaning are shown in Table 7-4.

depends on bit 5 and bit 4 of

Table 7-4

BIT 5 OF TDR BIT 4 OF TDR

= 0

= 1

0 0 Normal 250K bps 500K bps 0 1 0 1.2 M FDD X 1 0 1 X 1.4M FDD 1 1 X X X

Bit 4: Reserved. CHIP ID 3, CHIP ID 2, CHIP ID 1, CHIP ID 0 (Bit 3-0): These four bits are read-only bits that contain chip identification information. The value is 0AH for

W83877F during a read.

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W83877F

8.2.11 Configuration Register A (CRA), default = 1FH

When the device is in Extended Function mode and EFIR is 0AH, the CRA register can be accessed through EFDR. The bit definitions are as follows:

7 6 5 4 3 2 1 0

PEXTECPP PEXT ECP PEXT EPP PEXT ADP PDCACT PDIRHOP PEXT ACT PFDCACT

PFDCACT (Bit 7): This bit controls whether PFDCEN (pin 41) is active high or low in portable mode.

0 PFDCEN is active low 1 PFDCEN is active high

PEXTACT (Bit 6): This bit controls whether PEXTEN (pin 39) is active high or low in portable mode. This pin can also

reflect the mode of the parallel port: EXTADP mode, EPP mode, ECP mode, or ECP/EPP mode, or any combination of these modes.

0 PEXTEN is active low 1 PEXTEN is active high

Bit 5: Reserved. PDCACT (Bit 4):

This bit controls whether the PDCIN pin is active high or low.

0 PDCIN is active low 1 PDCIN is active high

PEXTADP (Bit 3): This bit controls whether the PEXTEN pin is active in EXTADP mode.

0 PEXTEN is not active in EXTADP mode 1 PEXTEN is active in EXTADP mode

PEXTEPP (Bit 2): This bit controls whether the PEXTEN pin is active in EPP mode.

0 PEXTEN is not active in EPP mode

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W83877F

RWC

1 PEXTEN is active in EPP mode

PEXTECP (Bit 1): This bit controls whether the PEXTEN pin is active in ECP mode.

0 PEXTEN is not active in ECP mode 1 PEXTEN is active in ECP mode

PEXTECPP (Bit 0): This bit controls whether the PEXTEN pin is active in ECP/EPP mode.

0 PEXTEN is not active in ECP/EPP mode 1 PEXTEN is active in ECP/EPP mode

8.2.12 Configuration Register B (CR0B), default = 0CH

When the device is in Extended Function mode and EFIR is 0BH, the CRB register can be accessed through EFDR. The bit definitions are as follows:

34567

0 0 0

DRV2EN INVERTZ

MFM

IDENT ENIFCHG

Bit 7-5: These bits are reserved and are logic 0 during a read. ENIFCHG (Bit 4):

This bit is active high. When active, it enables host interface mode change, which is determined by IDENT (Bit 3) and MFM (Bit 2).

IDENT (Bit 3): This bit indicates the type of drive being accessed and changes the level on

0 1

will be active low for high data rates (typically used for 3.5" drives) will be active high for high data rates (typically used for 5.25" drives)

(pin 87).

When hardware reset or ENIFCHG is a logic 1, IDENT and MFM select one of three interface modes, as shown in Table 7-5.

Table 7- 5

IDENT MFM INTERFACE

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W83877F

DRV2EN

0 0 Model 30 mode 0 1 PS/2 mode 1 0 AT mode 1 1 AT mode

MFM (Bit 2): This bit and IDENT select one of the three interface modes (PS/2 mode, Model 30, or PC/AT mode).

INTVERTZ (Bit 1): This bit determines the polarity of all FDD interface signals.

0 FDD interface signals are active low 1 FDD interface signals are active high

(Bit 0): PS/2 mode only

When this bit is a logic 0, indicates a second drive is installed and is reflected in status register A.

8.2.13 Configuration Register C (CR0C), default = 28H

When the device is in Extended Function mode and EFIR is 0CH, the CR0C register can be accessed through EFDR. The bit definitions are as follows:

34567

TX2INV RX2INV Reserved URIRSEL Reserved HEFERE TURB TURA

TURA (bit 7):

0 the clock source of UART A is 1.8462 MHZ (24 MHz divide 13) (default) 1 the clock source of UART A is 24 MHz, it can make the baudrate of UART A up to 1.5

MHz

TURB (bit 6):

0 the clock source of UART B is 1.8462 MHz (24 MHz divide 13) (default) 1 the clock source of UART B is 24 MHz, it can make the baudrate of UART A up to 1.5

MHz

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W83877F

HEFERE (bit 5): this bit combines with HEFRAS (CR16 bit 0) to define how to enable Extended

Function Registers.

HEFRAS HEFERE address and value

0 0 write 88H to the location 250H 0 1 write 89H to the location 250H (default) 1 0 write 86H to the location 3F0H twice 1 1 write 87H to the location 3F0H twice

The default value of HEFERE is 1. Bit 4: Reserved. URIRSEL (bit 3):

0 select UART B as IR function. 1 select UART B as normal function.

The default value of URIRSEL is 1. Bit 2: Reserved. RX2INV (bit 1):

0 the SINB pin of UART B function or IRRX pin of IR function in normal condition. 1 inverse the SINB pin of UART B function or IRRX pin of IR function

TX2INV (bit 0):

0 the SOUTB pin of UART B function or IRTX pin of IR function in normal condition. 1 inverse the SOUTB pin of UART B function or IRTX pin of IR function.

8.2.14 Configuration Register D (CR0D), default = a3H

When the device is in Extended Function mode and EFIR is 0DH, the CR0D register can be accessed through EFDR. The bit definitions are as follows:

34567

IRMODE0

IRMODE1 IRMODE2 HDUPLX SIRRX0 SIRRX1 SIRTX0 SIRTX1

SIRTX1 (bit 7): IRTX pin selection bit 1 SIRTX0 (bit 6): IRTX pin selection bit 0

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SIRTX1 SIRTX0 IRTX output on pin

0 0 disabled 0 1 IRTX1 (pin 43) 1 0 IRTX2 (pin 95) 1 1 disabled

SIRRX1 (bit 5): IRRX pin selection bit 1 SIRRX0 (bit 4): IRRX pin selection bit 0

SIRRX1 SIRRX0 IRRX input on pin

0 0 disabled 0 1 IRRX1 (pin 42) 1 0 IRRX2 (pin 94) 1 1 disabled

HDUPLX (bit 3):

0 The IR function is Full Duplex. 1 The IR function is Half Duplex.

W83877F

IRMODE2 (bit 2): IR function mode selection bit 2 IRMODE1 (bit 1): IR function mode selection bit 1 IRMODE0 (bit 0): IR function mode selection bit 0

IR MODE IR FUNCTION IRTX IRRX

00X Disable tri-state high 010* IrDA 011* IrDA Active pulse 3/16 bit time Demodulation into SINB 100 ASK-IR Inverting IRTX pin routed to SINB 101 ASK-IR Inverting IRTX & 500 KHZ clock routed to SINB 110 ASK-IR Inverting IRTX Demodulation into SINB 111* ASK-IR Inverting IRTX & 500 KHZ clock Demodulation into SINB

Note: The notation is normal mode in the IR function.

The SIR schematic diagram for registers CRC and CRD is shown below.

8.2.15 Configuration Register E (CR0E), Configuration Register F (CR0F)

Reserved for testing. Should be kept all 0's.

Active pulse 1.6 µS

Demodulation into SINB

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16550A

UART2

SOUT

SIN

Transmission Time Frame

RX2INV

(CRC.bit1)

MUX

URIRSEL

(CRC.bit3)

IRDA Mod.

3/16

IRDA Mod. Mod1.6u

500KHZ

IRMODE2,1=00

0 MUX

IRMODE0

(CRD.bit0)

0 MUX

IRMODE0

(CRD.bit0)

1 0

MUX

IRMODE2

(CRD.bit2)

IRDA

HUPLX

(CRD.bit3)

MUX 0

IRMODE1 (CRD.bit1)

1 MUX

IRMODE2 (CRD.bit2)

Demodulation

IR-DA

Demodulation

ASK_IR

1 MUX

URIRSEL

(CRC,bit3)

TX2INV CRC.bit0

01 00 10

MUX

SIRRX1~0

CR0D.bit5,4

11,00

01 10

MUX

SIRTX1~0

CRD.bit7,6

W83877F

IRRX1

SIN2

+5V

IRRX2

NCS0

(default)

+5V

disable IRTX1

SOUT2

IRTX2

NCS1

(default)

8.2.16 Configuration Register 10 (CR10), default = 00H

When the device is in Extended Function mode and EFIR is 10H, the CR10 register can be accessed through EFDR. The bit definitions are as follows:

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GIO0AD0 GIO0AD1

GIO0AD2 GIO0AD3

GIO0AD4 GIO0AD5 GIO0AD6 GIO0AD7

GIO0AD7-GIO0AD0 (bit 7-bit 0): GIOP0 (pin 92) address bit 7 - bit 0.

8.2.17 Configuration Register 11 (CR11), default = 00H

When the device is in Extended Function mode and EFIR is 11H, the CR11 register can be accessed through EFDR. The bit definitions are as follows:

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GIO0AD8 GIO0AD9

GIO0AD10 Reserved

Reserved Reserved G0CADM0 G0CADM1

G0CADM1-G0CADM0 (bit 7-bit 6): GIOP0 address bit compare mode selection

G0CADM1 G0CADM0 GIOP0 pin

0 0 compare GIO0AD10-GIO0AD0 with SA10-SA0 0 1 compare GIO0AD10-GIO0AD1 with SA10-SA1 1 0 compare GIO0AD10-GIO0AD2 with SA10-SA2 1 1 compare GIO0AD10-GIO0AD3 with SA10-SA3

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Bit 5-bit 3: Reserved GIO0AD10-GIO0AD8 (bit 2-bit 0): GIOP0 (pin 92) address bit 10-bit 8

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8.2.18 Configuration Register 12 (CR12), default = 00H

When the device is in Extended Function mode and EFIR is 12H, the CR12 register can be accessed through EFDR. The bit definitions are as follows:

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GIO1AD7-GIO1AD0 (bit 7-bit 0): GIOP1 (pin 96) address bit 7-bit 0.

8.2.19 Configuration Register 13 (CR13), default = 00H

When the device is in Extended Function mode and EFIR is 13H, the CR13 register can be accessed through EFDR. The bit definitions are as follows:

GIO1AD0 GIO1AD1

GIO1AD2 GIO1AD3

GIO1AD4 GIO1AD5 GIO1AD6 GIO1AD7

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GIO1AD8 GIO1AD9 GIO1AD10 Reserved Reserved Reserved G1CADM0 G1CADM1

G1CADM1-G1CADM0 (bit 7-bit 6): GIOP1 address bit compare mode selection

G1CADM1 G1CADM0 GIOP1 pin

0 0 compare GIO1AD10-GIO1AD0 with SA10-SA0 0 1 compare GIO1AD10-GIO1AD1 with SA10-SA1 1 0 compare GIO1AD10-GIO1AD2 with SA10-SA2 1 1 compare GIO1AD10-GIO1AD3 with SA10-SA3

Bit 5- bit 3: Reserved GIO1AD10-GIO1AD8 (bit 2-it 0): GIOP1 (pin 96) address bit 10-bit 8

8.2.20 Configuration Register 14 (CR14), default = 00H

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When the device is in Extended Function mode and EFIR is 14H, the CR14 register can be accessed through EFDR. The bit definitions are as follows:

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GIOP0MD2-GIOP0MD0 (bit 7-bit 5): GIOP0 pin mode selection

GIOP0MD2 GIOP0MD1 GIOP0MD0 GIOP0 pin

0 0

0 1

inactive (tri-state) as a data output pin (SD0→GIOP0), when (AEN = L)

AND (NIOW = L) AND (SA10-0 = GIO0AD10-0), the value of SD0 will be present on GIOP0

0 1 0

as a data input pin (GIOP0→SD0), when (AEN = L) AND (NIOR = L) AND (SA10-0 = GIO0AD10-0), the value of GIOP0 will be present on SD0

0 1 1

as a data input/output pin (GIOP0↔SD0). When (AEN = L) AND (NIOW = L) AND (SA10-0 =

GIO0AD10-0), the value of SD0 will be present on GIOP0 When (AEN = L) AND (NIOR = L) AND (SA100 = GIO0AD10-0), the value of GIOP0 will be present on SD0

1 X X as a Chip Select pin, the pin will be active at (AEN =

L) AND (SA10-0 = GIO0AD10-0) OR (NIOR = L) OR (NIOW = L)

GDA0IPI GDA0OPI GCS0IOW GCS0IOR GIO0CSH GIOP0MD0 GIOP0MD1 GIOP0MD2

GIO0CSH(bit 4):

0 the Chip Select pin will be active LOW when (AEN = L) AND (SA10-0 = GIO0AD10-

0) OR (NIOR = L) OR (NIOW = L)

1 the Chip Select pin will be active HIGH when (AEN = L) AND (SA10-0 = GIO0AD10-

0) OR (NIOR = L) OR (NIOW = L)

GCS0IOR (bit 3): See below.

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GCS0IOW (bit 2): See below.

GCS0IOR GCS0IOW

0 0 GIOP0 functions as a Chip Select pin, and will be active when

(AEN = L) AND (SA10-0 = GIO0AD10-0)

0 1 GIOP0 functions as a Chip Select pin, and will be active when

(AEN = L) AND (SA10-0 = GIO0AD10-0) AND (NIOW = L)

1 0 GIOP0 functions as a Chip Select pin, and will be active when

(AEN = L) AND (SA10-0 = GIO0AD10-0) AND (NIOR = L)

1 1 GIOP0 functions as a Chip Select pin, and will be active when

(AEN = L) AND (SA10-0 = GIO0AD10-0) AND (NIOW = L OR

NIOR = L) GDA0OPI (bit 1): See below. GDA0IPI (bit 0): See below.

GDA0OPI GDA0IPI

0 0 0 1

GIOP0 functions as a data pin, and GIOP0→SD0, SD0→GIOP0

GIOP0 functions as a data pin, and inverse GIOP0→SD0,

SD0→GIOP0

1 0

GIOP0 functions as a data pin, and GIOP0→SD0, inverse

SD0→GIOP0

1 1

GIOP0 functions as a data pin, and inverse GIOP0→SD0, inverse

SD0→GIOP0

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8.2.21 Configuration Register 15 (CR15), default = 00H

When the device is in Extended Function mode and EFIR is 15H, the CR15 register can be accessed through EFDR. The bit definitions are as follows:

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GDA0IPI GDA0OPI GCS0IOW GCS0IOR GIO0CSH GIOP0MD0 GIOP0MD1 GIOP0MD2

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GIOP1MD2-GIOP1MD0 (bit 7-bit 5): GIOP1 pin mode selection

GIOP1MD2 GIOP1MD1 GIOP1MD0 GIOP1 pin

0 0 0 inactive (tri-state) 0 0 1

0 1 0

0 1 1

1 X X as a Chip Select pin, the pin will be active at (AEN =

as a data output pin (SD1→GIOP1), when (AEN = L) AND (NIOW = L) AND (SA10-0 = GIO1AD10-0), the value of SD1 will be present on GIOP1

as a data input pin (GIOP1→SD1), when (AEN = L) AND (NIOR = L) AND (SA10-0 = GIO1AD10-0), the value of GIOP1 will be present on SD1

as a data input/output pin (GIOP1↔SD1). When (AEN = L) AND (NIOW = L) AND (SA10-0 = GIO1AD10-0), the value of SD1 will be present on GIOP1 When (AEN = L) AND (NIOR = L) AND (SA100 = GIO1AD10-0), the value of GIOP1 will be present on SD1

L) AND (SA10-0 = GIO1AD10-0) OR (NIOR = L) OR (NIOW = L)

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GIO1CSH (bit 4):

0 the Chip Select pin will active LOW when (AEN = L) AND (SA10-0 = GIOAD10-0)

OR (NIOR = L) OR (NIOW = L)

1 the Chip Select pin will active HIGH when (AEN = L) AND (SA10-0 = GIOAD10-0)

OR (NIOR = L) OR (NIOW = L) GCS1IOR (bit 3): See below. GCS1IOW (bit 2): See below.

GCS1IOR GCS1IOW

0 0 GIOP1 functions as a Chip Select pin, and will be active when

0 1 GIOP1 functions as a Chip Select pin, and will be active when

1 0 GIOP1 functions as a Chip Select pin, and will be active when

1 1 GIOP1 functions as a Chip Select pin, and will be active when

GDA0OPI (bit 1): See below.

(AEN = L) AND (SA10-0 = GIO1AD10-0)

(AEN = L) AND (SA10-0 = GIO1AD10-0) AND (NIOW = L)

(AEN = L) AND (SA10-0 = GIO1AD10-0) AND (NIOR = L)

(AEN = L) AND (SA10-0 = GIO1AD10-0) AND (NIOW = L OR NIOR = L)

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GDA1IPI (bit 0): See below.

GDA1OPI GDA1IPI

0 0 0 1

1 0

1 1

8.2.22 Configuration Register 16 (CR16), default = 0eH

When the device is in Extended Function mode and EFIR is 16H, the CR16 register can be accessed through EFDR. The bit definitions are as follows:

GIOP1 functions as a data pin, and GIOP1→SD1, SD1→GIOP1 GIOP1 functions as a data pin, and inverse GIOP1→SD1,

SD1→GIOP1 GIOP1 functions as a data pin, and GIOP1→SD1, inverse

SD1→GIOP1 GIOP1 functions as a data pin, and inverse GIOP1→ SD1, inverse

SD1→GIOP1

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Bit 7-bit 5: Reserved. GOIQSEL (bit 4):

0 pins 92, 96 function as IRQ_B, IRQ_A, respectively.

0 pins 92, 96 function as GIO0, GIO1, respectively. The corresponding power-on setting pin is NRTSB (pin 45). GMDRQ (bit 3):

0 pins 39, 41 function as DRQ_A, NDACK_A, respectively.

1 pins 39, 41 function as NGMWR, NGMRD, respectively. The corresponding power-on setting pin is SOUTB (pin 43). PNPCVS (bit 2):

0 PnP-related registers (CR1E, CR20-29) reset to be all 0s.

1 default settings for these registers. The corresponding power-on setting pin is NRTSA (pin 36).

HEFRAS IRIDE PNPCVS GMDRQ GOIQSEL Reserved Reserved Reserved

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PnP register PNPCVS = 1 PNPCVS = 0

CR1E 81H 00H

CR20 FCH 00H CR21 7CH 00H CR22 FDH 00H CR23 DEH 00H CR24 FEH 00H CR25 BEH 00H CR26 23H 00H CR27 65H 00H CR28 43H 00H CR29 62H 00H

Note: The new value of PNPCVS must be complementary to the old one to make an effective change. For example, the user must set PNPCVS to 1 first and then reset it to 0 to reset these PnP registers if the present value of PNPCVS is 0.

IRIDE (bit 1):

0 pins 1, 91, 94, 95 function as IDE ports. 1 pins 1, 91, 94, 95 function as IR ports.

The corresponding power-on setting pin is SOUTA (pin 38).

pin IRIDE = 0 IRIDE = 1

1 NRSTIDE IRQ_G 91 NIDBEN IRQ_H 94 NCS0 IRRX2 95 NCS1 IRTX2

HEFRAS (bit 0): combines with HEFERE (CR0C bit 5) to define how to access Extended Function

Registers (refer to CR0C bit 5 description). The corresponding power-on setting pin is NDTRA (pin 35).

8.2.23 Configuration Register 17 (CR17), default = 00H

When the device is in Extended Function mode and EFIR is 17H, the CR17 register can be accessed through EFDR. The bit definitions are as follows:

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Bit 7-bit 5: Reserved. PRIRQOD (bit4):

0 printer IRQ ports are totem-poles in SPP mode and open-drains in ECP/EPP mode. 1 printer IRQ ports are totem-poles in all modes.

DSFDLGRQ (bit 3):

0 enable FDC legacy mode on IRQ and DRQ selections. DO register bit 3 has effect on

selecting IRQ.

1 disable FDC legacy mode on IRQ and DRQ selections. DO register bit 3 has no effect

on selecting IRQ.

DSUBLGRQ DSUALGRQ DSPRLGRQ DSFDLGRQ PRIRQOD Reserved Reserved Reserved

DSPRLGRQ (bit 2):

0 enable PRT legacy mode on IRQ and DRQ selections. DCR bit 4 has effect on

selecting IRQ.

1 disable PRT legacy mode on IRQ and DRQ selections. DCR bit 4 has no effect on

selecting IRQ.

DSUALGRQ (bit 1):

0 enable UART A legacy mode on IRQ selection. MCR bit 3 has effect on selecting IRQ. 1 disable UART A legacy mode on IRQ selection. MCR bit 3 has no effect on selecting

IRQ.

DSUBLGRQ (bit 0):

0 enable UART B legacy mode on IRQ selection. MCR bit 3 has effect on selecting IRQ. 1 disable UART B legacy mode on IRQ selection. MCR bit 3 has no effect on selecting

IRQ.

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8.2.24 Configuration Register 1E (CR1E)

When the device is in Extended Function mode and EFIR is 1EH, the CR1E register can be accessed through EFDR. Default = 81H if CR16 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions are as follows:

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This register is used to select the base address of Game Chip Select Decoder (GAMECS) from 100H3F0H on 16-byte boundaries. NCS = 0 and A10 = 0 are required to qualify the GAMECS output.

GMAD7-GMAD2 (bit 7-bit 2): match A[9:4]. GMAS1-GMAS0 (bit 1-bit 0): CAMECS configuration.

GMAS0 GMAS1 GMAD2 GMAD3 GMAD4 GMAD5 GMAD6 GMAD7

00 GAMECS disable 01 1-byte decode, A[3:0] = 0001b 10 8-byte decode, A[3:0] = 0xxxb 11 16-byte decode, A[3:0] = xxxxb

8.2.25 Configuration Register 20 (CR20)

When the device is in Extended Function mode and EFIR is 20H, the CR20 register can be accessed through EFDR. Default = FCH if CR16 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions are as follows:

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Reserved Reserved FDCAD2 FDCAD3 FDCAD4 FDCAD5 FDCAD6 FDCAD7

This register is used to select the base address of the Floppy Disk Controller (FDC) from 100H-3F0H on 16-byte boundaries. NCS = 0 and A10 = 0 are required to access the FDC registers. A[3:0] are always decoded as 0xxxb.

FDCAD7-FDCAD2 (bit 7-bit 2): match A[9:4]. Bit 7 = 0 and bit 6 = 0 disable this decode. Bit 1-bit 0: Reserved, fixed at zero.

8.2.26 Configuration Register 21 (CR21)

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When the device is in Extended Function mode and EFIR is 21H, the CR21 register can be accessed through EFDR. Default = 7CH if CR16 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions are as follows:

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This register is used to select the base address of the IDE Interface Control Registers from 100H3F0H on 16-byte boundaries. NCS = 0 and A10 = 0 are required to access the IDE registers. A[3:0] are always decoded as 0xxxb.

IDE0AD7-IDE0AD2 (bit 7-bit 2): match A[9:4]. Bit 7 = 0 and bit 6 = 0 disable this decode. Bit 1-bit 0: Reserved, fixed at zero.

Reserved Reserved IDE0AD2 IDE0AD3 IDE0AD4 IDE0AD5 IDE0AD6 IDE0AD7

8.2.27 Configuration Register 22 (CR22)

When the device is in Extended Function mode and EFIR is 22H, the CR22 register can be accessed through EFDR. Default = FDH if CR16 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions are as follows:

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Reserved Reserved IDE1AD2 IDE1AD3 IDE1AD4 IDE1AD5 IDE1AD6 IDE1AD7

This register is used to select the base address of the IDE Interface Alternate Status Register from 106H-3F6H on 16-byte boundaries + 6. NCS = 0 and A10 = 0 are required to access the IDE Alternate Status register. A[3:0] must be 0110b.

IDE1AD7-IDE1AD2 (bit 7-bit 2): match A[9:4]. Bit 7 = 0 and bit 6 = 0 disable this decode. Bit 1: Reserved, fixed at zero. Bit 0: Reserved, fixed at one.

8.2.28 Configuration Register 23 (CR23)

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When the device is in Extended Function mode and EFIR is 23H, the CR23 register can be accessed through EFDR. Default = DEH if CR16 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions are as follows:

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This register is used to select the base address of the parallel port. If EPP is disable, the parallel port can be set from 100H-3FCH on 4-byte boundaries. If EPP is enable, the parallel port can be set from 100H-3F8H on 8-byte boundaries. NCS = 0 and A10 = 0 are required to access the parallel port when in compatible, bi-directional, or EPP modes. A10 is active in ECP mode.

PRTAD7-PRTAD0 (bit 7-bit 0): match A[9:2]. Bit 7 = 0 and bit 6 = 0 disable this decode.

PRTAD0 PRTAD1 PRTAD2 PRTAD3 PRTAD4 PRTAD5 PRTAD6 PRTAD7

8.2.29 Configuration Register 24 (CR24)

When the device is in Extended Function mode and EFIR is 24H, the CR24 register can be accessed through EFDR. Default = FEH if CR16 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions are as follows:

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Reserved URAAD1 URAAD2 URAAD3 URAAD4 URAAD5 URAAD6 URAAD7

This register is used to select the base address of the UART A from 100H-3F8H on 8-byte boundaries. NCS = 0 and A10 = 0 are required to access the UART A registers. A[2:0] are don't-care conditions.

URAAD7-URAAD1 (bit 7-bit 1): match A[9:3]. Bit 7 = 0 and bit 6 = 0 disable this decode. Bit 0: Reserved, fixed at zero.

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8.2.30 Configuration Register 25 (CR25)

When the device is in Extended Function mode and EFIR is 25H, the CR25 register can be accessed through EFDR. Default = BEH if CR16 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions are as follows:

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This register is used to select the base address of the UART B from 100H-3F8H on 8-byte boundaries. NCS = 0 and A10 = 0 are required to access the UART B registers. A[2:0] are don't-care conditions.

URBAD7-URBAD1 (bit 7-bit 1): match A[9:3]. Bit 7 = 0 and bit 6 = 0 disable this decode.

Reserved URBAD1 URBAD2 URBAD3 URBAD4 URBAD5 URBAD6 URBAD7

Bit 0: Reserved, fixed at zero.

8.2.31 Configuration Register 26 (CR26)

When the device is in Extended Function mode and EFIR is 26H, the CR26 register can be accessed through EFDR. Default = 23H if CR16 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions are as follows:

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PRTDQS0 PRTDQS1 PRTDQS2 PRTDQS3 FDCDQS0 FDCDQS1 FDCDQS2 FDCDQS3

FDCDQS3-FDCDQS0 (bit 7-bit 4): Allocate DMA resource for FDC. PRTDQS3-PRTDQS0 (bit 3-bit 0): Allocate DMA resource for PRT.

bit 7- bit4, bit 3 - bit 0 DMA selected

0000 None 0001 DMA_A 0010 DMA_B 0011 DMA_C

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8.2.32 Configuration Register 27 (CR27)

When the device is in Extended Function mode and EFIR is 27, the CR27 register can be accessed through EFDR. Default = 05H if CR6 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions are as follows:

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ECPIRQx2-ECPIRQx0 (bit7-bit 5): These bits are configurable equivalents to bit[5:3] of cnfgB register in ECP mode except that cnfgB[5:3] are read-only bits. They indicate the IRQ resource assigned for the ECP printer port. It is the software designer's responsibility to ensure that CR27[7:5] and CR27[3:0] are consistent. For example, CR27[7:5] should be filled with 001 (select IRQ 7) if CR27[3:0] are to be programmed as 0101 (select IRQ_E) while IRQ_E is connected to IRQ 7.

PRTIQS0 PRTIQS1 PRTIQS2 PRTIQS3 Reserved ECPIRQx0 ECPIRQx1 ECPIRQx2

CR27[7:5] IRQ resource

000 reflect other IRQ resources selected by CR27[3:0] (default) 001 IRQ 7 010 IRQ 9 011 IRQ 10 100 IRQ 11 101 IRQ 14 110 IRQ 15 111 IRQ 5

Bit 4: Reserved. PRTIQS3-PRTIQS0 (bit 3-bit 0): Select IRQ resource for the parallel port. Any unselected IRQ is in

tristate.

CR27[3:0] IRQ selected

0000 None 0001 IRQ_A 0010 IRQ_B 0011 IRQ_C 0100 IRQ_D 0101 IRQ_E 0110 IRQ_F 0111 IRQ_G 1000 IRQ_H

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