Datasheet W83782D Datasheet (Winbond Electronics)

W83782D Winbond H/W Monitoring IC

W83782D Data Sheet Revision History

Pages Dates Version Version

1

2

3

4

5

6

7

8

9

10

n.a. n.a. All the version before 0.50 are for internal use.

n.a. 98/7 0.5 n.a. First publication.

P.40 99/4 0.55 A1 Add the content of Diode Selection Register Index

P.42 99/4 0.55 A1 Add the content of VBAT Monitor Control Register

Main Contents

on Web

59h(Bank0)

Index 5Dh (Bank0)

Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.

Preliminary W83782D

TABLE OF CONTENTS

1. GENERAL DESCRIPTION ............................................................................................1

2. FEATURES.......................................................................................................................2

2.1 MONITORING ITEMS .........................................................................................................................2

2.2 ACTIONS ENABLING .........................................................................................................................2

2.3 GENERAL ............................................................................................................................................ 2

2.4 PACKAGE............................................................................................................................................2

3. KEY SPECIFICATIONS.................................................................................................3

4. PIN CONFIGURATION..................................................................................................3

5. PIN DESCRIPTION.........................................................................................................4

6. FUNCTIONAL DESCRIPTION......................................................................................7

6.1 GENERAL DESCRIPTION ...................................................................................................................7

6.2 ACCESS INTERFACE ..........................................................................................................................7

6.2.1 ISA interface .................................................................................................................................7

6.2.2 I2C interface.................................................................................................................................. 9

6.2.3 The first serial bus access timing are shown as follow: ...................................................................9

6.2.4 The serial bus timing of the temperature 2 and 3 is shown as follow:...........................................11

6.3 ANALOG INPUTS.............................................................................................................................. 14

6.3.1 Monitor over 4.096V voltage:......................................................................................................15

6.3.2 Monitor negative voltage:............................................................................................................15

6.3.3 Monitor temperature from thermistor:..........................................................................................16

6.3.4 Monitor temperature from Pentium IITM thermal diode or bipolar transistor 2N3904 .................16

6.4 FAN SPEED COUNT AND FAN SPEED CONTROL.........................................................................17

6.4.1 Fan speed count........................................................................................................................... 17

6.4.2 Fan speed control......................................................................................................................... 19

Publication Release Date: April 1999

- I - Version A1

Preliminary W83782D

6.5 TEMPERATURE MEASUREMENT MACHINE................................................................................20

6.5.1 The W83782D temperature sensor 1 SMI# interrupt has two modes: ...........................................21

6.5.2 The W83782D temperature sensor 2 and sensor 3 SMI# interrupt has two modes and it is

programmed at CR[4Ch] bit 6.....................................................................................................22

6.5.3 The W83782D temperature sensor 2 and 3 Over-Temperature (OVT) has two modes, and they are programmed at Bank1 and Bank2 CR[52h] bit1 . These two bits needs to be programmed the same

value. ...........................................................................................................................................23

7. REGISTERS AND RAM ............................................................................................... 24

7.1 ADDRESS REGISTER (PORT X5H) .................................................................................................. 24

7.2 DATA REGISTER (PORT X6H)......................................................................................................... 25

7.3 CONFIGURATION REGISTER ¾ INDEX 40H...................................................................................26

7.4 INTERRUPT STATUS REGISTER 1¾ INDEX 41H............................................................................ 26

7.5 INTERRUPT STATUS REGISTER 2 ¾ INDEX 42H........................................................................... 27

7.6 SMI# MASK REGISTER 1 ¾ INDEX 43H..........................................................................................28

7.7 SMI# MASK REGISTER 2 ¾ INDEX 44H..........................................................................................28

7.8 RESERVED REGISTER ¾ INDEX 45H..............................................................................................29

7.9 CHASSIS CLEAR REGISTER -- INDEX 46H .................................................................................... 29

7.10 VID/FAN DIVISOR REGISTER ¾ INDEX 47H................................................................................29

7.11 SERIAL BUS ADDRESS REGISTER ¾ INDEX 48H........................................................................30

7.12 VALUE RAM ¾ INDEX 20H- 3FH OR 60H - 7FH (AUTO-INCREMENT).......................................31

7.13 VOLTAGE ID (VID4) & DEVICE ID - 49H .....................................................................................33

7.14 TEMPERATURE 2 AND TEMPERATURE 3 SERIAL BUS ADDRESS REGISTER--INDEX 4AH .33

7.15 PIN CONTROL REGISTER - INDEX 4BH.......................................................................................34

7.16 IRQ#/OVT# PROPERTY SELECT - INDEX 4CH.............................................................................35

7.17 FAN IN/OUT AND BEEP/GPO# CONTROL REGISTER - INDEX 4DH..........................................36

7.18 REGISTER 50H ~ 5FH BANK SELECT - INDEX 4EH (NO AUTO INCREASE) ............................37

- II -

Preliminary W83782D

7.19 WINBOND VENDOR ID - INDEX 4FH (NO AUTO INCREASE)....................................................37

7.20 WINBOND TEST REGISTER -- INDEX 50H - 55H (BANK 0).......................................................38

7.21 BEEP CONTROL REGISTER 1-- INDEX 56H (BANK 0)................................................................38

7.22 BEEP CONTROL REGISTER 2-- INDEX 57H (BANK 0)................................................................39

7.23 CHIP ID -- INDEX 58H (BANK 0)....................................................................................................40

7.24 DIODE SELECTION REGISTER -- INDEX 59H (BANK 0)............................................................ 40

7.25 PWMOUT2 CONTROL -- INDEX 5AH (BANK 0)....................................................................... 40-A

7.26 PWMOUT1 CONTROL -- INDEX 5BH (BANK 0) ...........................................................................41

7.27 PWMOUT1/2 CLOCK SELECT -- INDEX 5CH (BANK 0)..............................................................41

7.28 VBAT MONITOR CONTROL REGISTER -- INDEX 5DH (BANK 0).............................................. 42

7.29 PWMOUT3 CONTROL -- INDEX 5EH (BANK 0) ........................................................................... 43

7.30 PWMOUT4 CONTROL -- INDEX 5FH (BANK 0)............................................................................ 43

7.31 TEMPERATURE SENSOR 2 TEMPERATURE (HIGH BYTE) REGISTER - INDEX 50H (BANK1)44

7.32 TEMPERATURE SENSOR 2 TEMPERATURE (LOW BYTE) REGISTER - INDEX 51H (BANK1)44

7.33 TEMPERATURE SENSOR 2 CONFIGURATION REGISTER - INDEX 52H (BANK1)...................45

7.34 TEMPERATURE SENSOR 2 HYSTERESIS (HIGH BYTE) REGISTER - INDEX 53H (BANK 1) .. 46

7.35 TEMPERATURE SENSOR 2 HYSTERESIS (LOW BYTE) REGISTER - INDEX 54H (BANK 1)...46

7.36 TEMPERATURE SENSOR 2 OVER-TEMPERATURE (HIGH BYTE) REGISTER - INDEX 55H

(BANK 1) ............................................................................................................................................47

7.37 TEMPERATURE SENSOR 2 OVER-TEMPERATURE (LOW BYTE) REGISTER - INDEX 56H

(BANK 1) ............................................................................................................................................47

7.38 TEMPERATURE SENSOR 3 TEMPERATURE (HIGH BYTE) REGISTER - INDEX 50H (BANK2)48

7.39 TEMPERATURE SENSOR 3 TEMPERATURE (LOW BYTE) REGISTER - INDEX 51H (BANK2)48

7.40 TEMPERATURE SENSOR 3 CONFIGURATION REGISTER - INDEX 52H (BANK 2)..................48

7.41 TEMPERATURE SENSOR 3 HYSTERESIS (HIGH BYTE) REGISTER - INDEX 53H (BANK 2) .. 49

7.42 TEMPERATURE SENSOR 3 HYSTERESIS (LOW BYTE) REGISTER - INDEX 54H (BANK 2)...49

7.43 TEMPERATURE SENSOR 3 OVER-TEMPERATURE (HIGH BYTE) REGISTER - INDEX 55H

(BANK 2) ............................................................................................................................................50

7.44 TEMPERATURE SENSOR 3 OVER-TEMPERATURE (LOW BYTE) REGISTER - INDEX 56H

(BANK 2) ............................................................................................................................................50

7.45 INTERRUPT STATUS REGISTER 3¾ INDEX 50H (BANK4).......................................................... 51

7.46 SMI# MASK REGISTER 3 ¾ INDEX 51H (BANK 4).......................................................................51

7.47 BEEP CONTROL REGISTER 3-- INDEX 53H (BANK 4)................................................................52

7.48 RESERVED REGISTER - INDEX 54H--58H (BANK 4)...................................................................52

Publication Release Date: April 1999

- III - Version A1

Preliminary W83782D

7.49 REAL TIME HARDWARE STATUS REGISTER I -- INDEX 59H (BANK 4) ..................................53

7.50 REAL TIME HARDWARE STATUS REGISTER II -- INDEX 5AH (BANK 4)................................54

7.51 REAL TIME HARDWARE STATUS REGISTER III -- INDEX 5BH (BANK 4)...............................54

7.52 PWMOUT3/4 CLOCK SELECT -- INDEX 5CH (BANK 4)..............................................................55

7.53 VALUE RAM 2¾ INDEX 50H - INDEX 5AH (AUTO-INCREMENT) (BANK 5)............................ 56

7.54 WINBOND TEST REGISTER - INDEX 50H (BANK 6)...................................................................56

8. SPECIFICATIONS ........................................................................................................ 57

8.1 ABSOLUTE MAXIMUM RATINGS................................................................................................... 57

8.2 DC CHARACTERISTICS ................................................................................................................... 57

8.3 AC Characteristics...............................................................................................................................59

8.3.1 ISA Read/Write Interface Timing................................................................................................59

8.3.2 Serial Bus Timing Diagram......................................................................................................... 60

9. HOW TO READ THE TOP MARKING......................................................................61

10. PACKAGE DIMENTIONS..........................................................................................62

11. APPLICATION CIRCUIT OF WINBOND W83782D / 781D ...................................63

- IV -

Priliminary W83782D

WINBOND H/W MONITORING IC

1. GENERAL DESCRIPTION

W83782D is an evolving version of W83782D --- Winbond's most popular hardware status monitoring IC. The W83782D can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system to work stable and properly. W83782D provides both ISA and I2C serial bus interface.

An 8-bit analog-to-digital converter (ADC) was built inside W83782D. The W83782D can simultaneously monitor 9 analog voltage inputs, 2 fan tachometer inputs, 3 remote temperature, one case-open detection signal. The remote temperature sensing can be performed by thermistors, or 2N3904 NPN-type transistors, or directly from IntelTM Deschutes CPU thermal diode output. Also the W83782D provides: 4 PWM (pulse width modulation) outputs for the fan speed control; beep tone output for warning; SMI#, OVT#, GPO# signals for system protection events.

Through the application software or BIOS, the users can read all the monitored parameters of system from time to time. And a pop-up warning can be also activated when the monitored item was out of the proper/preset range. The application software could be Winbond's Hardware DoctorTM, or Intel LDCM (LanDesk Client Management), or other management application software. Also the users can set up the upper and lower limits (alarm thresholds) of these monitored parameters and to activate one programmable and maskable interrupts. An optional beep tone could be used as warning signal when the monitored parameters is out of the preset range.

TM

Additionally, 5 VID inputs are provided to read the VID of CPU (i.e. PentiumTM II) if applicable. This is to provide the Vcore voltage correction automatically. Also W83782D uniquely provides an optional feature: early stage (before BIOS was loaded) beep warning. This is to detect if the fatal elements present --- Vcore or +3.3V voltage fail, and the system can not be boomed up. Also there are 3 specific pins to provide selectable address setting for application of multiple devices (up to 8 devices) wired through I2CTM interface.

Publication Release Date: April 1999

- 1 - Revision A1

Preliminary W83782D

2. FEATURES

2.1 Monitoring Items

• 3 thermal inputs from remote thermistors or 2N3904 NPN-type transistors or PentiumTM II (Deschutes) thermal diode output

• 9 voltage inputs

--- typical for Vcore, +3.3V, +12V, -12V, +5V, -5V, +5V Vsb, Vbat, and one reserved

• 3 fan speed monitoring inputs

• Case open detection input

• WATCHDOG comparison of all monitored values

• Programmable hysteresis and setting points (alarm thresholds) for all monitored items

2.2 Actions Enabling

• Beep tone warning

•

4 PWM (pulse width modulation) outputs for fan speed control (3 are MUX optional)

--- Total up to 3 sets of fan speed monitoring and controlling

• Issue SMI#, OVT#, GPO# signals to activate system protection

• Warning signal pop-up in application software

2.3 General

• ISA and I2CTM serial bus interface

• 5 VID input pins for CUP Vcore identification (for PentiumTM II)

• Initial power fault beep (for +3.3V, Vcore)

• Master reset input to W83782D

• Independent power plane of digital Vcc and analog Vcc (inputs to IC)

• 3 pins (IA0, IA1, IA2) to provide selectable address setting for application of multiple devices (up

to 8 devices) wired through I2CTM interface

• IntelTM LDCM (DMI driver 2.0) support

• AcerTM ADM (DMI driver 2.0) support

• Winbond hardware monitoring application software (Hardware Doctor

Windows 95/98 and Windows NT 4.0/5.0

• Input clock rate optional for 24, 48, 14.318 Mhz

• 5V Vcc operation

TM

) support, for both

2.4 Package

• 48-pin LQFP

- 2 -

Preliminary W83782D

3

#

3. KEY SPECIFICATIONS

• Voltage monitoring accuracy ±1% (Max)

• Monitoring Temperature Range and Accuracy

- 40°C to +120°C ± 3°C(Max)

• Supply Voltage 5V

• Operating Supply Current 5 mA typ.

• ADC Resolution 8 Bits

4. PIN CONFIGURATION

B E E P

-

/

5

5 V S B

V

G

V

I

N

P

I

D

O

N

3

A

#

25

24

VID2 PWMTOUT1

SDA

C

S

FAN1IO

FAN2IO FAN3IO/PWMOUT2 VID4 CASEOPEN MR

G N D D

13

CC

V

12

VREF VTIN3/PIITD3 VTIN2/PIITD2 VTIN1/PIITD1

VID0

OVT#

ARDMSEL

SMI#

SA2/IA2 SA1/IA1 SA0/IA0

CS#

V

+

C

I

3.3

O

V

R

N

I

E

R

N

A

0

36

37

48

1

+

-

12

5

V

12

V

B

V

I

A

I

N

T

N

W83782D

L

I

C

O

L

W

R

K

#

I N

D

D6D

4

5

7

V

D

2

I

1

0

D

/

1

P

W

M

O

U

T

4

3

Publication Release Date: April 1999

- 3 - Revision A1

Preliminary W83782D

Bi-directional ISA bus Data lines. This pin is activated if pin

ADRMSEL=0. /

Fan speed control PWM output. This pin is activated if pin

ADRMSEL=1.

Bi-directional ISA bus Data lines. This pin is activated if pin

ADRMSEL=0. /

Fan speed control PWM output. This pin is activated if pin

ADRMSEL=1.

5. PIN DESCRIPTION

I/O

- TTL level bi-directional pin with 12 mA source-sink capability

12t

I/O

- TTL level and schmitt trigger

12ts

OUT12 - Output pin with 12 mA source-sink capability AOUT - Output pin(Analog) OD12 - Open-drain output pin with 12 mA sink capability INt - TTL level input pin INts - TTL level input pin and schmitt trigger AIN - Input pin(Analog)

PIN NAME PIN NO. TYPE DESCRIPTION

IOR# 1 IN IOW# 2 IN CLKIN 3 IN

D7~D2 4-9 I/O

D1 /

10 I/O

ts ts

t

12t

An active low standard ISA bus I/O Read Control. An active low standard ISA bus I/O Write Control. System clock input. Can select 48MHz or 24MHz or 14.318MHz.

The default is 24MHz. Bi-directional ISA bus Data lines. D0 corresponds to the low

order bit, with D7 the high order bit. These pins are activated if pin ADRMSEL=0.

PWMOUT4 D0 /

11 I/O

PWMOUT3 VID1 12 IN

OUT

12t

12

t

Voltage Supply readouts from P6. This value is read in the VID/Fan Divisor Register.

VCC (+5V) 13 POWER

+5V VCC power. Bypass with the parallel combination of 10µF

(electrolytic or tantalum) and 0.1µF (ceramic) bypass capacitors. GNDD 14 DGROUND Internally connected to all digital circuitry. MR 15 IN CASEOPEN# 16 IN

ts

t

Master reset input.

CASE OPEN detection . An active low input from an external

device when case is opened. This signal can be latched if pin

VBAT is connect to battery, even W83782D is power off. VID4 17 IN

t

Voltage Supply readouts from P6. This value is read in the bit

<0> of Device ID Register.

- 4 -

Preliminary W83782D

Pin Discription, continued

PIN NAME PIN NO. TYPE DESCRIPTION

FAN3IO/ PWMOUT2 FAN2IO-

FAN1IO

SCL 21 IN SDA 22 OD PWMOUT1 23 OUT VID2 24 IN

VID3 25 IN

BEEP/GPO# 26 OD

GNDA 27 AGROUND Internally connected to all analog circuitry. The ground reference

-5VIN 28 AIN 0V to 4.096V FSR Analog Inputs. 5VSB 29 AIN 0V to 4.096V FSR Analog Inputs. VBAT 30 AIN 0V to 4.096V FSR Analog Inputs. (This pin should be connected

-12VIN 31 AIN 0V to 4.096V FSR Analog Inputs. +12VIN 32 AIN 0V to 4.096V FSR Analog Inputs. +5VIN 33 AIN This pin is Analog Vcc and connects internal monitor channel

+3.3VIN 34 AIN 0V to 4.096V FSR Analog Inputs. VINR0 35 AIN 0V to 4.096V FSR Analog Inputs. VCOREA 36 AIN 0V to 4.096V FSR Analog Inputs. VREF 37 AOUT Reference Voltage. VTIN3 / PIITD3

18 I/O

12t

0V to +5V amplitude fan tachometer input. /

Fan speed control PWM output.

19-20 I/O

12t

0V to +5V amplitude fan tachometer input /

Fan on-off control output. These multi-functional pins can be

programmable input or output.

ts

12

t

Serial Bus Clock.

Serial Bus bi-directional Data.

Fan speed control PWM output.

Voltage Supply readouts from P6. This value is read in the

VID/Fan Divisor Register.

t

Voltage Supply readouts from P6. This value is read in the

VID/Fan Divisor Register.

12

Beep (Default) / General purpose output

This multi-functional pin is programmable.

for all analog inputs.

to 3V BATTERY.)

IN3 with fixed scale.

38 AIN Thermistor 3 terminal input.(Default) /

PentiumTM II diode 3 input.

This multi-functional pin is programmable.

Publication Release Date: April 1999

- 5 - Revision A1

Preliminary W83782D

Pin Discription, continued

PIN NAME PIN NO. TYPE DESCRIPTION

VTIN2 / PIITD2

VTIN1 / PIITD1

VID0 41 IN

OVT# 42 OD ADRMSEL 43 IN

SMI# 44 OD

SA2-SA0

IA2,IA1,IA0 CS# 48 IN

39 AIN Thermistor 2 terminal input. (Default)/

PentiumTM II diode 2 input.

This multi-functional pin is programmable.

40 AIN Thermistor 1 terminal input. (Default)/

PentiumTM II diode 1 input.

This multi-functional pin is programmable.

t

Voltage Supply readouts from P6. This value is read in the

VID/Fan Divisor Register.

12

t

Over temperature Shutdown Output.

Pin 45--47 mode selection.

0 = The 3 lowest order bits of ISA Address Bus.(Default, internal

pull-down 47K ohm)

1 = 7 bit I2CTM address setting pin.(bit2 - bit0)

12

System Management Interrupt (open drain). This output is

enabled when Bit 1 in the Configuration Register is set to 1. The

default state is disabled.

45-47 IN

t

The three lowest order bits of the 16-bit ISA Address Bus. A0

corresponds to the lowest order bit.

(Default, when ARDMSEL =0 or left open )

IN

t

The hardware setting pin of 7 bit I2CTM serial address bit2, bit1

and bit0 at CR[48h]. (When ARDMSEL =1)

Chip Select input from an external decoder which decodes high

order address bits on the ISA Address Bus. This is an active low

input.

- 6 -

Preliminary W83782D

6. FUNCTIONAL DESCRIPTION

6.1 General Description

The W83782D provides 7 analog positive inputs, 3 fan speed monitors, at most 4 sets for fan PWM (Pulse Width Modulation) control, 3 thermal inputs from remote thermistors or 2N3904 transistors or Pentium the monitor value exceed the set limit value including voltage, temperature, or fan counter. When start the monitor function on the chip, the watch dog machine monitor every function and store the value to registers. If the monitor value exceeds the limit value, the interrupt status will be set to 1.

6.2 Access Interface

The W83782D provides two interface for microprocessor to read/write internal registers.

6.2.1 ISA interface

The first interface uses ISA Bus to access which the ports of low byte (bit2~bit0) are defined in the port 5h and 6h. The high byte (from ISA address bus bit15~bit3) of these ports is decoded by Chip Select (CS#), the general decoded address is set to port 295h and port 296h. These two ports are described as following:

Port 295h: W83782D Index register port. Port 296h: Data port. The register structure is showed as the Figure 1.

TM

II (Deschutes) thermal diode outputs, case open detection and beep function output when

Publication Release Date: April 1999

- 7 - Revision A1

ISA Data

Bus

ISA

Address

Bus

Port 5h

Index Register

Port 6h

Data Register

Preliminary W83782D

Configuration Register

40h

SMI# Status/Mask Registers

41h, 42h, 44h, 45h

VID<3:0>/Fan Divisor Register

Temperature 2, 3 Serial Bus Address

Select Bank for 50h~5Fh Reg.

Temperature 2 Control/Staus Registers

47h

Serial Bus Address

48h

Monitor Value Registers

20h~3Fh

and

60h~7Fh (auto-increment)

VID<4>/Device ID

49h

4Ah

Control Register

4Bh~4Dh

4Eh

Winbond Vendor ID

4Fh

BANK 0

R-T Table Value BEEP Control Register Winbond Test Register

50h~58h

BANK 1

50h~56h

Figure 1. ISA interface access diagram

- 8 -

BANK 2

Temperature 3 Control/Staus Registers

50h~56h

BANK 4

Additional Control/Staus Registers

50h~5Ch

BANK 5

Additional Limit Value &

Value RAM

50h~57h

Preliminary W83782D

6.2.2 I2C interface

The second interface uses I2C Serial Bus. In the W83782D has three serial bus address. That is, the first address defined at CR[48h] can read/write all registers excluding Bank 1 and Bank 2 temperature sensor 2/3 registers. The second address defined at CR[4Ah] bit2-0 only read/write temperature sensor 2 registers, and the third address defined at CR[4Ah] bit6-4 only can access (read/write) temperature sensor 3 registers.

The first serial bus address of W83782D has 3 hardware setting bits set by pin47-45 when pin 43 is set to high. The address is 00101[pin45][pin46][pin47]. If pin45=1, pin46=1, pin47=0, for example, the content of CR[48h] is 00101110. If CR[4Ah] bit 2-0 is XXX , the temperature sensor 2 serial address is 1001XXXG, in which G is the read/write bit. If CR[4Ah] bit 6-4 is YYY , the temperature sensor 3 serial address is 1001YYYG, in which G is the read/write bit.

6.2.3 The first serial bus access timing are shown as follow:

(a) Serial bus write to internal address register followed by the data byte

SCL

SDA

0

0 1 0 1 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0

Start By Master

Figure 2. Serial Bus Write to Internal Address Register followed by the Data Byte

Frame 1

Serial Bus Address Byte

SCL

(Continued)

SDA (Continued)

7 8 0 7 8

R/W

Ack

by

781D

0

D7 D6 D5 D4 D3 D2 D1 D0

Frame 2

Internal Index Register Byte

Frame 3

Data Byte

7 8

Ack

by

781D

Stop

by

Master

Ack

by

781D

Publication Release Date: April 1999

- 9 - Revision A1

(b) Serial bus write to internal address register only

Preliminary W83782D

0

7 8 0 7 8

SCL

SDA

0 1 0 1 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0

Start By Master

Frame 1

Serial Bus Address Byte

R/W

Ack 781D

Ack

Stop by

by

Frame 2

Internal Index Register Byte

781D

Master

0

Figure 3. Serial Bus Write to Internal Address Register Only

(c) Serial bus read from a register with the internal address register prefer to desired location

SCL

SDA

0

0 1 0 1 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0

Start By Master

Frame 1

Serial Bus Address Byte

Figure 4. Serial Bus Write to Internal Address Register Only

7 8 0 7 8

R/W

Ack 781D

by

Frame 2

Internal Index Register Byte

0

Ack

by

Master

Stop by Master

- 10 -

Preliminary W83782D

6.2.4 The serial bus timing of the temperature 2 and 3 is shown as follow:

(a) Typical 2-byte read from preset pointer location (Temp, TOS, T

SCL

SDA

0

0 1 0 1 1 0 1 D7 D1 D0

Start By

Master

Frame 1

Serial Bus Address Byte

7 8 0 7 8

R/W

Ack

by

782D

... ...

...

Frame 2

MSB Data Byte

Master

)

HYST

0 7

...

D7 D1 D0

Ack

by

Frame 3

LSB Data Byte

Figure 5. Typical 2-Byte Read From Preset Pointer Location

(b) Typical pointer set followed by immediate read for 2-byte register (Temp, TOS, T

Frame 2

Pointer Byte

Ack by

Master

4

D1 D0

0 7

D7 D1 D0

...

Frame 5

LSB Data Byte

Ack

by

782D

SCL

SDA

SCL

SDA

Start By

Master

0

1 0 0 1 A2 A1 A0 R/W

Start By

Master

0

1 0 0 1 A2 A1 A0 R/W

Serial Bus Address Byte

Frame 1

Serial Bus Address Byte

Frame 3

7 8 0

0 0 0 0 0 0

Ack

by

782D

7 8 0 7 8

... ...

D7 D1 D0

...

Ack

by

782D

0

Frame 4

MSB Data Byte

Master

HYST

No Ack

by

Master

Stop by

Ack

Master

by

)

Stop by

Master

Figure 6. Typical Pointer Set Followed by Immediate Read for 2-Byte Register

(c) Typical read 1-byte from configuration register with preset pointer

SCL

SDA

0

1 0 0 1 A2 A1 A0 R/W D1D5 D4 D3D6

Start By Master

Frame 1

Serial Bus Address Byte

Figure 7. Typical 1-Byte Read From Configuration With Preset Pointer

7 8 0

Ack

by

782D

D7 D2

Frame 2

Data Byte

Publication Release Date: April 1999

- 11 - Revision A1

8

7

D0

No Ack

Stop by

by

Master

Preliminary W83782D

(d) Typical pointer set followed by immediate read from configuration register

SCL

0

SDA

1 0 0 1 A2 A1 A0 R/W

Start By

Master

Frame 1

Serial Bus Address Byte

0

7 8 0

SCL (Cont..)

SDA (Cont..)

1 0 0 1 A2 A1 A0 R/W

Repea Start

By

Master

Frame 3

Serial Bus Address Byte

Figure 8. Typical Pointor Set Followed by Immediate Read from Temp 2/3 Configuration Register

(e) Temperature 2/3 configuration register Write

SCL

SDA

0

1 0 0 1 A2 A1 A0 R/W

Start By Master

Frame 1

Serial Bus Address Byte

7 8 0

0 0 0 0 00

Ack

by

782D

D7 D5 D4

Ack

by

782D

D6 D3

Frame 4

MSB Data Byte

Frame 2

Pointer Byte

4

0 0 0 0 0 0 0

Ack 782D

by

Frame 2

Pointer Byte

4

D2 D1 D0

D1 D0

7

7 8

8

No Ack

by

Master

Ack

by

782D

Ack

by

Stop by Master

...

SCL (Cont...)

0

SDA (Cont...)

0 0 D4 D3 D2 D10 D0

Frame 3

Configuration Data Byte

Figure 9. Configuration Register Write

- 12 -

7 8

Ack

by

782D

Stop

by

Master

Preliminary W83782D

(f) Temperature 2/3 TOS and T

SCL

SDA

SCL (Cont...)

SDA (Cont...)

0

1 0 0 1 A2 A1 A0 R/W

Start By Master

Frame 1

Serial Bus Address Byte

0

D6 D5 D4 D3 D2 D1D7 D0

Frame 3

MSB Data Byte

Figure 10. Configuration Register Write

HYST

write

7 8 0

Ack by 782D

7 8

Ack

by

781D

4

0

0 0 0 0

Frame 2

Pointer Byte

7 8

D1 D0

0 7 8

D6 D5 D4 D3 D2 D1D7 D0

Frame 4

LSB Data Byte

Ack by 782D

Ack 782D

Stop

by

Master

Publication Release Date: April 1999

- 13 - Revision A1

Preliminary W83782D

6.3 Analog Inputs

The maximum input voltage of the analog pin is 4.096V because the 8-bit ADC has a 16mv LSB. Really, the application of the PC monitoring would most often be connected to power suppliers. The CPU V-core voltage ,+3.3V and battery voltage can directly connected to these analog inputs. The 5VSB and +12V inputs should be reduced a factor with external resistors so as to obtain the input range. As Figure 11 shows.

V1

Positive Input

Negative Input

Typical Thermister Connection

V3

V4

+2.5VINA

Positive Inputs

R1

R2

R7

R

THM

10K, 25 C

+2.5VINB

+3.3VIN

VDD(+5V)

12VIN

V2

R5

10K, 1%

R

VBAT

R3

R4

N12VIN

N5VIN

R8

VREF Pin 37 VTIN3

VTIN2 VTIN1

**The Connections of VTIN1 and VTIN2

are same as VTIN3

Pin 38 Pin 39 Pin 40

Pin 36 Pin 35 Pin 34 Pin 33 Pin 30

Pin 32

5VSB Pin 29

Pin 31

Pin 28

R6

8-bit ADC

with

16mV LSB

Figure 11.

- 14 -

Preliminary W83782D

Ω

−

×−β

6.3.1 Monitor over 4.096V voltage:

The input voltage +12VIN can be expressed as following equation.

R

12

VIN V

= ×

1

The value of R1 and R2 can be selected to 28K Ohms and 10K Ohms, respectively, when the input voltage V1 is 12V. The node voltage of +12VIN can be subject to less than 4.096V for the maximun input range of the 8-bit ADC. Similarly, the node voltage of 5VSB (measure standby power VSB for ATX power supply) also can be evaluated by using two series resistors R3 and R4 which real value can be 5.1K ohms and 7.5K ohms so as to obtain the 5VSB is limited to less than 4.096V. The Pin 33 is connected to the power supply VCC with +5V. There are two functions in this pin with 5V. The first function is to supply internal analog power in the W83782D and the second function is that this voltage with 5V is connected to internal serial resistors to monitor the +5V voltage. The value of two serial resistors are 34K ohms and 50K ohms so that input voltage to ADC is 2.98V which is less than

4.096V of ADC maximum input voltage. The express equation can represent as follows.

V VCC

= ×

in

where VCC is set to 5V.

50

K K

50 34

Ω Ω

R R

K

+

2

+

1 2

≅

2 98

.

V

6.3.2 Monitor negative voltage:

The negative voltage should be connected two series resistors and a positive voltage VREF (is equal to 3.6V). In the Figure 11, the voltage V3 and V4 are two negative voltage which they are -12V and 5V respectively. The voltage V3 is connected to two serial resistors then is connected to another terminal VREF which is positive voltage. So as that the voltage node N12VIN can be obtain a posedge voltage if the scales of the two serial resirtors are carefully selected. It is recommanded from Winbond that the scale of two serial resistors are R5=232K ohms and R6=56K ohm. the The input voltage of node -12VIN can be calculated by following equation.

K

N VIN VREF V

If the V5 is equal to -12V then the voltage is equal to 0.567V and the converted hexdecimal data is set to 35h by the 8-bit ADC with 16mV-LSB.This monitored value should be converted to the real negative votage and the express equation is shown as follows.

= + ×

where VREF is equal 3.6V.

V

=

5

5 5

N VIN VREF

12

1

- 15 - Revision A1

232

K K

232 56

+

Ω Ω

β

V12

+( ) ( )

Publication Release Date: April 1999

Preliminary W83782D

−

×−γ

Where β is 232K/(232K+56K). If the N2VIN is 0.567 then the V5 is approximately equal to -12V. The another negative voltage input V6 (approximate -5V) also can be evaluated by the similar

method and the serial resistors can be selected with R7=120K ohms and R8=56K ohms by the Winbond recommended. The expression equation of V6 With -5V voltage is shown as follows.

N VIN VREF

V

Where the β is set to 120K/(120K+56K). If the monitored ADC value in the N5VIN channel is 0.8635, VREF=3.6V and the parameter β is 0.6818 then the negative voltage of V6 can be evalated to be -

5V.

6.3.3 Monitor temperature from thermistor:

The W83782D can connect three thermistors to measure three different envirment temperature. The specification of thermistor should be considered to (1) β value is 3435K, (2) resistor value is 10K ohms at 25°C. In the Figure 11, the themistor is connected by a serial resistor with 10K Ohms, then connect to VREF (Pin 37).

5

=

6

1

γ

6.3.4 Monitor temperature from Pentium IITM thermal diode or bipolar transistor 2N3904

The W83782D can alternate the thermistor to Pentium IITM (Deschutes) thermal diode interface or transistor 2N3904 and the circuit connection is shown as Figure 12. The pin of Pentium IITM D- is connected to power supply ground (GND) and the pin D+ is connected to pin PIITDx in the W83782D. The resistor R=30K ohms should be connected to VREF to supply the diode bias current and the bypass capacitor C=3300pF should be added to filter the high frequency noise. The transistor 2N3904 should be connected to a form with a diode, that is, the Base (B) and Collector (C) in the 2N3904 should be tied togeter to act as a thermal diode.

- 16 -

Preliminary W83782D

VREF

Bipolar Transistor

Temperature Sensor

C

B

2N3904

E

OR

Pentium II

CPU D+

Therminal

Diode

D-

Figure 12.

R=30K, 1%

PIITDx

C=3300pF

W83782D

R=30K, 1%

PIITDx

C=3300pF

6.4 FAN Speed Count and FAN Speed Control

6.4.1 Fan speed count

Inputs are provides for signals from fans equipped with tachometer outputs. The level of these signals should be set to TTL level, and maximum input voltage can not be over +5.5V. If the input signals from the tachometer outputs are over the VCC, the external trimming circuit should be added to reduce the voltage to obtain the input specification. The normal circuit and trimming circuits are shown as Figure 13.

Determine the fan counter according to:

Count

.

=

RPM Divisor

×

6

×

135 10

In other words, the fan speed counter has been read from register CR28 or CR29 or CR2A, the fan speed can be evaluated by the following equation.

RPM

=

.

Count Divisor

×

6

×

1 35 10

Publication Release Date: April 1999

- 17 - Revision A1

Preliminary W83782D

The default divisor is 2 and defined at CR47.bit7~4, CR4B.bit7~6, and Bank0 CR5D.bit5~7 which are three bits for divisor. That provides very low speed fan counter such as power supply fan. The followed table is an example for the relation of divisor, PRM, and count.

Divisor Nominal

PRM

1 8800 6.82 ms 153 6160 9.74 ms

2 (default)

4 2200 27.27 ms 153 1540 38.96 ms

8 1100 54.54 ms 153 770 77.92 ms 16 550 109.08 ms 153 385 155.84 ms 32 275 218.16 ms 153 192 311.68 ms 64 137 436.32 ms 153 96 623.36 ms

128 68 872.64 ms 153 48 1246.72 ms

4400 13.64 ms 153 3080 19.48 ms

Time per

Revolution

Counts 70% RPM Time for 70%

Table 1.

- 18 -

Preliminary W83782D

Output and Register Attenuator

and Zener Clamp

+12V

FAN Out

GND

+5V

Pull-up resister

4.7K Ohms

Fan Input

FAN

Connector

Figure 13-1. Fan with Tach Pull-Up to +5V

+12V

Pull-up resister

> 1K

+12V

FAN Out

FAN

Connector

GND

Fan Input

3.9V Zener

Pin 18/19/20

W83782D

Pin 18/19/20

W83782D

+12V

Pull-up resister

4.7K Ohms

+12V

FAN Out

GND

FAN

14K~39K

Fan Input

10K

Connector

Figure 13-2. Fan with Tach Pull-Up to +12V, or Totem-Pole

+12V

Pull-up resister < 1K or totem-pole output

FAN Out

FAN

Connector

+12V

GND

> 1K

3.9V Zener

Fan Input

Pin 18/19/20

W83782D

Pin 18/19/20

W83782D

Figure 13-3. Fan with Tach Pull-Up to +12V

Figure 13-4. Fan with Tach Pull-Up to +12V, or Totem-Pole Putput and Zener Clamp

6.4.2 Fan speed control

The W83782D provides four sets for fan PWM speed control. The duty cycle of PWM can be programmed by a 8-bit registers which are defined in the Bank0 CR5A, CR5B, CR5E, and CR5F. The default duty cycle is set to 100%, that is, the default 8-bit registers is set to FFh. The expression of duty can be represented as follows.

Duty cycle

− = ×(%) 100%

Programmed 8 - bit Register Value

255

The PWM clock frequency also can be program and defined in the Bank0.CR5C and Bank4.CR5C. The application circuit is shown as follows.

Publication Release Date: April 1999

- 19 - Revision A1

Preliminary W83782D

+12V

R1

R2

D

G

PWM Clock Input

NMOS

S

Figure 14.

6.5 Temperature Measurement Machine

The temperature data format is 8-bit two’s-complement for sensor 1 and 9-bit two’s-complement for sensor 2/3. The 8-bit temperature data can be obtained by reading the CR[27h]. The 9-bit temperature data can be obtained by reading the 8 MSBs from the Bank1/2 CR[50h] and the LSB from the Bank1/2 CR[51h] bit 7. The format of the temperature data is show in Table 1.

PNP Transistor

+

C

-

FAN

Temperature 8-Bit Digital Output 9-Bit Digital Output

8-Bit Binary 8-Bit Hex 9-Bit Binary 9-Bit Hex

+125øC 0111,1101 7Dh 0,1111,1010 0FAh

+25øC 0001,1001 19h 0,0011,0010 032h

+1øC 0000,0001 01h 0,0000,0010 002h

+0.5øC - - 0,0000,0001 001h

+0øC 0000,0000 00h 0,0000,0000 000h

-0.5øC - - 1,1111,1111 1FFh

-1øC 1111,1111 FFh 1,1111,1110 1FFh

-25øC 1110,0111 E7h 1,1100,1110 1CEh

-55øC 1100,1001 C9h 1,1001,0010 192h

Table 2.

- 20 -

Preliminary W83782D

6.5.1 The W83782D temperature sensor 1 SMI# interrupt has two modes: (1) Comparator Interrupt Mode

Setting the T the Comparator Interrupt Mode. Temperature exceeds TO (Over Temperature) Limit causes an interrupt and this interrupt will be reset by reading all the Interrupt Status Register. Once an interrupt event has occurred by exceeding TO, then reset, if the temperature remains above the TO , the interrupt will occur again when the next conversion has completed. If an interrupt event has occurred by exceeding TO and not reset, the interrupts will not occur again. The interrupts will continue to occur in this manner until the temperature goes below TO. (Figure 16-1 )

(2) Two-Times Interrupt Mode

Setting the T Mode. Temperature exceeding TO causes an interrupt and then temperature going below T will also cause an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. Once an interrupt event has occurred by exceeding TO , then reset, if the temperature remains above the T

(Temperature Hysteresis) limit to 127øC will set temperature sensor 1 SMI# to

HYST

lower than TO will set temperature sensor 1 SMI# to the Two-Times Interrupt

HYST

, the interrupt will not occur. (Figure 15-2 )

HYST

T

HYST

127'C

T

OI

SMI# SMI#

Figure 15-1. Comparator Interrupt Mode

* *

* * * **

*Interrupt Reset when Interrupt Status Registers are read

T

HYST

OI

Figure 15-2. Two-Times Interrupt Mode

Publication Release Date: April 1999

- 21 - Revision A1

Preliminary W83782D

6.5.2 The W83782D temperature sensor 2 and sensor 3 SMI# interrupt has two modes and it is programmed at CR[4Ch] bit 6.

(1) Comparator Interrupt Mode

Temperature exceeding TO causes an interrupt and this interrupt will be reset by reading all the Interrupt Status Register. Once an interrupt event has occurred by exceeding TO, then reset, if the temperature remains above the T has completed. If an interrupt event has occurred by exceeding TO and not reset, the interrupts will not occur again. The interrupts will continue to occur in this manner until the temperature goes below T

. ( Figure 16-1 )

HYST

(2) Two-Times Interrupt Mode

Temperature exceeding TO causes an interrupt and then temperature going below T cause an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. Once an interrupt event has occurred by exceeding TO , then reset, if the temperature remains above the T

, the interrupt will not occur. (Figure 16-2 )

HYST

, the interrupt will occur again when the next conversion

HYST

will also

T

OI

T

HYST

SMI# SMI#

Figure 16-1. Comparator Interrupt Mode

* * *

* * * **

*Interrupt Reset when Interrupt Status Registers are read

T

HYST

OI

Figure 16-2. Two-Times Interrupt Mode

- 22 -

Preliminary W83782D

6.5.3 The W83782D temperature sensor 2 and 3 Over-Temperature (OVT#) has two modes,

and they are programmed at Bank1 and Bank2 CR[52h] bit1 . These two bits needs to be programmed the same value.

(1) Comparator Mode :

Temperature exceeding TO causes the OVT# output activated until the temperature is less than T

. ( Figure 17)

HYST

(2) Interrupt Mode:

Temperature exceeding TO causes the OVT# output activated indefinitely until reset by reading temperature sensor 2 or sensor 3 registers. Temperature exceeding TO , then OVT# reset, and then temperature going below T reading temperature sensor2 or sensor 3 registers. Once the OVT# is activated by exceeding T , then reset, if the temperature remains above T Figure 17)

will also cause the OVT# activated indefinitely until reset by

HYST

, the OVT# will not be activated again.(

HYST

O

T

(Comparator Mode; default)

(Interrupt Mode)

OVT#

To

HYST

* * *

*Interrupt Reset when Temperature 2/3 is read

Figure 17. Over-Temperature Response Diagram

*

Publication Release Date: April 1999

- 23 - Revision A1

Priliminary W83782D

7. REGISTERS AND RAM

7.1 Address Register (Port x5h)

Data Port: Port x5h Power on Default Value 00h Attribute: Bit 6:0 Read/write , Bit 7: Read Only Size: 8 bits

7 6 5 4 3 2 1 0

Data

Bit7: Read Only

The logical 1 indicates the device is busy because of a Serial Bus transaction or another ISA bus transaction. With checking this bit, multiple ISA drivers can use W83782D without interfering with each other or a Serial Bus driver.

It is the user's responsibility not to have a Serial Bus and ISA bus operations at the same time. This bit is:

Set: with a write to Port x5h or when a Serial Bus transaction is in progress. Reset: with a write or read from Port x6h if it is set by a write to Port x5h, or when the Serial Bus

transaction is finished.

Bit 6-0: Read/Write

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Busy Address Pointer (Power On default 00h)

(Power On default 0) A6 A5 A4 A3 A2 A1 A0

- 24 -

Address Pointer Index (A6-A0)

Priliminary W83782D

Registers and RAM A6-A0 in Hex Power On Value of Registers:

<k7:0>in Binary

Configuration Register 40h 00001000 Interrupt Status Register 1 41h 00000000 Auto-increment to the address of Interrupt

Status Register 2 after a read or write to Port

x6h. Interrupt Status Register 2 42h 00000000 SMI#Ý Mask Register 1 43h 00000000 Auto-increment to the address of SMIÝ Mask

Register 2 after a read or write to Port x6h. SMIÝ Mask Register 2 44h 00000000 NMI Mask Register 1 45h 00000000 Auto-increment to the address of NMI Mask

Register 2 after a read or write to Port x6h NMI Mask Register 2 46h 01000000 VID/Fan Divisor Register 47h <7:4> = 0101;

<3:0> = VID3-ID0 Serial Bus Address Register 48h <6:0> = 0101101; <7> = 0 POST RAM 00-1Fh Auto-increment to the next location after a

read or write to Port x6h and stop at 1Fh. Value RAM 20-3Fh Value RAM 60-7Fh Auto-increment to the next location after a

read or write to Port x6h and stop at 7Fh.

Notes

7.2 Data Register (Port x6h)

Data Port: Port x6h Power on Default Value 00h Attribute: Read/write Size: 8 bits

7 6 5 4 3 2 1 0

Bit 7-0: Data to be read from or to be written to RAM and Register.

- 25 - Revision A1

Data

Publication Release Date: April 1999

Priliminary W83782D

7.3 Configuration Register  Index 40h

Register Location: 40h Power on Default Value 00000001 binary Attribute: Read/write Size: 8 bits

7 6 5 4 3 2 1 0

START SMI#Enable RESERVED INT_Clear RESERVED RESERVED BEEP/GPO# INITIALIZATION

Bit 7: A one restores power on default value to all registers except the Serial Bus Address register.

This bit clears itself since the power on default is zero. Bit 6: The logical 1 in this bit drives a zero on BEEP/GPO# pin. Bit 5: Reserved Bit 4: Reserved Bit 3: A one disables the SMI# output without affecting the contents of Interrupt Status Registers.

The device will stop monitoring. It will resume upon clearing of this bit. Bit 2: Reserved Bit 1: A one enables the SMI# Interrupt output.

Bit 0: A one enables startup of monitoring operations, a zero puts the part in standby mode.

Note: The outputs of Interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred unlike "INT_Clear'' bit.

7.4 Interrupt Status Register 1 Index 41h

Register Location: 41h Power on Default Value 00h Attribute: Read Only Size: 8 bits

- 26 -

Priliminary W83782D

7 6 5 4 3 2 1 0

VCOREA VINRO +3.3VIN +5VIN TEMP1 TEMP2 FAN1 FAN2

Bit 7: A one indicates the fan count limit of FAN2 has been exceeded. Bit 6: A one indicates the fan count limit of FAN1 has been exceeded. Bit 5: A one indicates a High limit of VTIN2 has been exceeded from temperature sensor 2. Bit 4: A one indicates a High limit of VTIN1 has been exceeded from temperature sensor 1. Bit 3: A one indicates a High or Low limit of +5VIN has been exceeded. Bit 2: A one indicates a High or Low limit of +3.3VIN has been exceeded. Bit 1: A one indicates a High or Low limit of VINR0 has been exceeded. Bit 0: A one indicates a High or Low limit of VCOREA has been exceeded.

7.5 Interrupt Status Register 2  Index 42h

Register Location: 42h Power on Default Value 00h Attribute: Read Only Size: 8 bits

7 6 5 4 3 2 1 0

+12VIN

-12VIN

-5VIN FAN3 Chassis Intrusion Temp3 Reserved Reserved

Bit 7-6:Reserved.This bit should be set to 0. Bit 5: A one indicates a High limit of VTIN3 has been exceeded from temperature sensor 3.

Publication Release Date: April 1999

- 27 - Revision A1

Priliminary W83782D

SMI

Bit 4: A one indicates Chassis Intrusion has gone high. Bit 3: A one indicates the fan count limit of FAN3 has been exceeded. Bit 2: A one indicates a High or Low limit of -5VIN has been exceeded. Bit1: A one indicates a High or Low limit of -12VIN has been exceeded. Bit0: A one indicates a High or Low limit of +12VIN has been exceeded.

7.6 SMI# Mask Register 1  Index 43h

Register Location: 43h Power on Default Value 00h Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

Bit 7-0: A one disables the corresponding interrupt status bit for

7.7 SMI# Mask Register 2  Index 44h

Register Location: 44h Power on Default Value 00h Attribute: Read/Write Size: 8 bits

VCOREA VINRO +3.3VIN +5VIN TEMP1 TEMP2 FAN1 FAN2

interrupt.

- 28 -

7 6 5 4 3 2 1 0

SMI

Bit 7-6: Reserved. This bit should be set to 0.

Priliminary W83782D

+12VIN

-12VIN

-5VIN FAN3 Chassis Intrusion TEMP3 Reserved Reserved

Bit 5-0: A one disables the corresponding interrupt status bit for

interrupt.

7.8 Reserved Register  Index 45h

7.9 Chassis Clear Register -- Index 46h

Register Location: 46h Power on Default Value <7:0> = 00000000 binary Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Chassis Clear

Bit 7: Set 1 , clear Chassis Intrusion event. This bit self clears after clearing Chassis Intrusion event. Bit 6-0:Reserved. This bit should be set to 0.

7.10 VID/Fan Divisor Register  Index 47h

Register Location: 47h Power on Default Value <7:4> is 0101, <3:0> is mapped to VID<3:0> Attribute: Read/Write Size: 8 bits

Publication Release Date: April 1999

- 29 - Revision A1

7 6 5 4 3 2 1 0

Bit 7-6: FAN2 Speed Control. Bit 5-4: FAN1 Speed Control. Bit 3-0: The VID <3:0> inputs

Note : Please refer to Bank0 CR[5Dh] , Fan divisor table.

7.11 Serial Bus Address Register  Index 48h

Priliminary W83782D

VID0 VID1 VID2 VID3 FAN1DIV_B0 FAN1DIV_B1 FAN2DIV_B0 FAN2DIV_B1

Register Location: 48h Power on Default Value Serial Bus address <6:0> = 0101101 and <7> = 0 binary Size: 8 bits

7 6 5 4 3 2 1 0

Serial Bus Address

Reserved

Bit 7: Read Only - Reserved. Bit 6-0: Read/Write - Serial Bus address <6:0>.

- 30 -

Priliminary W83782D

7.12 Value RAM  Index 20h- 3Fh or 60h - 7Fh (auto-increment)

Address A6-A0 Address A6-A0 with

Auto-Increment

20h 60h VCOREA reading 21h 61h VINR0 reading 22h 62h +3.3VIN reading 23h 63h +5VIN reading 24h 64h +12VIN reading 25h 65h -12VIN reading 26h 66h -5VIN reading 27h 67h Temperature reading 28h 68h FAN1 reading

Note: This location stores the number of counts of the internal clock per revolution.

29h 69h FAN2 reading

Note: This location stores the number of counts of the internal clock per revolution.

2Ah 6Ah FAN3 reading

Note: This location stores the number of counts of the internal clock per revolution.

Description

2Bh 6Bh VCOREA High Limit, default value is defined by

Vcore Voltage +0.2v.

2Ch 6Ch VCOREA Low Limit, default value is defined by Vcore

Voltage -0.2v. 2Dh 6Dh VINR0 High Limit. 2Eh 6Eh VINR0 Low Limit. 2Fh 6Fh +3.3VIN High Limit 30h 70h +3.3VIN Low Limit 31h 71h +5VIN High Limit 32h 72h +5VIN Low Limit

Publication Release Date: April 1999

- 31 - Revision A1

7.12 Value RAM  Index 20h- 3Fh or 60h - 7Fh (auto-increment), continued

Priliminary W83782D

Address A6-A0 Address A6-A0 with

Auto-Increment

33h 73h +12VIN High Limit 34h 74h +12VIN Low Limit 35h 75h -12VIN High Limit 36h 76h -12VIN Low Limit 37h 77h -5VIN High Limit 38h 78h -5VIN Low Limit 39h 79h Temperature sensor 1 (VTIN1) High Limit 3Ah 7Ah Temperature sensor 1 (VTIN1) Hysteresis Limit 3Bh 7Bh FAN1 Fan Count Limit

Note: It is the number of counts of the internal clock

for the Low Limit of the fan speed. 3Ch 7Ch FAN2 Fan Count Limit

Note: It is the number of counts of the internal clock

for the Low Limit of the fan speed. 3Dh 7Dh FAN3 Fan Count Limit

Note: It is the number of counts of the internal clock

for the Low Limit of the fan speed.

Description

3E- 3Fh 7E- 7Fh Reserved

Setting all ones to the high limits for voltages and fans (0111 1111 binary for temperature) means interrupts will never be generated except the case when voltages go below the low limits.

- 32 -

7.13 Voltage ID (VID4) & Device ID -- Index 49h

Register Location: 49h Power on Default Value <7:1> is 000,0001b

<0> is mapped to VID <4>

Size: 8 bits

7 6 5 4 3 2 1 0

Priliminary W83782D

VID4

DID<6:0>

Bit 7-1: Read Only - Device ID<6:0> Bit 0 : Read/Write - The VID4 inputs.

7.14 Temperature 2 and Temperature 3 Serial Bus Address Register--Index 4Ah

Register Location: 4Ah Power on Default Value <7:0> = 0000,0001 binary. Reset by MR Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

I2CADDR2 I2CADDR2 I2CADDR2 DIS_T2 I2CADDR3 I2CADDR3 I2CADDR3 DIS_T3

Bit 7: Set to 1, disable temperature sensor 3 and can not access any data from Temperature Sensor 3. Bit 6-4: Temperature 3 Serial Bus Address. The serial bus address is 1001xxx. Where xxx are defined in

these bits.

Publication Release Date: April 1999

- 33 - Revision A1

Priliminary W83782D

Bit 3: Set to 1, disable temperature Sensor 2 and can not access any data from Temperature Sensor 2. Bit 2-0: Temperature 2 Serial Bus Address. The serial bus address is 1001xxx. Where xxx are defined in

these bits.

7.15 Pin Control Register -- Index4Bh

Register Location: 4Bh Power on Default Value <7:0> 44h. Reset by MR. Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

Reserved Reserved CLKINSEL CLKINSEL ADCOVSEL ADCOVSEL FAN3DIV_B0 FAN3DIV_B1

Bit 7-6:Fan3 speed divisor.

Please refer to Bank0 CR[5Dh] , Fan divisor table.

Bit 5-4: Select A/D Converter Clock Input. <5:4> = 00 - default. ADC clock select 22.5 Khz. <5:4> = 01- ADC clock select 5.6 Khz. (22.5K/4) <5:4> = 10 - ADC clock select 1.4Khz. (22.5K/16) <5:4> = 11 - ADC clock select 0.35 Khz. (22.5K/64) Bit 3-2: Clock Input Select.

<3:2> = 00 - Pin 3 (CLKIN) select 14.318M Hz clock. <3:2> = 01 - Default. Pin 3 (CLKIN) select 24M Hz clock. <3:2> = 10 - Pin 3 (CLKIN) select 48M Hz clock . <3:2> = 11 - Reserved. Pin3 no clock input.

Bit 1-0: Reserved. User defined.

- 34 -

Priliminary W83782D

7.16 IRQ#/OVT# Property Select -- Index 4Ch

Register Location: 4Ch Power on Default Value <7:0> --0000,0001. Reset by MR. Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

Reserved Reserved OVTPOL DIS_OVT1 DIS_OVT2 Reserved T23_INTMode Reserved

Bit 7: Reserved. User Defined. Bit6: Set to 1, the SMI# output type of Temperature 2 and 3 is set to Comparator Interrupt mode. Set

to 0, the SMI# output type is set to Two-Times Interrupt mode. (default 0) Bit5: Reserved. User Defined. Bit 4: Disable temperature sensor 3 over-temperature (OVT) output if set to 1. Default 0, enable

OVT2 output through pin OVT#.

Bit 3: Disable temperature sensor 2 over-temperature (OVT) output if set to 1. Default 0, enable

OVT1 output through pin OVT#. Bit 2: Over-temperature polarity. Write 1, OVT# active high. Write 0, OVT# active low. Default 0. Bit 1: Reserved. User Defined. Bit 0: Reserved. User Defined.

Publication Release Date: April 1999

- 35 - Revision A1

Priliminary W83782D

7.17 FAN IN/OUT and BEEP/GPO# Control Register -- Index 4Dh

Register Location: 4Dh Power on Default Value <7:0> 0001,0101. Reset by MR. Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

FANINC1 FANOPV1 FANINC2 FANOPV2 FANINC3 FANOPV3 GPOSEL DIS_ABN

Bit 7: Disable power-on abnormal the monitor voltage including V-Core A and +3.3V. If these voltage

exceed the limit value, the pin (Open Drain) of BEEP will drives 300Hz and 600Hz frequency

signal. Write 1, the frequency will be disable. Default 0. After power on, the system should set

1 to this bit to 1 in order to disable BEEP.

Bit 6: BEEP/GPO# Pin Function Select. Write 1 Select GPO# function. Set 0, select BEEP function.

This bit default 0.

Bit 5: FAN 3 output value if FANINC3 sets to 0. Write 1, then pin 18 always generate logic high

signal. Write 0, pin 18 always generates logic low signal. This bit default 0.

Bit 4: FAN 3 Input Control. Set to 1, pin 18 acts as FAN clock input, which is default value. Set to 0,

this pin 18 acts as FAN control signal and the output value of FAN control is set by this register

bit 5. This output pin can connect to power PMOS gate to control FAN ON/OFF.

Bit 3: FAN 2 output value if FANINC2 sets to 0. Write 1, then pin 19 always generate logic high

signal. Write 0, pin 19 always generates logic low signal. This bit default 0.

Bit 2: FAN 2 Input Control. Set to 1, pin 19 acts as FAN clock input, which is default value. Set to 0,

this pin 19 acts as FAN control signal and the output value of FAN control is set by this register

bit 3. This output pin can connect to power NMOS gate to control FAN ON/OFF.

Bit 1: FAN 1 output value if FANINC1 sets to 0. Write 1, then pin 20 always generate logic high

signal. Write 0, pin 20 always generates logic low signal. This bit default 0.

Bit 0: FAN 1 Input Control. Set to 1, pin 20 acts as FAN clock input, which is default value. Set to 0,

this pin 20 acts as FAN control signal and the output value of FAN control is set by this register

t 1. This output pin can connect to power PMOS gate to control FAN ON/OFF.

- 36 -

Priliminary W83782D

7.18 Register 50h ~ 5Fh Bank Select -- Index 4Eh

Register Location: 4Eh Power on Default Value <6:3> = Reserved, <7> = 1, <2:0> = 0. Reset by MR Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

BANKSEL0 BANKSEL1 BANKSEL2 Reserved Reserved Reserved Reserved HBACS

Bit 7: HBACS- High byte access. Set to 1, access Register 4Fh high byte register.

Set to 0, access Register 4Fh low byte register. Default 1. Bit 6-3: Reserved. This bit should be set to 0. Bit 2-0: Index ports 0x50~0x5F Bank select.

7.19 Winbond Vendor ID -- Index 4Fh

Register Location: 4Fh Power on Default Value <15:0> = 5CA3h Attribute: Read Only Size: 16 bits

15 8 7 0

Bit 15-8: Vendor ID High Byte if CR4E.bit7=1.Default 5Ch.

VIDH

VIDL

Bit 7-0: Vendor ID Low Byte if CR4E.bit7=0. Default A3h.

- 37 - Revision A1

Publication Release Date: April 1999

Priliminary W83782D

7.20 Winbond Test Register -- Index 50h - 55h (Bank 0)

7.21 BEEP Control Register 1-- Index 56h (Bank 0)

Register Location: 56h Power on Default Value <7:0> 0000,0000. Reset by MR. Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

EN_VCA_BP EN_Vr0_BP EN_V33_BP EN_V5_BP EN_T1_BP EN_T2_BP EN_FAN1_BP EN_FAN2_BP

Bit 7: Enable BEEP Output from FAN 2 if the monitor value exceed the limit value. Write 1, enable

BEEP output, which is default value. Bit 6: Enable BEEP Output from FAN 1 if the monitor value exceed the limit value. Write 1, enable

BEEP output, which is default value. Bit 5: Enable BEEP Output from Temperature Sensor 2 if the monitor value exceed the limit value.

Write 1, enable BEEP output. Default 0 Bit 4: Enable BEEP output for Temperature Sensor 1 if the monitor value exceed the limit value.

Write 1, enable BEEP output. Default 0 Bit 3: Enable BEEP output from VDD (+5V), Write 1, enable BEEP output if the monitor value exceed

the limits value. Default 0, that is disable BEEP output. Bit 2: Enable BEEP output from +3.3V. Write 1, enable BEEP output, which is default value. Bit 1: Enable BEEP output from VINR0. Write 1, enable BEEP output, which is default value. Bit 0: Enable BEEP Output from VCOREA if the monitor value exceed the limits value. Write 1,

enable BEEP output, which is default value

- 38 -

Priliminary W83782D

7.22 BEEP Control Register 2-- Index 57h (Bank 0)

Register Location: 57h Power on Default Value <7:0> 1000-0000. Reset by MR. Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

EN_V12_BP EN_NV12_BP EN_NV5_BP EN_FAN3_BP EN_CASO_BP EN_T3_BP Reserved EN_GBP

Bit 7: Enable Global BEEP. Write 1, enable global BEEP output. Default 1. Write 0, disable all BEEP

output. Bit 6: Reserved. This bit should be set to 0. Bit 5: Enable BEEP Output from Temperature Sensor 3 if the monitor value exceed the limit value.

Write 1, enable BEEP output. Default 0 Bit 4: Enable BEEP output for case open if the monitor value exceed the limit value. Write 1, enable

BEEP output. Default 0. Bit 3: Enable BEEP Output from FAN 3 if the monitor value exceed the limit value. Write 1, enable

BEEP output. Default 0. Bit 2: Enable BEEP output from -5V, Write 1, enable BEEP output if the monitor value exceed the

limits value. Default 0, that is disable BEEP output. Bit 1: Enable BEEP output from -12V, Write 1, enable BEEP output if the monitor value exceed the

limits value. Default 0, that is disable BEEP output. Bit 0: Enable BEEP output from +12V, Write 1, enable BEEP output if the monitor value exceed the

limits value. Default 0, that is disable BEEP output.

7.23 Chip ID -- Index 58h (Bank 0)

Register Location: 58h Power on Default Value <7:0> 0011-0000. Reset by MR. Attribute: Read Only Size: 8 bits

Publication Release Date: April 1999

- 39 - Revision A1

Priliminary W83782D

7 6 5 4 3 2 1 0

CHIPID

Bit 7: Winbond Chip ID number. Read this register will return 30h.

7.24 Diode Selection Register -- Index 59h (Bank 0)

Register Location: 59h Power on Default Value <7>=0 and <6:4> = 111 and <3:0> = 0000 Attribute: Read/Write

Size: 8 bits

7 6 5 4 3 2 1 0

Reserved Reserved Reserved Reserved SELPIIV1 SELPIIV2 SELPIIV3 Reserved

Bit 7: Reserved Bit 6: Temperature sensor diode 3. Set to 1, select Pentium II compatible Diode. Set to 0 to select 2N3904

Bipolar mode.

Bit 5: Temperature sensor diode 2. Set to 1, select Pentium II compatible Diode. Set to 0 to select 2N3904

Bipolar mode.

Bit 4: Temperature sensor diode 1. Set to 1, select Pentium II compatible Diode. Set to 0 to select 2N3904

Bipolar mode.

Bit 3-0: Reserved

- 40 -

7.25 PWMOUT2 Control -- Index 5Ah (Bank 0)

Register Location: 5Ah Power on default value: <7:0> 1111-1111. Reset by MR. Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

Bit 7: PWMOUT2 duty cycle control Write FF, Duty cycle is 100%, Write 00, Duty cycle is 0%.

Priliminary W83782D

PWM2_DUTY

- 40-A -

7.26 PWMOUT1 Control -- Index 5Bh (Bank 0)

Register Location: 5Bh Power on default value: <7:0> 1111-1111. Reset by MR. Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

Priliminary W83782D

PWM1_DUTY

Bit 7: PWMOUT1 duty cycle control Write FF, Duty cycle is 100%, Write 00, Duty cycle is 0%.

7.27 PWMOUT1/2 Clock Select -- Index 5Ch (Bank 0)

Register Location: 5Ch Power on Default Value <7:0> 0001-0001. Reset by MR. Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

PWM2CLKSEL PWM2CLKSEL PWM2CLKSEL EN_FANPWM2 PWM1CLKSEL PWM1CLKSEL PWM1CLKSEL Reserved

Bit 7: Reserved Bit 6-4: PWMOUT1 clock selection.

The clock defined frequency is same as PWMOUT2 clock selection.

Publication Release Date: April 1999

-41 - Revision A1

Priliminary W83782D

Bit 3: Set to 1. Enable PWMOUT2 PWM Control Bit 2-0: PWMOUT2 clock Selection. <2:0> = 000: 46.87K Hz <2:0> = 001: 23.43K Hz (Default) <2:0> = 010: 11.72K Hz <2:0> = 011: 5.85K Hz <2:0> = 100: 2.93K Hz

7.28 VBAT Monitor Control Register -- Index 5Dh (Bank 0)

Register Location: 5Dh Power on Default Value <7:0> 0000-0000. Reset by MR. Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

EN_VBAT_MNT DIODES1 DIODES2 DIODES3 RESERVE FANDIV1_B2 FANDIV2_B2 FANDIV3_B2

Bit 7: Fan3 divisor Bit 2. Bit 6: Fan2 divisor Bit 2. Bit 5: Fan1 divisor Bit 2. Bit 4: Reserve. Bit 3: Temperature sensor 3 select into thermal diode such as Pentium II CPU supported. Set to 1,

select bipolar sensor. Set to 0, select thermistor sensor. Bit 2: Sensor 2 type selection. Defined as DIODES3 described in the bit 3. Bit 1: Sensor 1 type selection. Defined as DIODES2 described in the bit 3. Bit 0: Set to 1, enable battery voltage monitor. Set to 0, disable battery voltage monitor. If enable this

bit, the monitor value is value after one monitor cycle. Note that the monitor cycle time is at

least 300ms for W83782D.

- 42 -

Fan divisor table :

Priliminary W83782D

Bit 2 Bit 1 Bit 0 Fan

Divisor

0 0 0 1 1 0 0 16 0 0 1 2 1 0 1 32 0 1 0 4 1 1 0 64 0 1 1 8 1 1 1 128

Bit 2 Bit 1 Bit 0 Fan Divisor

7.29 PWMOUT3 Control -- Index 5Eh (Bank 0)

Register Location: 5Eh Power on Default Value <7:0> 1111-1111. Reset by MR. Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

PWM3_DUTY

Bit 7: PWMOUT3 duty cycle control Write FF, Duty cycle is 100%, Write 00, Duty cycle is 0%.

7.30 PWMOUT4 Control -- Index 5Fh (Bank 0)

Register Location: 5Fh Power on Default Value <7:0> 1111-1111. Reset by MR. Attribute: Read Only Size: 8 bits

-43 - Revision A1

Publication Release Date: April 1999

Priliminary W83782D

7 6 5 4 3 2 1 0

PWM4_DUTY

Bit 7: PWMOUT4 duty cycle control Write FF, Duty cycle is 100%, Write 00, Duty cycle is 0%.

7.31 Temperature Sensor 2 Temperature (High Byte) Register - Index 50h (Bank 1)

Register Location: 50h Attribute: Read Only Size: 8 bits

7 6 5 4 3 2 1 0

TEMP2<8:1>

Bit 7: Temperature <8:1> of sensor 2, which is high byte.

7.32 Temperature Sensor 2 Temperature (Low Byte) Register - Index 51h (Bank 1)

Register Location: 51h Attribute: Read Only Size: 8 bits

- 44 -

7 6 5 4 3 2 1 0

Bit 7: Temperature <0> of sensor2, which is low byte. Bit 6-0: Reserved. This bit should be set to 0.

Priliminary W83782D

Reserved

TEMP2<0>

7.33 Temperature Sensor 2 Configuration Register - index 52h (Bank 1)

Register Location: 52h Power on Default Value <7:0> = 0x00 Size: 8 bits

7 6 5 4 3 2 1 0

STOP2 INTMOD Reserved FAULT FAULT Reserved Reserved Reserved

Bit 7-5: Read - Reserved. This bit should be set to 0. Bit 4-3: Read/Write - Number of faults to detect before setting OVT# output to avoid false tripping

due to noise. Bit 2: Read - Reserved. This bit should be set to 0. Bit 1: Read/Write - OVT# Interrupt mode select. This bit default is set to 0, which is compared mode.

When set to 1, interrupt mode will be selected. Bit 0: Read/Write - When set to 1 the sensor will stop monitor.

-45 - Revision A1

Publication Release Date: April 1999

Priliminary W83782D

7.34 Temperature Sensor 2 Hysteresis (High Byte) Register - Index 53h (Bank 1)

Register Location: 53h Power on Default Value <7:0> = 0x4B Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

THYST2<8:1>

Bit 7-0: Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C.

7.35 Temperature Sensor 2 Hysteresis (Low Byte) Register - Index 54h (Bank 1)

Register Location: 54h Power on Default Value <7:0> = 0x0 Attribute: Read Only Size: 8 bits

7 6 5 4 3 2 1 0

Reserved

THYST2<0>

Bit 7: Temperature hysteresis bit 0, which is low Byte. Bit 6-0: Reserved. This bit should be set to 0.

- 46 -

Priliminary W83782D

7.36 Temperature Sensor 2 Over-temperature (High Byte) Register - Index 55h (Bank 1)

Register Location: 55h Power on Default Value <7:0> = 0x50 Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

TOVF2<8:1>

Bit 7-0: Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C.

7.37 Temperature Sensor 2 Over-temperature (Low Byte) Register - Index 56h(Bank 1)

Register Location: 56h Power on Default Value <7:0> = 0x0 Size: 8 bits

7 6 5 4 3 2 1 0

Reserved

TOVF2<0>

Bit 7: Read/Write - Over-temperature bit 0, which is low Byte. Bit 6-0: Read Only - Reserved. This bit should be set to 0.

Publication Release Date: April 1999

-47 - Revision A1

Priliminary W83782D

7.38 Temperature Sensor 3 Temperature (High Byte) Register - Index 50h (Bank 2)

Register Location: 50h Attribute: Read Only Size: 8 bits

7 6 5 4 3 2 1 0

TEMP2<8:1>

Bit 7-0: Temperature <8:1> of sensor 2, which is high byte.

7.39 Temperature Sensor 3 Temperature (Low Byte) Register - Index 51h (Bank 2)

Register Location: 51h Attribute: Read Only Size: 8 bits

7 6 5 4 3 2 1 0

Reserved

TEMP2<0>

Bit 7: Temperature <0> of sensor2, which is low byte. Bit 6-0: Reserved. This bit should be set to 0.

7.40 Temperature Sensor 3 Configuration Register - Index 52h (Bank 2)

Register Location: 52h Power on Default Value <7:0> = 0x00 Size: 8 bits

- 48 -

Priliminary W83782D

7 6 5 4 3 2 1 0

STOP3 INTMOD Reserved FAULT FAULT Reserved Reserved Reserved

Bit 7-5: Read - Reserved. This bit should be set to 0. Bit 4-3: Read/Write - Number of faults to detect before setting OVT# output to avoid false tripping

due to noise. Bit 2: Read - Reserved. This bit should be set to 0. Bit 1: Read/Write - OVT# Interrupt Mode select. This bit default is set to 0, which is Compared Mode.

When set to 1, Interrupt Mode will be selected. Bit 0: Read/Write - When set to 1 the sensor will stop monitor.

7.41 Temperature Sensor 3 Hysteresis (High Byte) Register - Index 53h (Bank 2)

Register Location: 53h Power on Default Value <7:0> = 0x4B Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

THYST3<8:1>

Bit 7-0: Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C.

7.42 Temperature Sensor 3 Hysteresis (Low Byte) Register - Index 54h (Bank 2)

Register Location: 54h Power on Default Value <7:0> = 0x0 Attribute: Read Only Size: 8 bits

Publication Release Date: April 1999

-49 - Revision A1

Priliminary W83782D

7 6 5 4 3 2 1 0

Reserved

THYST3<0>

Bit 7: Temperature hysteresis bit 0, which is low Byte. Bit 6-0: Reserved. This bit should be set to 0.

7.43 Temperature Sensor 3 Over-temperature (High Byte) Register - Index 55h (Bank 2)

Register Location: 55h Power on Default Value <7:0> = 0x50 Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

TOVF3<8:1>

Bit 7-0: Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C.

7.44 Temperature Sensor 3 Over-temperature (Low Byte) Register - Index 56h(Bank 2)

Register Location: 56h Power on Default Value <7:0> = 0x0 Size: 8 bits

- 50 -

7 6 5 4 3 2 1 0

Bit 7: Read/Write - Over-temperature bit 0, which is low Byte. Bit 6-0: Read Only - Reserved. This bit should be set to 0.

7.45 Interrupt Status Register 3 -- Index 50h (BANK4)

Register Location: 50h Power on Default Value <7:0> = 00h Attribute: Read Only Size: 8 bits

7 6 5 4 3 2 1 0

Priliminary W83782D

Reserved

TOVF3<0>

5VSB VBAT Reserved Reserved Reserved Reserved Reserved Reserved

Bit 7-2: Reserved. Bit 1: A one indicates a High or Low limit of VBAT has been exceeded. Bit 0: A one indicates a High or Low limit of 5VSB has been exceeded.

7.46 SMI# Mask Register 3 -- Index 51h (BANK 4)

Register Location: 51h Power on Default Value <7:0> = 0000,0000h Attribute: Read/Write Size: 8 bits

Publication Release Date: April 1999

-51 - Revision A1

Bit 7-2: Reserved.

SMI

7 6 5 4 3 2 1 0

Priliminary W83782D

5VSB VBAT Reserved Reserved Reserved Reserved Reserved Reserved

Bit 1: A one disables the corresponding interrupt status bit for Bit 0: A one disables the corresponding interrupt status bit for

interrupt. interrupt.

7.47 BEEP Control Register 3-- Index 53h (Bank 4)

Register Location: 53h Power on Default Value <7:0> 0000,0000. Reset by MR. Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

EN_5VSB_BP EN_VBAT_BP Reserved Reserved Reserved EN_USER_BP Reserved Reserved

Bit 7-6: Reserved. Bit 5: User define BEEP output function. Write 1, the BEEP is always active. Write 0, this function is

inactive. (Default 0) Bit 4-2: Reserved. Bit 1: Enable BEEP output from VBAT. Write 1, enable BEEP output, which is default value. Bit 0: Enable BEEP Output from 5VSB. Write 1, enable BEEP output, which is default value.

7.48 Reserved Register -- Index 54h--58h

- 52 -

Priliminary W83782D

7.49 Real Time Hardware Status Register I -- Index 59h (Bank 4)

Register Location: 59h Power on Default Value <7:0> 0000,0000. Reset by MR. Attribute: Read Only Size: 8 bits

7 6 5 4 3 2 1 0

VCOREA_STS VINR0_STS +3.3VIN_STS +5VIN_STS TEMP1_STS TEMP2_STS FAN1_STS FAN2_STS

Bit 7: FAN 2 Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter

is in the limit range.

Bit 6: FAN 1 Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter

is in the limit range.

Bit 5: Temperature sensor 2 Status. Set 1, the voltage of temperature sensor is over the limit value.

Set 0, the voltage of temperature sensor is in the limit range.

Bit 4: Temperature sensor 1 Status. Set 1, the voltage of temperature sensor is over the limit value.

Set 0, the voltage of temperature sensor is in the limit range.

Bit 3: +5V Voltage Status. Set 1, the voltage of +5V is over the limit value. Set 0, the voltage of +5V

is in the limit range.

Bit 2: +3.3V Voltage Status. Set 1, the voltage of +3.3V is over the limit value. Set 0, the voltage of

+3.3V is in the limit range.

Bit 1: VINR0 Voltage Status. Set 1, the voltage of VINR0 is over the limit value. Set 0, the voltage of

VINR0 is in the limit range.

Bit 0: VCOREA Voltage Status. Set 1, the voltage of VCORE A is over the limit value. Set 0, the

voltage of VCORE A is in the limit range.

Publication Release Date: April 1999

-53 - Revision A1

Priliminary W83782D

7.50 Real Time Hardware Status Register II -- Index 5Ah (Bank 4)

Register Location: 5Ah Power on Default Value <7:0> 0000,0000. Reset by MR. Attribute: Read Only Size: 8 bits

7 6 5 4 3 2 1 0

+12VIN_STS

-12VIN_STS

-5VIN_STS FAN3_STS CASE_STS TEMP3_STS Reserved Reserved

Bit 7-6: Reserved Bit 5: Temperature sensor 3 Status. Set 1, the voltage of temperature sensor is over the limit value.

Set 0, the voltage of temperature sensor is in the limit range. Bit 4: Case Open Status. Set 1, the case open sensor is sensed the high value. Set 0 Bit 3: FAN3 Voltage Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed

counter is during the limit range. Bit 2: -5V Voltage Status. Set 1, the voltage of -5V is over the limit value. Set 0, the voltage of -5V is

during the limit range. Bit 1: -12V Voltage Status. Set 1, the voltage of -12V is over the limit value. Set 0, the voltage of -

12V is during the limit range. Bit 0: +12V Voltage Status. Set 1, the voltage of +12V is over the limit value. Set 0, the voltage of

+12V is in the limit range.

7.51 Real Time Hardware Status Register III -- Index 5Bh (Bank 4)

Register Location: 5Bh Power on Default Value <7:0> = 0000,0000h Attribute: Read Only Size: 8 bits

- 54 -

Priliminary W83782D

7 6 5 4 3 2 1 0

5VSB_STS VBAT_STS Reserved Reserved Reserved Reserved Reserved Reserved

Bit 7-2: Reserved. Bit 1: VBAT Voltage Status. Set 1, the voltage of VBAT is over the limit value. Set 0, the voltage of

VBAT is during the limit range. Bit 0: 5VSB Voltage Status. Set 1, the voltage of 5VSB is over the limit value. Set 0, the voltage of

5VSB is in the limit range.

7.52 PWMOUT3/4 Clock Select -- Index 5Ch (Bank 4)

Register Location: 5Ch Power on Default Value <7:0> 0001,0001. Reset by MR. Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

Bit 7: Reserved. Bit 6-4: PWMOUT4 clock selection.

The clock defined frequency is same as PWMOUT3 clock selection. Bit 3: Reserved. Bit 2-0: PWMOUT3 clock Selection. <2:0> = 000: 46.87K Hz <2:0> = 001: 23.43K Hz (Default) <2:0> = 010: 11.72K Hz <2:0> = 011: 5.85K Hz <2:0> = 100: 2.93K Hz

PWM3CLKSEL PWM3CLKSEL PWM3CLKSEL Reserved PWM4CLKSEL PWM4CLKSEL PWM4CLKSEL Reserved

Publication Release Date: April 1999

-55 - Revision A1

Priliminary W83782D

7.53 Value RAM 2 Index 50h - 5Ah (auto-increment) (BANK 5)

Address A6-A0

Auto-Increment

50h 5VSB reading 51h VBAT reading 52h Reserved 53h Reserved 54h 5VSB High Limit 55h 5VSB Low Limit. 56h VBAT High Limit 57h VBAT Low Limit

Description

7.54 Winbond Test Register - Index 50h (Bank 6)

- 56 -

Preliminary W83782D

12ts

8. SPECIFICATIONS

8.1 Absolute Maximum Ratings

PARAMETER RATING UNIT

Power Supply Voltage -0.5 to 7.0 V Input Voltage -0.5 to VDD+0.5 V Operating Temperature 0 to +70 Storage Temperature -55 to +150

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.

° C ° C

8.2 DC Characteristics

(Ta = 0° C to 70° C, VDD = 5V ± 10%, VSS = 0V)

PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS

I/O

- TTL level bi-directional pin with source-sink capability of 12 mA

12t

Input Low Voltage VIL 0.8 V Input High Voltage VIH 2.0 V Output Low Voltage VOL 0.4 V IOL = 12 mA Output High Voltage VOH 2.4 V IOH = - 12 mA Input High Leakage ILIH +10 Input Low Leakage ILIL -10

I/O

- TTL level bi-directional pin with source-sink capability of 12 mA and schmitt-trigger level

input

Input Low Threshold Voltage Vt- 0.5 0.8 1.1 V VDD = 5 V

µA µA

VIN = VDD VIN = 0V

Input High Threshold Voltage Vt+ 1.6 2.0 2.4 V VDD = 5 V Hysteresis VTH 0.5 1.2 V VDD = 5 V Output Low Voltage VOL 0.4 V IOL = 12 mA Output High Voltage VOH 2.4 V IOH = - 12 mA Input High Leakage ILIH +10 Input Low Leakage ILIL -10

- 57 - Revision A1

µA µA

Publication Release Date: April 1999

VIN = VDD VIN = 0V

Preliminary W83782D

8.2 DC Characteristics, continued

PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS

OUT

- TTL level output pin with source-sink capability of 12 mA

12t

Output Low Voltage VOL 0.4 V IOL = 12 mA Output High Voltage VOH 2.4 V IOH = -12 mA

OD8 - Open-drain output pin with sink capability of 8 mA

Output Low Voltage VOL 0.4 V IOL = 8 mA

OD12 - Open-drain output pin with sink capability of 12 mA

Output Low Voltage VOL 0.4 V IOL = 12 mA

OD48 - Open-drain output pin with sink capability of 48 mA

Output Low Voltage VOL 0.4 V IOL = 48 mA

INt - TTL level input pin

Input Low Voltage VIL 0.8 V Input High Voltage VIH 2.0 V Input High Leakage ILIH +10 Input Low Leakage ILIL -10

IN

- TTL level Schmitt-triggered input pin

ts

µA µA

VIN = VDD VIN = 0 V

Input Low Threshold Voltage Vt- 0.5 0.8 1.1 V VDD = 5 V Input High Threshold Voltage Vt+ 1.6 2.0 2.4 V VDD = 5 V Hysteresis VTH 0.5 1.2 V VDD = 5 V Input High Leakage ILIH +10 Input Low Leakage ILIL -10

µA µA

VIN = VDD VIN = 0 V

- 58 -

8.3 AC Characteristics

8.3.1 ISA Read/Write Interface Timing

AEN

SA[2:0],CS#

t

AR

Preliminary W83782D

t

RD

t

RCU

IOR#

IOW#

SD[7:0]

IRQ

AEN

SA[2:0],CS#

IOW#

IOR#

t

AW

t

RA

RC

t

RVD

VALID DATA

ISA Bus Read Timing

t

RDH

t

RI

VALID VALID

t

WR

t

WA

WC

t

WCU

SD[7:0]

IRQ

VALID DATA

t

DS

ISA Bus Write Timing

- 59 - Revision A1

t

DH

t

WI

Publication Release Date: April 1999

ISA Read/Write Timing

PARAMETER SYMBOL MIN. MAX. UNIT

Valid Address to Read Active t Valid Address to Write Active t Data Hold t Data Setup t Address Hold from Inactive Read t Read Cycle Update t Read Strobe Width t Read Data Hold t Read Strobe to Clear IRQ t Active Read to Valid Data t Address Hold from Inactive Write t Write Cycle Update t Write Strobe to Clear IRQ t Write Strobe Width t Read Cycle = t Write Cycle = tAW+tWR - t

AR

+ tRD+t

RCV

WCV

Preliminary W83782D

AR

AW

DH

DS

RA

RCU

RD

RDH

RI

RVD

WA

WCU

WI

WR

RC 210 nS

WC 210 nS

10 nS 10 nS

5 nS 80 nS 40 nS

200 nS 120 nS

40 nS

60 nS

115 nS

5 nS 80 nS

60 nS

120 nS

8.3.2 Serial Bus Timing Diagram

SCL

t

HD;SDA

SDA IN

SDA OUT

t

SCL

t

HD;DAT

VALID DATA

t

SU;DAT

Serial Bus Timing Diagram

- 60 -

t

SU;STO

Serial Bus Timing

PARAMETER SYMBOL MIN. MAX. UNIT

SCL clock period t Start condition hold time t Stop condition setup-up time t DATA to SCL setup time t DATA to SCL hold time t SCL and SDA rise time t SCL and SDA fall time t

9. HOW TO READ THE TOP MARKING

The top marking of W83782D

Preliminary W83782D

SCL

HD;SDA

SU;STO

SU;DAT

HD;DAT

R

F

10 uS

4.7 uS

120 nS

5 nS

1.0 uS

300 nS

Left: Winbond logo

1st line: Type number W83782D, D means LQFP (Thickness = 1.4 mm).

2nd line: Tracking code 825 A A

825: packages made in '98, week 25 A: assembly house ID; A means ASE, O means OSE A: IC revision; A means version A, B means version B

Publication Release Date: April 1999

- 61 - Revision A1

10. PACKAGE DIMENTIONS

(48-pin QFP)

H

D

25

12

b

y

37

48

Seating Plane

36

1

e

See Detail F

Preliminary W83782D

Dimension in inch Dimension in mm

Symbol

Min. Nom. Max. Max.Nom.Min.

A

1

24

A

2

A b

E

H

13

c

D

E e

D

H

E

L

1

L

y 0

c

A

2

A

1

A

L

1

Detail F

Notes:

1. Dimensions D & E do not include interlead flash.

2. Dimension b does not include dambar protrusion/intrusion.

3. Controlling dimension: Millimeters

4. General appearance spec. should be based on final visual inspection spec.

---

0.05

1.35

0.17 0.27

0.09

0.45

--- --0

---

1.40

0.20

---

7.00

0.50

9.00

0.60

1.00

0.08

3.5 7

1.60

0.15

1.45

0.20

0.75

Headquarters

No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064

Winbond Electronics (North America) Corp.

2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE

Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

- 62 -

11. APPLICATION CIRCUIT OF WINBOND W83782D / 781D

VOLTAGE SENSING

R11 R

VCOREA

10K

R

R1

10K

R2 R

10K

R

VINR0

3VIN

+12VIN

R4

R

GNDA

10K 1%

R21

R

232K 1%/782D 210K 1%/781D

VBAT/-12VOUT

5VSB/-5VOUT ADRMSEL

120K 1%/782D

90.9K 1%/781D

R10 R

4.7K OVT# SMI#

-12V

-12VIN

VREF

GNDA SDA

-5VIN VCC

R20

R

T3 T2 T1

CS#

-5V

L1 INDUCTOR

FB

VCC

C3 CAP

10u

IOW#

CLKIN

37

VREF

38

VTIN3/PIITD3

39

VTIN2/PIITD2

40

VTIN1/PIITD1

41

VID0

42

OVT#

43

ADRMSEL

44

SMI#

45

SA2/IA2

46

SA1/IA1

47

SA0/IA0

48

CS#

IOR#

VREF VID2

VID0 OVT#

SMI# VID4 A2 A1 A0 GNDD

GNDA

VCOREA

VINR0

C4 CAP

0.1u

36

CLKIN

IOW#

IOR#

1

2

CPU Voltage ID output

3VCC

R12

R13

R

10K

PIIVID4 PIIVID3 PIIVID2 PIIVID1 PIIVID0

VBAT

VREF

5VSB

5.1K 1%/782D

TO PIIX4

Select one of the two setting.

CPUVCOA

GTLVOLT

3VCC

+12V

R18 R

56K 1%/782D

60.4K 1%/781D

R22 R

0 /782D

R

R38

R19 R

{

GNDA

Set A2-A0 as 3 lowest order bits of ISA address bus

SA2 SA1 SA0

Set A2-A0 as bit2, bit1, bit0 of 7 bit I2C address setting

VCC

IA2 IA1 IA0

R36 R

7.5K 1%/782D

60.4K 1%/781D

56K 1%/782D

3VCC

THRM#

EXTSMI#

GNDA GNDD

ADRMSELIN

ADRMSELIN SDA

R

R3

28K 1%

R27 R

R37

R

0/782D

R28

R9 R

4.7K

L2

INDUCTOR

FB

A2 VID4 A1 VID3 A0 VID2

A2 SCL A1 A0

VBAT/-12VOUT

3VIN

+12VIN

-12VIN

3D74D65D56D47D38D29

R14 R

10K

5VSB/-5VOUT

-5VIN

GNDA

BEEP/GPO#

26

GNDA27-5VIN285VSB29VBAT30-12VIN31+12VIN32AVCC33+3.3VIN34VINR035VCOREA

FAN3IO/PWMOUT2

D1/PWMOUT410D0/PWMOUT3

11

R15 R

10K

VID3 VID1

VID325BEEP/GPO#

VID1

12

PWMOUT1

FAN1IO FAN2IO

CASEOPEN#

GNDD

R16 R

10K

VID1 VID0

U1

24

VID2

23 22

SDA

21

SCL

20 19 18 17

VID4

16 15

MR

14 13

VCC

W83782D

SD[0..7]

CAP

10u

FAN1IN FAN2IN

CASEOPEN# RESETDRV

C1

R25 R

0 /781D

R26 R

0 /782D

RSTOUT#

PWMOUT1

R29

R

PWMOUT2

R

FAN3IN

R30

0/782D

0/781D

VCC

C2 CAP

0.1u

Beep Circuits

VCC

R33

0/782D

R

100

LS1

SPEAKER

R35

R32 R

R

0/781D

Q1 NPN

3904/782D

R8 R

4.7K

SMDAT SMCLK

BEEP/GPO#

3VCC

10K/782D

R6R0

R5 R

0

R34 R

R31

R

510/782D

R7 R

4.7K

ADRMSELIN

IRQ

R23 R

0 /782D

R24 R

0 /781D

ADRMSEL

Title

Size Document Number Rev Custom

Date: Sheet of

Winbond Electronic Corp.

W83781D-W83782D Application Circuit

1 2Thursday, July 23, 1998

0.3

Temperature Sensing

VBAT

R39 R

10K 1%

R40 R

10K 1%

R41 R

10K 1%

R42 R

30K 1%

CAPACITOR

R43

30K 1%

CAPACITOR

R44 R

30K 1%

CAPACITOR

CASEOPEN#

R

R66

R

0/781D

VREF

T1 T2 T3 GNDA

Measuring temperature by either thermistor or diode.

VREF

T1

GNDA

VREF

T2

GNDA

VREF

T3

GNDA

Choosing the more accurate measuring method between the above is recommanded.

Case Open Circuits

R65

R

0/782D

R17 R

10M/782D

S1

CASEOPEN SW

R64

R

0/782D

3300p

C5

C6

C7

R68 R

0/781D

C10 CAP

1000p

/781D

RT3

THERMISTOR

RT2 THERMISTOR

RT1

THERMISTOR

2.2M/781D

10K 1%

T

10K 1%

T

10K 1%

T

Q2 NPN

3904

Q3 NPN

3904

These two inverters consume VBAT

74HC14

/781D

1 2

R67 R

D+

D-

(for system)

(from PII CPU)

(for cpu2)

U2A

(for system)

(for cpu1)

(for cpu2)

R69 R

10K/781D

U2B

74HC14

/781D

PWM Circuit for FAN speed control

R59 R

4.7K/782D

R58

1K/782D

Q6

MOSFET N

2N7002/782D

R57 R

4.7K/782D

R56

1K/782D

Q4

MOSFET N

2N7002/782D

CASEOPEN

R54 R

510/782D

R55 R

510/782D

PWMOUT1

PWMOUT2

R70 R

0/781D

34

R

47u/782D

R

Q7

PNP

3906/782D

C9

Q5

PNP

3906/782D

+

C8

47u/782D

0/782D

+12V

R60

R

0/781D

R

R61

R63

0/781D

JP2

HEADER 3

+12V

R62 R

R

JP1

HEADER 3

+12V

JP3

HEADER 3

D1

DIODE

1N4148

3 2 1

DIODE

1N4148

3 2 1

DIODE

1N4148

3 2 1

R45 R

4.7K

R46 R

27K

D2

R48 R

4.7K

R49 R

27K

D3

R51 R

4.7K

R52 R

27K

R47 R

10K

R50 R

10K

R53 R

10K

FAN1IN

FAN2IN

FAN3IN

Title

Size Document Number Rev

Custom

Date: Sheet of

Winbond Electronic Corp.

W83781D-W83782D Application Circuit

2 2Wednesday, July 22, 1998

0.3

Rev. Description

0.1 First published.

0.2

0.3

Change CASEOPEN circuit for W83781D/782D co-layout.

Change 2N3904 in Fan Speed Control circuit to 2N7002.

Winbond Electronic Corp.

Title

W83781D-W83782D Application Circuit

Size Document Number Rev

B

Date: Sheet of

3 3Thursday, July 23, 1998

0.3