Datasheet W83781D Datasheet (Winbond Electronics)

W83781D Winbond H/W Monitoring IC

W83781D Data Sheet Revision History

Pages Dates Version Version

1

2

3

4

5

6

7

8

n.a. n.a. All the version before 0.60 are internal use.

n.a. 11/07/97 0.60 n.a. First published.

5 11/19/97 0.61 n.a. Pin 18-20: I/O Type ¡÷ I/O

4 5

6 33 37 40 43 48

12/17/97 0.62 n.a. Pin18-20:I/O Type ¡÷ Fan 1, Pin18:Fan1¡÷ Fan3

1/13/98 0.63 n.a. 8.24 index 55h(Bank 0) ¡÷ Winbond Test Register

on Web

Main Contents

12ts

Pin23: I/O Type ¡÷ OUT Pin42: I/O Type ¡÷ OUT

8.30 index 52h(Bank 1) bit2 ¡÷ Reserve

8.37 index 52h(Bank 2) bit2 ¡÷ Reserve

9.2 I/O 12ts TTL DC Characteristics Package QFT ¡÷ LQFP

8t 12

9

10

Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.

W83781D

Monitoring IC

Winbond H/W

TABLE OF CONTENTS

1. GENERAL DESCRIPTION.......................................................................................................... 1

2. FEATURES.................................................................................................................................... 1

2.1 MONITORING ITEMS......................................................................................................................................... 1

2.2 ACTIONS ENABLING......................................................................................................................................... 2

2.3 GENERAL............................................................................................................................................................2

2.4 PACKAGE ............................................................................................................................................................ 2

3. KEY SPECIFICATIONS ..............................................................................................................2

4. BLOCK DIAGRAM ...................................................................................................................... 3

5. PIN CONFIGURATION ............................................................................................................... 4

6. PIN DESCRIPTION ...................................................................................................................... 5

7. FUNCTIONAL DESCRIPTION ................................................................................................... 7

7.1 GENERAL DESCRIPTION .................................................................................................................................. 7

7.1.1 The first serial bus access timing are shown as follow: .................................................................................. 9

7.1.2 The serial bus timing of the temperature 2 and 3 is shown as follow: ........................................................... 10

7.2 ANALOG INPUTS.............................................................................................................................................. 12

7.3 FAN INPUTS AND FAN CONTROL ................................................................................................................. 13

7.4 TEMPERATURE MEASUREMENT MACHINE................................................................................................ 14

8. CONTROL AND STATUS REGISTERS................................................................................... 16

8.1 ADDRESS REGISTER (PORT X5H).................................................................................................................. 16

8.2 DATA REGISTER (PORT X6H)......................................................................................................................... 19

8.3 CONFIGURATION REGISTER ¾- INDEX 40H (BANK 0)................................................................................19

8.4 INTERRUPT STATUS REGISTER 1¾ INDEX 41H (BANK 0).......................................................................... 20

8.5 INTERRUPT STATUS REGISTER 2 ¾ INDEX 42H (BANK 0)......................................................................... 21

Publication Release Date: Nov. 1997

- I - Version 0.60

W83781D

Monitoring IC

Winbond H/W

8.6 SMI# MASK REGISTER 1 ¾ INDEX 43H (BANK 0)........................................................................................ 21

8.7 SMI# MASK REGISTER 2 ¾ INDEX 44H (BANK 0)......................................................................................... 22

8.8 IRQ MASK REGISTER 2 ¾ INDEX 45H (BANK 0)........................................................................................... 22

8.9 IRQ MASK REGISTER 2 ¾ INDEX 46H (BANK 0)........................................................................................... 23

8.10 VID/FAN DIVISOR REGISTER ¾ INDEX 47H (BANK 0)...............................................................................23

8.11 SERIAL BUS ADDRESS REGISTER ¾ INDEX 48H (BANK 0)....................................................................... 24

8.12 VALUE RAM ¾ INDEX 20H- 3FH OR 60H – INDEX 7FH (AUTO-INCREMENT) (BANK 0)........................ 25

8.13 VOLTAGE ID (VID7-4) – INDEX 49H (BANK 0)...........................................................................................27

8.14 TEMPERATURE 2 AND TEMPERATURE 3 SERIAL BUS ADDRESS REGISTER INDEX 4AH (BANK 0). 28

8.15 PIN CONTROL REGISTER – INDEX 4BH (BANK 0)..................................................................................... 29

8.16 IRQ/OVT# PROPERTY SELECT – INDEX 4CH (BANK 0)...........................................................................30

8.17 FAN IN/OUT AND BEEP/GPO# CONTROL REGISTER -- INDEX 4DH (BANK 0) ....................................... 31

8.18 REGISTER 50H ~ 5FH BANK SELECT -- INDEX 4EH (NO AUTO INCREASE) (BANK 0).......................... 32

8.19 WINBOND VENDOR ID -- INDEX 4FH (NO AUTO INCREASE) (BANK 0) ................................................. 32

8.20 RESISTOR-TEMPERATURE TABLE REGISTER – INDEX 50H - 51H (BANK 0)......................................... 33

8.21 WINBOND TEST REGISTER 1 – INDEX 52H (BANK 0)............................................................................... 33

8.22 WINBOND TEST REGISTER 2 – INDEX 53H (BANK 0)............................................................................... 33

8.23 WINBOND TEST REGISTER 3 – INDEX 54H (BANK 0)............................................................................... 33

8.24 WINBOND TEST REGISTER 4 – INDEX 55H (BANK 0)............................................................................... 33

8.25 BEEP CONTROL REGISTER 1— INDEX 56H (BANK 0) (AUTO-INCREMENT)........................................... 34

8.26 BEEP CONTROL REGISTER 2— INDEX 57H (BANK 0) ( NO AUTO-INCREMENT).................................... 34

8.27 CHIP ID- INDEX 58H (BANK 0)...................................................................................................................... 35

8.28 TEMPERATURE SENSOR 2 TEMPERATURE REGISTER - INDEX 50H (BANK 1)..................................... 36

8.29 TEMPERATURE SENSOR 2 TEMPERATURE REGISTER - INDEX 51H (BANK 1)..................................... 36

8.30 TEMPERATURE SENSOR 2 CONFIGURATION REGISTER - INDEX 52H (BANK 1)................................. 37

8.31 TEMPERATURE SENSOR 2 HYSTERESIS (HIGH BYTE) REGISTER - INDEX 53H (BANK 1).................. 37

8.32 TEMPERATURE SENSOR 2 HYSTERESIS (LOW BYTE) REGISTER - INDEX54H (BANK 1).................... 38

8.33 TEMPERATURE SENSOR 2 OVER-TEMPERATURE(HIGH BYTE) REGISTER - INDEX 55H (BANK 1) .. 38

8.34 TEMPERATURE SENSOR 2 OVER-TEMPERATURE (LOW BYTE) REGISTER - INDEX 56H (BANK 1).. 39

8.35 TEMPERATURE SENSOR 3 TEMPERATURE REGISTER - INDEX 50H (BANK 2)..................................... 39

8.36 TEMPERATURE SENSOR 3 TEMPERATURE REGISTER - INDEX 51H (BANK 2)..................................... 40

Publication Release Date: Nov. 1997

- II - Version 0.60

W83781D

Monitoring IC

Winbond H/W

8.37 TEMPERATURE SENSOR 3 CONFIGURATION REGISTER - INDEX 52H (BANK 2)................................. 40

8.38 TEMPERATURE SENSOR 3 HYSTERESIS (HIGH BYTE) REGISTER - INDEX 53H (BANK 2).................. 41

8.39 TEMPERATURE SENSOR 3 HYSTERESIS (LOW BYTE) REGISTER - INDEX 54H (BANK 2)................... 41

8.40 TEMPERATURE SENSOR 3 OVER-TEMPERATURE (HIGH BYTE)REGISTER - INDEX 55H (BANK 2) .. 42

8.41 TEMPERATURE SENSOR 3 OVER-TEMPERATURE (LOW BYTE) REGISTER - INDEX 56H (BANK 2).. 42

9. SPECIFICATIONS...................................................................................................................... 43

9.1 ABSOLUTE MAXIMUM RATINGS .................................................................................................................. 43

9.2 DC CHARACTERISTICS................................................................................................................................... 43

9.2.1 AC Characteristics ...................................................................................................................................... 45

9.2.2 ISA Read/Write Interface Timing ................................................................................................................ 45

9.2.3 Serial Bus Timing Diagram......................................................................................................................... 46

10. HOW TO READ THE TOP MARKING.................................................................................. 47

11. PACKAGE DIMENTIONS....................................................................................................... 48

Publication Release Date: Nov. 1997

- III - Version 0.60

W83781D

PRELIMINARY

1. GENERAL DESCRIPTION

The W83781D is a hardware status monitoring IC for personal computers, server computers, or microprocessor based systems. W83781D can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system to work stable and properly. W83781D provides both ISA and I2CTM serial bus interface.

A 8-bit analog-to-digital converter (ADC) was built inside W83781D. The W83781D can monitor 3 external thermistor temperature sensors, 5 positive analog voltage inputs, two inverting inputs (for monitoring negative voltages), and also three fan tachometer outputs. There is also one input for case open detection circuits.

With the application software, the users can read all the monitored parameters of system from time to time. The application software could be the popular IntelTM LDCM (LANDesk Client Management) or Winbonds application software. Also the users can set up the upper and lower limits of these monitored parameters and to activate two programmable and maskable interrupts. An optional beep tone could be used as warning signal when the monitored parameters is out of the preset range.

Additionally, 5 VID inputs are provided to read the VID of CPU (such as PentiumTM II) if applicable. This is to provide the Vcore correction automatically. Also W83781D uniquely provides an optional feature: early stage (before BIOS was load) beep warning. This is to detect if the fatal elements present --- VcoreA, +3.3V voltage fail, and the system can not be boomed up.

2. FEATURES

2.1 Monitoring Items

• 3 thermal inputs from remote thermistors

• 5 positive voltage inputs (typical for +12V, +5V, +3.3V, VcoreA, VcoreB)

• 2 op amps for negative voltage monitoring (typical for -12V, -5V)

• 3 fan speed monitoring inputs

• Case open detection input

• WATCHDOG comparison of all monitored values

• Programmable hysteresis and setting points for all monitored items

-1- Publication Release Date : Nov. 1997

Revision 0.60

2.2 Actions Enabling

• Warning signal pop up in application software

• Beep tone warning

• Fan ON/OFF control

• Issue SMI#, IRQ to activate system protection

2.3 General

• ISA and I2CTM serial bus interface

• 5 VID input pins for CPU Vcore identification

• Initial power fault beep (for +3.3V, VcoreA)

• Master reset input to W83781D

• Independent power plane of digital Vcc and analog Vcc (input to IC)

• Intel LDCMTM compatible

W83781D

PRELIMINARY

• Winbond monitoring application software support

• Input clock rate optional for 24, 48, 14.318 MHz

2.4 Package

• 48-pin LQFP

3. KEY SPECIFICATIONS

• Voltage monitoring accuracy ±1% (Max)

• Monitoring Temperature Range and Accuracy

- 40°C to +120°C ± 3°C(Max)

• Supply Voltage 5V

• Supply Current Operating: 1 mA typ. Shutdown: 10 µA typ.

• ADC Resolution 8 Bits

- 2 - Publication Release Date : Nov. 1997

Revision 0.60

4. BLOCK DIAGRAM

IN0

:

IN6

VID0 : VID4

VTIN3 : VTIN1

: :

8-Bit A/D and Mux 16mV LSB 0~4.096V Input

Configure and Control Registers

Watch-Dog and Interrupt Status Registers

W83781D

PRELIMINARY

SMI#

IRQ

OVT#

FAN3 : FAN1

CASEOPEN

MR

: :

FAN Speed Counter

ISA/Serial Bus Interface

C

S

D

C

A

L

(Serial Bus) (ISA Bus Interface)

I

C

L

O

K

W

I

R

N

#

A

O

S

2

R

# D #

D

A 1

D

A

7

6

0

D 5

D4D3D

BEEP / GPO# RSTOUT#

D

1

2

0

- 3 - Publication Release Date : Nov. 1997

Revision 0.60

5. PIN CONFIGURATION

1

3

7

N

A

3

#

1

W83781D

PRELIMINARY

B E

V

+

C

3.3

O

V

R

I

E

N

A

B

-

+

-

12

5

12

5

12

V

O

I

U

N

U

N

T

E P

-

/

G

5

G V I

V

N

P

I

D

O

D

#

VREF VTIN3 VTIN2 VTIN1

VID0

OVT#

IRQ

SMI#

A2 A1 A0

CS#

36

37

48

1

I

C

O

L

W

R

K

#

I N

W83781D

D

D6D

4

2

5

25

24

VID2 RSTOUT#

SDA

C

S

L

FAN1 IN/OUT FAN2 IN/OUT

FAN3 IN/OUT VID4 CASEOPEN

MR

G ND D

13

12

V

D

I

0

D

CC

V

- 4 - Publication Release Date : Nov. 1997

Revision 0.60

6. PIN DESCRIPTION

System clock input. Can select 48MHz or 24MHz or 14.318MHz.

The default is 24MHz.

4-

11

Bi-directional ISA bus Data lines. D0 corresponds to the low order

bit, with D7 the high order bit.

Voltage Supply readouts from P6.This value is read in the VID/Fan

Divisor Register.

+5V VCC power. Bypass with the parallel combination of 10µF

(electrolytic or tantalum) and 0.1µF (ceramic) bypass capacitors.

CASE OPEN. An active high input from an external circuit which

latches a Case Open event. This line can go high without any

clamping action intrusion regardless of the powered state of the

W83781D. The W83781D provides an internal open drain on this

line, controlled by Bit 7 of IRQ Mask Register 2, to provide a

minimum 20 ms reset of this line.

Voltage Supply readouts from P6.This value is read in the bit <0>

of Device ID Register.

18-

20

Fan on-off control output. These multifunctional pins can be

programmable input or output.

8 mA driver (open drain), active low output with a 20 ms minimum

pulse width. Available when enabled via Bit 7 in SMI# Mask

Register 2.

I/O

- TTL level bi-directional pin with 12 mA source-sink capability

12t

I/O

- TTL level and schmitt trigger

12ts

OUT

- TTL level output pin with 12 mA source-sink capability

12t

OUT8t - TTL level output pin with 8 mA source-sink capability AOUT - Output pin(Analog) OD8 - Open-drain output pin with 8 mA sink capability OD12 - Open-drain output pin with 12 mA sink capability OD48 - Open-drain output pin with 48 mA sink capability INt - TTL level input pin INts - TTL level input pin and schmitt trigger AIN - Input pin(Analog)

W83781D

PRELIMINARY

Pin Name

Type Description

No.

IOR# 1 IN IOW# 2 IN CLKIN 3 IN

D7~D0

I/O

VID1 12 IN

ts ts

t

12t

t

An active low standard ISA bus I/O Read Control. An active low standard ISA bus I/O Write Control.

VCC (+5V) 13 POWER

GNDD 14 DGROUND Internally connected to all digital circuitry. MR 15 IN CASEOPEN 16 I/O

VID4 17 IN

FAN3-FAN1

I/O

ts

12t

t

12ts

Master reset input.

0V to +5V amplitude fan tachometer input /

IN/OUT

SCL 21 IN SDA 22 I/O

ts

12ts

RSTOUT# 23 OUT

Serial Bus Clock. Serial Bus bi-directional Data.

8t

- 5 - Publication Release Date : Nov. 1997

Revision 0.60

6. Pin Description , continued

Voltage Supply readouts from P6.This value is read in the VID/Fan

Divisor Register.

Voltage Supply readouts from P6.This value is read in the VID/Fan

Divisor Register.

Beep function or General purpose output (active low). This pin is

open drain driving 48 mA.

Internally connected to all analog circuitry. The ground reference

for all analog inputs.

This pin is Analog Vcc and connects internal monitor channel IN3

with fixed scale.

Voltage Supply readouts from P6.This value is read in the VID/Fan

Divisor Register.

System Management Interrupt (open drain). This output is enabled

when Bit 1 in the Configuration Register (CR40) is set to 1. The

default state is disabled.

45-

47

The three lowest order bits of the 16-bit ISA Address Bus. A0

corresponds to the lowest order bit.

Chip Select input from an external decoder which decodes high

order address bits on the ISA Address Bus. This is an active low

input.

W83781D

PRELIMINARY

Pin Name

Type Description

No.

VID2 24 IN

VID3 25 IN

BEEP/GPO# 26 OD

t

48

This multifunctional pin is programmable selected by CR4D bit 6.

GNDA 27 AGROUND

-5VIN 28 AIN Ground-referred inverting op amp input.

-5VOUT 29 AOUT Output of inverting op amp for Input 6.

-12VOUT 30 AOUT Output of inverting op amp for Input 5.

-12VIN 31 AIN Ground-referred inverting op amp input. +12VIN 32 AIN 0V to 4.096V FSR Analog Inputs. +5VIN 33 AIN

+3.3VIN 34 AIN 0V to 4.096V FSR Analog Inputs. VCOREB 35 AIN 0V to 4.096V FSR Analog Inputs. VCOREA 36 AIN 0V to 4.096V FSR Analog Inputs. VREF 37 AOUT Reference Voltage. VTIN3 38 AIN Thermistor 3 terminal input. VTIN2 39 AIN Thermistor 2 terminal input. VTIN1 40 AIN Thermistor 1 terminal input. VID0 41 IN

t

OVT# 42 OD IRQ 43 OUT SMI# 44 OD

A2-A0

IN

CS# 48 IN

12

12t

12

t

Over temperature Shutdown Output. Interrupt Request.

# Indicates Active Low("Not")

- 6 - Publication Release Date : Nov. 1997

Revision 0.60

W83781D

PRELIMINARY

7. FUNCTIONAL DESCRIPTION

7.1 General Description

The W83781D provides 5 analog positive inputs, 2 analog negative input, 3 fan speed monitors or fan ON/OFF control, 3 thermistor voltage inputs, case open detection and beep function output when the monitor value exceed the set limit value. When start the monitor function on the chip, the watch dog machine monitor every function and store the value to registers. If the monitor value exceeds the limit value, the interrupt status will be set to 1.

The W83781D provides two interface for microprocessor to read/write internal registers. The first interface use ISA Bus to access which the ports of low byte (bit2~bit0) are defined in the port 5h and 6h. The high byte of these ports is decoded by Chip Select (CS#), the general decoded address is set to port 295h and port 296h. These two ports are described as following:

Port 295h: W83781D Index register port. Port 296h: Data port. The register structure is showed as the diagram next page.

The second interface use Serial Bus. In the W83781D has three serial bus address. That is, the first address defined at CR48 can read/write all registers excluding Bank 1 and Bank 2 temperature 2/3 registers, the second address defined at CR4A.bit2-0 only read/write temperature sensor 2 registers, and the third address defined at CR4A.bit6-4 only can access (read/write) temperature sensor 3 registers.

- 7 - Publication Release Date : Nov. 1997

Revision 0.60

ISA

Data

Bus

ISA

Address

Bus

Port 5h

Index

Register

Port 6h

Data Register

Configuration Register

40h

Interrupt Status Registers

41h, 42h

SMI# & IRQ Mask Registers

42h, 43, 44h, 45h

VID<3:0>/Fan Divisor Register

Temperature 2, 3 Serial Bus Address

Fan IN/OUT and BEEP/GPO# Control Register

Select Bank for 50h~5Fh Reg.

47h

Serial Bus Address

48h

Monitor Value Registers

20h~3Fh

and

60h~7Fh (auto-increment)

VID<4>/Device ID

49h

4Ah

Pin Control Register

4Bh

IRQ Polarity Select

4Ch

4Dh

4Eh

Winbond Vendor ID

4Fh

BANK 0

R-T Table Value BEEP Control Register Winbond Test Register

50h~58h

W83781D

PRELIMINARY

Temperature 2 Control/Staus Registers

Temperature 3 Control/Staus Registers

BANK 1

50h~56h

BANK 2

50h~56h

- 8 - Publication Release Date : Nov. 1997

Revision 0.60

7.1.1 The first serial bus access timing are shown as follow:

(a) Serial bus write to internal address register followed by the data byte

W83781D

PRELIMINARY

0

7 8 0 7 8

SCL

SDA

0 1 0 1 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0

Start By

Master

Frame 1

Serial Bus Address Byte

R/W

781D

Ack

0

SCL

(Continued)

SDA (Continued)

D7 D6 D5 D4 D3 D2 D1 D0

Serial Bus Write to Internal Address Register followed by the Data Byte

(b) Serial bus write to internal address register only

SCL

SDA

0

0 1 0 1 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0

Start By

Master

Frame 1

Serial Bus Address Byte

Serial Bus Write to Internal Address Register Only

7 8 0 7 8

R/W

Ack

by

781D

0

Ack

by

Internal Index Register Byte

Frame 2

781D

by

7 8

Ack

Stop

by

781D

Frame 3

Data Byte

Internal Index Register Byte

Frame 2

Master

781D

Ack

Stop by

by

Master

(c) Serial bus read from a register with the internal address register prefer to desired location

SCL

SDA

0

0 1 0 1 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0

Start By

Master

Frame 1

Serial Bus Address Byte

Serial Bus Write to Internal Address Register Only

7 8 0 7 8

R/W

Ack

781D

by

Internal Index Register Byte

Frame 2

0

Ack by

Master

Stop by Master

- 9 - Publication Release Date : Nov. 1997

Revision 0.60

7.1.2 The serial bus timing of the temperature 2 and 3 is shown as follow:

W83781D

PRELIMINARY

(a) Typical 2-byte read from preset pointer location (Temp, TOS, T

SCL

SDA

0

0 1 0 1 1 0 1 D7 D1 D0

Start By

Master

Frame 1

Serial Bus Address Byte

7 8 0 7 8

R/W

Ack

by

781D

... ...

...

Frame 2

MSB Data Byte

)

HYST

0 7

D7 D1 D0

Ack by

Master

...

LSB Data Byte

Frame 3

Typical 2-Byte Read From Preset Pointer Location

(b) Typical pointer set followed by immediate read for 2-byte register (Temp, TOS, T

4

Frame 2

Pointer Byte

D1 D0

0 7

SCL

SDA

0

1 0 0 1 A2 A1 A0 R/W

Start By

Master

0

Frame 1

Serial Bus Address Byte

7 8 0

0 0 0 0 0 0

Ack

by

781D

7 8 0 7 8

... ...

781D

Ack

by

HYST

Ack

by

Master

)

Stop by

Master

...

SDA

1 0 0 1 A2 A1 A0 R/W

Start By

Master

Frame 3

Serial Bus Address Byte

0

D7 D1 D0

Ack

by

781D

Frame 4

MSB Data Byte

Ack

by

Master

Typical Pointer Set Followed by Immediate Read for 2-Byte Register

(c) Typical read 1-byte from configuration register with preset pointer

SCL

SDA

0

1 0 0 1 A2 A1 A0 R/W D1D5 D4 D3D6

Start By

Master

Frame 1

Serial Bus Address Byte

Typical 1-Byte Read From Configuration With Reset Pointer

7 8 0

Ack

by

781D

D7 D2

Frame 2

Data Byte

- 10 - Publication Release Date : Nov. 1997

...

D7 D1 D0

Frame 5

LSB Data Byte

8

7

D0

No Ack

by

Master

No Ack Master

Stop by Master

by

Revision 0.60

(d) Typical pointer set followed by immediate read from configuration register

W83781D

PRELIMINARY

SCL

0

SDA

1 0 0 1 A2 A1 A0 R/W

Start By

Master

Frame 1

Serial Bus Address Byte

0

SCL (Cont..)

SDA (Cont..)

1 0 0 1 A2 A1 A0 R/W

Repea Start

Master

By

Frame 3

Serial Bus Address Byte

Typical Pointor Set Followed by Immediate Read from Temp 2/3 Configuration Register

(e) Temperature 2/3 configuration register Write

SCL

0

7 8 0

Ack

by

781D

7 8 0

0 0 0 0 000

Ack

by

781D

D7 D5 D4

D6 D3

Frame 4

MSB Data Byte

4

Frame 2

Pointer Byte

D2 D1 D0

4

D1 D0

7

No Ack Master

7 8

8

by

781D

Ack

by

Stop by Master

...

SDA

1 0 0 1 A2 A1 A0 R/W

Start By

Master

Frame 1

Serial Bus Address Byte

SCL (Cont...)

SDA (Cont...)

Configuration Register Write

0 0 0 0 0 0 0

Ack

by

781D

0

Frame 2

Pointer Byte

7 8

D1 D0

781D

Ack

by

0 0 D4 D3 D2 D10 D0

Ack

Stop

by

Frame 3

Configuration Data Byte

781D

Master

by

- 11 - Publication Release Date : Nov. 1997

Revision 0.60

W83781D

PRELIMINARY

(f) Temperature 2/3 TOS and T

SCL

SDA

SCL (Cont...)

SDA (Cont...)

0

1 0 0 1 A2 A1 A0 R/W

Start By

Master

Serial Bus Address Byte

0

D6 D5 D4 D3 D2 D1D7 D0

Frame 3

MSB Data Byte

HYST

Frame 1

write

7 8 0

Ack

by

781D

7 8

Ack

by

781D

4

0

0 0 0 0

Frame 2

Pointer Byte

D6 D5 D4 D3 D2 D1D7 D0

Frame 4

LSB Data Byte

D1 D0

7 8

781D

Ack

by

Ack

Stop

by

781D

Master

Configuration Register Write

7.2 Analog Inputs

The maximum input voltage of the analog pin is 4.096 because the 8-bit ADC has a 16mv LSB. Really, the application of the PC monitoring would most often be connected to power suppliers. The CPU V-core voltage and 3.3V can directly connected to these analog inputs. The +5V and +12V inputs should be reduced a factor with external resistors so as to obtain the input range. As followed figure is shown.

Pin 36+2.5VINA

Positive Input

Negative Input

Positive Inputs

Vs

R1

R

IN

+12VIN

R2

+2.5VINB

+3.3VIN

VDD(+5V)

-12VIN

-12VOUT

R

F

-5VOUT Pin 29

-5VIN

Pin 31

Pin 30

Pin 28

Pin 35 Pin 34 Pin 33 Pin 32

+

8-bit ADC

with

16mV LSB

Typical Thermister Connection

10K, 1%

R

THM

VREF Pin 37 VTIN3

VTIN2 VTIN1

Pin 38 Pin 39 Pin 40

- 12 - Publication Release Date : Nov. 1997

Revision 0.60

W83781D

PRELIMINARY

The input voltage can be expressed as following equation.

R

V V

= ×

IN s

The value of R1 and R2 can be selected to 28K Ohms and 10K Ohms, respectively, when the input voltage is 12V. The Pin 33 is connected to +5V power supply to provide analog power, and this voltage is connected to internal resistors to monitor the +5V voltage.

The negative voltage should be connected an op amps to invert and reduce the -5V and -12V voltage. The input voltage can be calculated by following equation.

V V

= − × ( )

S IN

The Winbond recommended value is RIN=90.9K Ohms and RF=60.4K Ohms for -5V voltage input, RIN=210K Ohms and RF=60.4K Ohms for -12V voltage input.

The temperature sensors are connected by a 10K Ohms, then connect to VREF (Pin 37). The sensors should choose 10K Ohms at 25øC and B-value is 3435 for default R-T table. If the B-value is not 3435, the R-T table should be re-program to generate a correct temperature.

2

R R

+

1 2

R

IN

F

7.3 FAN Inputs and FAN Control

Inputs are provides for signals from fans equipped with tachometer outputs. The level of these signals should be set to TTL level, and maximum input voltage can not be over +5.5V. If the input signals from the tachometer outputs are over the VCC, the external trimming circuit should be added to reduce the voltage to obtain the input specification. The normal circuit and trimming circuits are shown as following.

Determine the fan counter according to:

6

×

135 10

Count

The default divisor is 2 and defined at CR47.bit7~4 and CR4B.bit7~6. The followed table is an example for the relation of divisor, PRM, and count.

Divisor Nominal

PRM

Time per

Revolution

1 8800 6.82 ms 153 6160 9.74 ms

2

4400 13.64 ms 153 3080 19.48 ms 3 2200 27.27 ms 153 1540 38.96 ms 4 1100 54.54 ms 153 770 77.92 ms

.

=

RPM Divisor

×

Counts 70% RPM Time for 70%

- 13 - Publication Release Date : Nov. 1997

Revision 0.60

W83781D

PRELIMINARY

FAN Out

FAN

Connector

FAN Out

FAN

Connector

+12V

GND

+5V

Pull-up resister

4.7K Ohms

Fan Input

Fan with Tach Pull-Up to +5V

+12V

Pull-up resister

> 1K

+12V

GND

Fan Input

3.9V Zener

Pin 18/19/20

W83781D

+12V

Pull-up resister

4.7K Ohms

+12V

FAN Out

GND

FAN

14K~39K

Fan Input

10K

Connector

Fan with Tach Pull-Up to +12V, or Totem-Pole

Output and Register Attenuator

+12V

Pull-up resister < 1K or totem-pole output

FAN Out

FAN

Connector

+12V

GND

> 1K

3.9V Zener

Fan Input

Pin 18/19/20

W83781D

Pin 18/19/20

W83781D

Fan with Tach Pull-Up to +12V and Zener Clamp

Fan with Tach Pull-Up to +12V, or Totem-Pole

Putput and Zener Clamp

7.4 Temperature Measurement Machine

The temperature data format is 8-bit two -complement for sensor 1 and 9-bit two -complement for sensor 2/3. The table are expressed the temperature data as following.

Temperature 8-Bit Digital Output 9-Bit Digital Output

8-Bit Binary 8-Bit Hex 9-Bit Binary 9-Bit Hex

+125øC 0111,1101 7Dh 0,1111,1010 0FAh

+25øC 0001,1001 19h 0,0011,0010 032h

+1øC 0000,0001 01h 0,0000,0010 002h

+0.5øC - - 0,0000,0001 001h

+0øC 0000,0000 00h 0,0000,0000 000h

-0.5øC - - 1,1111,1111 1FFh

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Revision 0.60

7.4 temperature data, continued

Temperature 8-Bit Digital Output 9-Bit Digital Output

8-Bit Binary 8-Bit Hex 9-Bit Binary 9-Bit Hex

-1øC 1111,1111 FFh 1,1111,1110 1FFh

-25øC 1110,0111 E7h 1,1100,1110 1CEh

-55øC 1100,1001 C9h 1,1001,0010 192h

W83781D

PRELIMINARY

The W83781D temperature interrupt has two mode: (1) The first is Interrupt Mode--exceeding T causes an interrupt until reset by reading Interrupt Status Register 1 (CR41). Once an interrupt event has occurred over TOI, the interrupt will occur again by the temperature going below T Comparator Mode--setting the T

limit to 127øC will cause the comparator mode. When

HYST

. (2)

temperature exceeds TOI, the interrupt will be generate Interrupt. If the temperature goes below the TOI, the interrupt will be reset. Two interrupt modes are shown as below.

T

HYST

127 C

T

OI

T

HYST

IRQ IRQ

*Interrupt Reset when Interrupt Status Register 1 is read

* * *

(1) Interrupt Mode

T

OI

(2) Comparator Mode

The temperature sensor 2 or 3 Over-Temperature (OVT) response is same as temperature sensor 1 IRQ signal.

T

OI

T

HYST

(Comparator Mode; default)

((Interrupt Mode)

OVT#

* * *

*Interrupt Reset when Temperature 2/3 is read

Over-Temperature Response Diagram

- 15 - Publication Release Date : Nov. 1997

*

Revision 0.60

W83781D

INDEX Pointer

PRELIMINARY

8. CONTROL AND STATUS REGISTERS

8.1 Address Register (Port x5h)

The main register is the INDEX Register located at Port x5h. The bit designations are as follows:

7 6 5 4 3 2 1 0

Busy

Bit7: Read Only

The logical 1 indicates the device is busy because of a Serial Bus transaction or another ISA bus

transaction. With checking this bit, multiple ISA drivers can use W83781D without

interfering with each other or a Serial Bus driver.

It is the user's responsibility not to have a Serial Bus and ISA bus operations at the same time. This bit is:

Set: with a write to Port x5h or when a Serial Bus transaction is in progress. Reset: with a write or read from Port x6h if it is set by a write to Port x5h, or when the Serial Bus

transaction is finished.

Bit 6-0: Read/Write

INDEX of Control and Status Registers. See the tables below for detail.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Busy Index Pointer (Power On default 00h)

(Power On default 0) A6 A5 A4 A3 A2 A1 A0

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Revision 0.60

Index Pointer (A6-A0)

W83781D

PRELIMINARY

Registers Bank A6-A0

in Hex

Configuration Register 0 40h 00001000 Interrupt Status Register 1 0 41h 00000000 Auto-increment to the

Interrupt Status Register 2 0 42h 00000000 SMI# Mask Register 1 0 43h 00000000 Auto-increment to the

SMI# Mask Register 2 0 44h 00000000 IRQ Mask Register 1 0 45h 00000000 Auto-increment to the

IRQ Mask Register 2 0 46h 00000000 VID/Fan Divisor Register 0 47h <7:4> = 0101;

Serial Bus Address Register

0 48h <6:0> = 0101101; <7> = 0

Power On Value of

Registers: <7:0>in Binary

<3:0> = VID3-VID0

Notes

address of Interrupt Status Register 2 after a read or write to Port x6h.

address of SMI# Mask Register 2 after a read or write to Port x6h.

address of IRQ Mask Register 2 after a read or write to Port x6h

Voltage ID 0 49h <7:6> is Reserved

<5:4> is 01 binary <0> is mapped to VID <4>

Temperature 2 and Temperature 3 Serial Bus Address Register

Pin Control Register 0 4Bh <7:0> 44h RQ/OVT# Property Select 0 4Ch <7:0> ---0,0001 FAN IN/OUT and

BEEP/GPO# Control Register

Register 50h ~ 5Fh Bank Select

Winbond Vendor ID 0 4Fh <15:0> = 5CA3h Resistor-Temperature

Table Register

0 4Ah <7:0> = 0000,0001 binary

0 4Dh <7:0> 0001,0101

0 4Eh <6:3> = Reserved, <7> =

1, <2:0> = 0

0 50-51h

- 17 - Publication Release Date : Nov. 1997

Revision 0.60

Index Pointer (A6-A0),continued

Registers Bank A6-A0

in Hex

Power On Value

of Registers:

<7:0>in Binary

W83781D

PRELIMINARY

Notes

FAN Input Clock Pre-Divisor Register 2

BEEP Control Register 1 0 56h <7:0> 0000,0000 BEEP Control Register 2 0 57h <7:0> 1000-0000 Chip ID 0 58h <7:0> 0001-0000 Temperature Sensor 2

Temperature Register Temperature Sensor 2

Configuration Register Temperature Sensor 2 Hysteresis

(High Byte) Register Temperature Sensor 2 Hysteresis

(Low Byte) Register Temperature Sensor 2 Over-

temperature(High Byte) Register Temperature Sensor 2 Over-

temperature (Low Byte) Register Temperature Sensor 3

Temperature Register Temperature Sensor 3

Configuration Register

0 55h <7:0> -000,0001

1 50-51h

1 52h <7:0> = 0x00

1 53h <7:0> = 0x4B

1 54h <7:0> = 0x0

1 55h <7:0> = 0x50

1 56h <7:0> = 0x0

2 50-51h

2 52h <7:0> = 0x00

Temperature Sensor 3 Hysteresis (High Byte) Register

Temperature Sensor 3 Hysteresis (Low Byte) Register

Temperature Sensor 3 Overtemperature (High Byte)Register

Temperature Sensor 2 Overtemperature (Low Byte) Register

Value RAM 0 20-3Fh Value RAM 0 60-7Fh Auto-increment to the next

Note: Index Pointer (A6-A0) and Value RAM only can be read at the

2 53h <7:0> = 0x4B

2 54h <7:0> = 0x0

2 55h <7:0> = 0x50

2 56h <7:0> = 0x0

- 18 - Publication Release Date : Nov. 1997

location after a read or write to Port x6h and stop at 7Fh.



accurate bank



.

Revision 0.60

8.2 Data Register (Port x6h)

Data Port: Port x6h Power on Default Value 00h Attribute: Read/write Size: 8 bits

7 6 5 4 3 2 1 0

W83781D

PRELIMINARY

Data

Bit 7-0: Data to be read from or to be written to RAM and Register.

8.3 Configuration Register - Index 40h (Bank 0)

Register Location: 40h Power on Default Value 00000001 binary Attribute: Read/write Size: 8 bits

7 6 5 4 3 2 1 0

START EN_SMI# EN_IRQ INT_CLEAR RST_OUT# IRQPOL BEEP/GPO# INITIALIZATION

Bit 7:The logical 1 restores power on default value to all registers except the Serial Bus Address

register. This bit clears itself since the power on default is zero. Bit 6:The logical 1 in this bit drives a zero on GPO# pin. Bit 5:IRQ polarity select. When set to 0, IRQ active high. Set to 1, IRQ active low. Default 0. Bit 4:The logical 1 outputs at least a 20 ms active low reset signal at RST_OUT# if <7> = 1 in SMI#

Mask Register 2. This bit is cleared once the pulse has gone inactive.

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Revision 0.60

W83781D

PRELIMINARY

Bit 3:The logical 1 disables the SMI# and IRQ outputs without affecting the contents of Interrupt

Status Registers. The device will stop monitoring. It will resume upon clearing of this bit. Bit 2:The logical 1 enables the IRQ Interrupt output. Bit 1:The logical 1 enables the SMI# Interrupt output. Bit 0: 1 enables startup of monitoring operations

0 puts the part in standby mode.

Note: The outputs of Interrupt pins will not be cleared if the user writes a zero to this location after

an interrupt has occurred unlike "INT_CLEAR'' bit.

8.4

Interrupt Status Register 1 Index 41h (Bank 0)

Register Location: 41h Power on Default Value 00h Attribute: Read Only Size: 8 bits

7 6 5 4 3 2 1 0

IN0 IN1 IN2 IN3 TEMP1 TEMP23 FAN1 FAN2

Bit 7: The logical 1 indicates the fan count limit has been exceeded. Bit 6: The logical 1 indicates the fan count limit has been exceeded. Bit 5: The logical 1 indicates a High or Low limit has been exceeded from temperature sensor 2 or

sensor 3. The high and low limits value are defined in index registers: 53h-56h of the Bank 1. Bit 4: The logical 1 indicates a High or Low limit has been exceeded from temperature sensor 1. Bit 3-0: The logical 1 indicates a High or Low limit has been exceeded.

- 20 - Publication Release Date : Nov. 1997

Revision 0.60

8.5

Interrupt Status Register 2  Index 42h (Bank 0)

Register Location: 42h Power on Default Value 00h Attribute: Read Only Size: 8 bits

7 6 5 4 3 2 1 0

W83781D

PRELIMINARY

IN4

-IN5

-IN6 FAN3 Case Open Reserved Reserved Reserved

Bit 7-5:Reserved.This bit should be set to 0. Bit 4: The logical 1 indicates Case Open has gone high. Bit 3: The logical 1 indicates the fan count limit has been exceeded. Bit 2-0: The logical 1 indicates a High or Low limit has been exceeded.

8.6 SMI# Mask Register 1  Index 43h (Bank 0)

Register Location: 43h Power on Default Value 00h Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

IN0 IN1 IN2 IN3 TEMP1 TEMP23 FAN1 FAN2

Bit 7-0: The logical 1 disables the corresponding interrupt status bit for SMI# interrupt.

- 21 - Publication Release Date : Nov. 1997

Revision 0.60

8.7 SMI# Mask Register 2  Index 44h (Bank 0)

RST_OUT# Enable

Register Location: 44h Power on Default Value 00h Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

W83781D

PRELIMINARY

IN4

-IN5

-IN6 FAN3 Case Open Reserved Reserved

Bit 7: <7> = 1 in SMI# ask Register 2 enables the RST_OUT# in the Configuration Register. 13.8 IRQ

Mask Register 1Index 45h Bit 6-5: Reserved. This bit should be set to 0. Bit 4-0: The logical 1 disables the corresponding interrupt status bit for SMI# interrupt.

8.8

IRQ Mask Register 2  Index 45h (Bank 0)

Register Location: 45h Power on Default Value 00h Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

V25INA V25INB V33IN V5IN VTHIN1 VTHIN23 FAN1 FAN2

Bit 7-0: The logical 1 disables the corresponding interrupt status bit for IRQ interrupt.

- 22 - Publication Release Date : Nov. 1997

Revision 0.60

8.9

IRQ Mask Register 2  Index 46h (Bank 0)

Register Location: 46h Power on Default Value <7:0> = 01000000 binary Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

W83781D

PRELIMINARY

IN4

-IN5

-IN6 FAN3 Case Open Reserved Reserved Chassis Clear

Bit 7:The logical 1 outputs a minimum 20 ms active low pulse on the Case Open pin. The register bit self clears after the pulse has been output.

Bit 6-5:Reserved. This bit should be set to 0. Bit 4-0:The logical 1 disables the corresponding interrupt status bit for IRQ interrupt.

8.10 VID/Fan Divisor Register  Index 47h (Bank 0)

Register Location: 47h Power on Default Value <7:4> is 0101, <3:0> is 0000 Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

VID0 VID1 VID2 VID3 FAN1 RPM Control FAN1 RPM Control FAN2 RPM Control FAN2 RPM Control

- 23 - Publication Release Date : Nov. 1997

Revision 0.60

Bit 7-6: FAN2 Speed Control.

<7:6> = 00 - divide by 1; <7:6> = 01 - divide by 2; <7:6> = 10 - divide by 4; <7:6> = 11 - divide by 8.

Bit 5-4: FAN1 Speed Control.

<5:4> = 00 - divide by 1; <5:4> = 01 - divide by 2; <5:4> = 10 - divide by 4; <5:4> = 11 - divide by 8.

Bit 3-0: The VID <3:0> inputs

W83781D

PRELIMINARY

8.11 Serial Bus Address Register  Index 48h (Bank 0)

Register Location: 48h Power on Default Value Serial Bus address <6:0> = 0101101 and <7> = 0 binary Size: 8 bits

7 6 5 4 3 2 1 0

Serial Bus Address

Reserved

Bit 7: Read Only - Reserved. Bit 6-0: Read/Write - Serial Bus address <6:0>.

- 24 - Publication Release Date : Nov. 1997

Revision 0.60

W83781D

PRELIMINARY

8.12 Value RAM  Index 20h- 3Fh or 60h  Index 7Fh (auto-increment) (Bank 0)

Index A6-A0 Index A6-A0 with Auto-

Increment

20h 60h IN0 reading 21h 61h IN1 reading 22h 62h IN2 reading 23h 63h IN3 reading 24h 64h IN4 reading 25h 65h -IN5 reading 26h 66h -IN6 reading 27h 67h Temperature reading 28h 68h FAN1 reading

Note: This location stores the number of counts of the internal clock per revolution.

29h 69h FAN2 reading

Note: This location stores the number of counts of the internal clock per revolution.

2Ah 6Ah FAN3 reading

Note: This location stores the number of counts of the internal clock per revolution.

Description

2Bh 6Bh IN0 High Limit, default value is defined by Vcore

Voltage +0.2V.

2Ch 6Ch IN0 Low Limit, default value is defined by Vcore

Voltage -0.2V.

2Dh 6Dh IN1 High Limit, , default value is defined by Vcore

Voltage +0.2V.

2Eh 6Eh IN1 Low Limit, default value is defined by Vcore

Voltage -0.2V. 2Fh 6Fh IN2 High Limit 30h 70h IN2 Low Limit 31h 71h IN3 High Limit 32h 72h IN3 Low Limit 33h 73h IN4 High Limit 34h 74h IN4 Low Limit 35h 75h -IN5 High Limit 36h 76h -IN5 Low Limit 37h 77h -IN6 High Limit

- 25 - Publication Release Date : Nov. 1997

Revision 0.60

8.12 Value RAM  Index 20h- 3Fh or 60h  Index 7Fh (auto-increment) (Bank 0),continued

W83781D

PRELIMINARY

Index A6-A0 Index A6-A0 with Auto-

Increment

38h 78h -IN6 Low Limit 39h 79h Over Temperature Limit (High)

3Ah 7Ah Temperature Hysteresis Limit (Low) 3Bh 7Bh FAN1 Fan Count Limit

Note: It is the number of counts of the internal clock

for the Low Limit of the fan speed.

3Ch 7Ch FAN2 Fan Count Limit

Note: It is the number of counts of the internal clock

for the Low Limit of the fan speed.

3Dh 7Dh FAN3 Fan Count Limit

Note: It is the number of counts of the internal clock

for the Low Limit of the fan speed.

3E- 3Fh 7E- 7Fh Reserved

Setting all ones to the high limits for voltages and fans (0111 1111 binary for temperature) means interrupts will never be generated except the case when voltages go below the low limits.

Note1: For the high limits of the voltages, the device is doing a greater than comparison. For the low

limits, however, it is doing a less than or equal comparison.

Description

Note 2: V-Core Table:

Processor Pins

0 = Connected to Vss

1 = Open or pull-up to Vin

VID4 VID3 VID2 VID1 VID0 (VDC) VID4 VID3 VID2 VID1 VID0 (VDC)

0 1 1 1 1 * 1 1 1 1 1 No CPU 0 1 1 1 0 * 1 1 1 1 0 2.1 0 1 1 0 1 * 1 1 1 0 1 2.2 0 1 1 0 0 * 1 1 1 0 0 2.3 0 1 0 1 1 * 1 1 0 1 1 2.4 0 1 0 1 0 * 1 1 0 1 0 2.5 0 1 0 0 1 * 1 1 0 0 1 2.6 0 1 0 0 0 * 1 1 0 0 0 2.7 0 0 1 1 1 * 1 0 1 1 1 2.8

Vcore

- 26 - Publication Release Date : Nov. 1997

Processor Pins

0 = Connected to Vss

1 = Open or pull-up to Vin

Vcore

Revision 0.60

Note 2: V-Core Table, continued

W83781D

PRELIMINARY

Processor Pins

Vcore

0 = Connected to Vss

1 = Open or pull-up to Vin

VID4 VID3 VID2 VID1 VID0 (VDC) VID4 VID3 VID2 VID1 VID0 (VDC)

0 0 1 1 0 * 1 0 1 1 0 2.9 0 0 1 0 1 1.80 1 0 1 0 1 3.0 0 0 1 0 0 1.85 1 0 1 0 0 3.1 0 0 0 1 1 1.90 1 0 0 1 1 3.2 0 0 0 1 0 1.95 1 0 0 1 0 3.3 0 0 0 0 1 2.00 1 0 0 0 1 3.4 0 0 0 0 0 2.05 1 0 0 0 0 3.5

Processor Pins

0 = Connected to Vss

1 = Open or pull-up to Vin

Vcore

8.13 Voltage ID (VID7-4) – Index 49h (Bank 0)

Register Location: 49h Power on Default Value <7:1> is 000,0001b

<0> is mapped to VID <4>

Size: 8 bits

7 6 5 4 3 2 1 0

Bit 7-1: Read Only - Device ID<6:0> Bit 0: Read/Write - The VID4 inputs/outputs. Reset by MR.

- 27 - Publication Release Date : Nov. 1997

VID4

DID<6:0>

Revision 0.60

W83781D

OS

PRELIMINARY

8.14 Temperature 2 and Temperature 3 Serial Bus Address Register Index 4Ah (Bank 0)

Register Location: 4Ah Power on Default Value <7:0> = 0000,0001 binary. Reset by MR Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

I2CADDR2 I2CADDR2 I2CADDR2 DIS_T2 I2CADDR3 I2CADDR3 I2CADDR3 DIS_T3

Bit 7: Set to 1, disable temperature sensor 3 and can not access any data from Temperature Sensor 3. Bit 6-4: Temperature 3 Serial Bus Address. The serial bus address is 1001xxx. Where xxx are defined in

these bits. Bit 3: Set to 1, disable temperature Sensor 2 and can not access any data from Temperature Sensor 2. Bit 2-0: Temperature 2 Serial Bus Address. The serial bus address is 1001xxx. Where xxx are defined in

these bits.

Register

SCL

SDA

Data

Interface

Address

Pointer

(Select Register)

Temperature

(Read Only)

Configuration

T

HYST

T

- 28 - Publication Release Date : Nov. 1997

Revision 0.60

(Select which register will be read from or written to):

P7 P6 P5 P4 P3 P2 P1 P0

P7-P2: Must be kept 0. P1-P0: Register select:

P1 P0 Index Register Selection (Bank1 & Bank2)

0 0 Temperature (Read only) (Power up default) CR50h & CR51h 0 1 Configuration (Read / Write) CR52h

W83781D

PRELIMINARY

1 0 T 1 1 T

(Read / Write) CR53h & CR54h

HYST

(Read / Write) CR55h & CR56h

OS

8.15 Pin Control Register  Index 4Bh (Bank 0)

Register Location: 4Bh Power on Default Value <7:0> 44h. Reset by MR. Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

Reserved Reserved CLKINSEL CLKINSEL ADCOVSEL ADCOVSEL FAN3_DIV FAN3_DIV

Bit 7-6:Fan3 speed divisor.

<1:0> = 00 - divide by 1;<1:0> = 01 - divide by 2; <1:0> = 10 - divide by 4;<1:0> = 11 - divide by 8;Reset by MR.

Bit 5-4: Select A/D Converter Clock Input.

<5:4> = 00 - default.

<5:4> = 01- divided by 4.

<5:4> = 10 - divided by 16.

<5:4> = 11 - divided by 64.

- 29 - Publication Release Date : Nov. 1997

Revision 0.60

Bit 3-2: Clock Input Select.

<3:2> = 00 - Pin 3 (CLKIN) select 14.318M Hz clock.

<3:2> = 01 - Default. Pin 3 (CLKIN) select 24M Hz clock.

<3:2> = 10 - Pin 3 (CLKIN) select 48M Hz clock .

<3:2> = 11 - Reserved. Pin3 no clock input. Bit 1-0: Reserved. User defined.

8.16

IRQ/OVT# Property Select  Index 4Ch (Bank 0)

Register Location: 4Ch Power on Default Value <7:0> ---0,0001. Reset by MR. Attribute: Read/Write Size: 8 bits

W83781D

PRELIMINARY

7 6 5 4 3 2 1 0

Reserved IRQEDGE OVTPOL DIS_OVT1 DIS_OVT2 Reserved Reserved Reserved

Bit 7-5: Reserved. User Defined. Bit 4: Disable temperature sensor 3 over-temperature (OVT) output if set to 1. Default 0, enable

OVT2 output through pin OVT#. Bit 3: Disable temperature sensor 2 over-temperature (OVT) output if set to 1. Default 0, enable

OVT1 output through pin OVT#. Bit 2: Over-temperature polarity. Write 1, OVT# active high. Write 0, OVT# active low. Default 0. Bit 1: When set to 1, IRQ Edge Active. Set to 0, IRQ Level trigger. Default 0, level trigger interrupt. Bit 0: Reserved. User Defined.

- 30 - Publication Release Date : Nov. 1997

Revision 0.60

W83781D

PRELIMINARY

8.17

FAN IN/OUT and BEEP/GPO# Control Register -- Index 4Dh (Bank 0)

Register Location: 4Dh Power on Default Value <7:0> 0001,0101. Reset by MR. Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

FANINC1 FANOPV1 FANINC2 FANOPV2 FANINC3 FANOPV3 GPOSEL DIS_ABN

Bit 7: Disable power-on abnormal the monitor voltage including V-Core A,, and +3.3V. If these

voltage exceed the limit value, the pin (Open Drain) of BEEP will drives low and high frequency signal. Write 1, the frequency will be disable. Default 0. After power on, the system should set this bit to 1 in order to disable BEEP.

Bit 6: BEEP/GPO# Pin Function Select. Write 1 Select GPO# function. Set 0, select BEEP function.

This bit default 0.

Bit 5: FAN 3 output value if FANINC3 sets to 0. Write 1, then pin 18 always generate logic high

signal. Write 0, pin 18 always generates logic low signal. This bit default 0.

Bit 4: FAN 3 Input Control. Set to 1, pin 18 acts as FAN clock input, which is default value. Set to 0,

this pin 18 acts as FAN control signal and the output value of FAN control is set by this register bit 5. This output pin can connect to power PMOS gate to control FAN ON/OFF.

Bit 3: FAN 2 output value if FANINC2 sets to 0. Write 1, then pin 19 always generate logic high

signal. Write 0, pin 19 always generates logic low signal. This bit default 0.

Bit 2: FAN 2 Input Control. Set to 1, pin 19 acts as FAN clock input, which is default value. Set to 0,

this pin 19 acts as FAN control signal and the output value of FAN control is set by this register bit 3. This output pin can connect to power NMOS gate to control FAN ON/OFF.

Bit 1: FAN 1 output value if FANINC1 sets to 0. Write 1, then pin 20 always generate logic high

signal. Write 0, pin 20 always generates logic low signal. This bit default 0.

Bit 0: FAN 1 Input Control. Set to 1, pin 20 acts as FAN clock input, which is default value. Set to 0,

this pin 20 acts as FAN control signal and the output value of FAN control is set by this register bit 1. This output pin can connect to power PMOS gate to control FAN ON/OFF.

- 31 - Publication Release Date : Nov. 1997

Revision 0.60

8.18 Register 50h ~ 5Fh Bank Select -- Index 4Eh (No Auto Increase) (Bank 0)

Register Location: 4Eh Power on Default Value <6:3> = Reserved, <7> = 1, <2:0> = 0. Reset by MR Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

BANKSEL0 BANKSEL1 BANKSEL2 Reserved Reserved Reserved Reserved HBACS

Bit 7: HBACS- High byte access. Set to 1, access Register 4Fh high byte register.

W83781D

PRELIMINARY

Set to 0, access Register 4Fh low byte register. Default 1. Bit 6-3: Reserved. This bit should be set to 0. Bit 2-0: Index ports 0x50~0x5F Bank select.

8.19

Winbond Vendor ID -- Index 4Fh (No Auto Increase) (Bank 0)

Register Location: 4Fh Power on Default Value <15:0> = 5CA3h Attribute: Read Only Size: 16 bits

15 8 7 0

VIDH

VIDL

Bit 15-8: Vendor ID High Byte if CR4E.bit7=1.Default 5Ch. Bit 7-0: Vendor ID Low Byte if CR4E.bit7=0. Default A3h.

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W83781D

PRELIMINARY

8.20 Resistor-Temperature Table Register  Index 50h - 51h (Bank 0)

Note: Index will be auto-increased when read Data Port 0x6, and Index will stop at 0x5F if continue reading Data Port. Any no defined register is read will return 0xFF.

A6-A0 Name Read/Write Description

50h RT_IDX Read/Write R-T Table index port, which is mapped to data port

51h. The default value is 0x00.

51h RT_DATA Read/Write R-T Table data port, which is selected by RT_IDX.

8.21 Winbond Test Register 1  Index 52h (Bank 0)

8.22 Winbond Test Register 2  Index 53h (Bank 0)

8.23 Winbond Test Register 3  Index 54h (Bank 0)

8.24 Winbond Test Register 4  Index 55h (Bank 0)

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W83781D

PRELIMINARY

8.25

BEEP Control Register 1 Index 56h (Bank 0) (Auto-increment)

Register Location: 56h Power on Default Value <7:0> 0000,0000. Reset by MR. Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

EN_V25A_BP EN_V25B_BP EN_V33_BP EN_V5_BP EN_T1_BP EN_T23_BP EN_FAN1_BP EN_FAN2_BP

Bit 7: Enable BEEP Output from FAN 2 if the monitor value exceed the limit value. Write 1, enable

BEEP output. Default value is 0. Bit 6: Enable BEEP Output from FAN 1 if the monitor value exceed the limit value. Write 1, enable

BEEP output. Default value is 0. Bit 5: Enable BEEP Output from Temperature Sensor 2 and 3 if the monitor value exceed the limit

value. Write 1, enable BEEP output. Default value is 0. Bit 4: Enable BEEP output for Temperature Sensor 1 if the monitor value exceed the limit value.

Write 1, enable BEEP output. Default value is 0. Bit 3: Enable BEEP output from VDD (5V), Write 1, enable BEEP output if the monitor value exceed

the limits value. Default 0, that is disable BEEP output. Bit 2: Enable BEEP output from 3.3V. Write 1, enable BEEP output. Default value is 0. Bit 1: Enable BEEP output from V-Core B. Write 1, enable BEEP output. Default value is 0. Bit 0: Enable BEEP Output from V-Core A if the monitor value exceed the limits value. Write 1,

enable BEEP output. Default value is 0.

8.26 BEEP Control Register 2— Index 57h (Bank 0) ( No Auto-increment)

Register Location: 57h Power on Default Value <7:0> 1000-0000. Reset by MR. Attribute: Read/Write Size: 8 bits

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PRELIMINARY

7 6 5 4 3 2 1 0

EN_V12_BP EN_NV12_BP EN_NV5_BP EN_FAN3_BP EN_CASO_BP Reserved Reserved EN_GBP

Bit 7: Enable Global BEEP. Write 1, enable global BEEP output. Default 1. Write 0, disable all BEEP

output. Bit 6-5: Reserved. This bit should be set to 0. Bit 4: Enable BEEP output for case open if the monitor value exceed the limit value. Write 1, enable

BEEP output. Default 0. Bit 3: Enable BEEP Output from FAN 3 if the monitor value exceed the limit value. Write 1, enable

BEEP output. Default 0. Bit 2: Enable BEEP output from -5V, Write 1, enable BEEP output if the monitor value exceed the

limits value. Default 0, that is disable BEEP output. Bit 1: Enable BEEP output from -12V, Write 1, enable BEEP output if the monitor value exceed the

limits value. Default 0, that is disable BEEP output. Bit 0: Enable BEEP output from +12V, Write 1, enable BEEP output if the monitor value exceed the

limits value. Default 0, that is disable BEEP output.

8.27

Chip ID- Index 58h (Bank 0)

Register Location: 58h Power on Default Value <7:0> 0001-0000. Reset by MR. Attribute: Read Only Size: 8 bits

7 6 5 4 3 2 1 0

CHIPID

Bit 7: Winbond Chip ID number. Read this register will return 10h.

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8.28 Temperature Sensor 2 Temperature Register - Index 50h (Bank 1)

Register Location: 50h Attribute: Read Only Size: 8 bits

7 6 5 4 3 2 1 0

TEMP2<8:1>

Bit 7: Temperature <8:1> of sensor 2, which is high byte.

W83781D

PRELIMINARY

8.29

Temperature Sensor 2 Temperature Register - Index 51h (Bank 1)

Register Location: 51h Attribute: Read Only Size: 8 bits

7 6 5 4 3 2 1 0

Reserved

TEMP2<0>

Bit 7: Temperature <0> of sensor2, which is low byte. Bit 6-0: Reserved. This bit should be set to 0.

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8.30

Temperature Sensor 2 Configuration Register - Index 52h (Bank 1)

Register Location: 52h Power on Default Value <7:0> = 0x00 Size: 8 bits

7 6 5 4 3 2 1 0

STOP2 INTMOD Reserved FAULT FAULT Reserved Reserved Reserved

Bit 7-5: Read - Reserved. This bit should be set to 0.

W83781D

PRELIMINARY

Bit 4-3: Read/Write - Number of faults to detect before setting OVT# output to avoid false tripping due to noise.

Bit 2: Read - Reserved. This bit should be set to 0. Bit 1: Read/Write - Interrupt mode select. This bit default is set to 0, which is compared mode. When

set to 1, interrupt mode will be selected. Bit 0: Read/Write - When set to 1 the sensor will stop monitor.

8.31

Temperature Sensor 2 Hysteresis (High Byte) Register - Index 53h (Bank 1)

Register Location: 53h Power on Default Value <7:0> = 0x4B Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

THYST2<8:1>

Bit 7-0: Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C.

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8.32

Temperature Sensor 2 Hysteresis (Low Byte) Register - Index54h (Bank 1)

Register Location: 54h Power on Default Value <7:0> = 0x0 Attribute: Read Only Size: 8 bits

7 6 5 4 3 2 1 0

Reserved

THYST2<0>

W83781D

PRELIMINARY

Bit 7: Temperature hysteresis bit 0, which is low Byte. Bit 6-0: Reserved. This bit should be set to 0.

8.33

Temperature Sensor 2 Over-temperature(High Byte) Register - Index 55h (Bank 1)

Register Location: 55h Power on Default Value <7:0> = 0x50 Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

TOVF2<8:1>

Bit 7-0: Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C.

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8.34

Temperature Sensor 2 Over-temperature (Low Byte) Register - Index 56h (Bank 1)

Register Location: 56h Power on Default Value <7:0> = 0x0 Size: 8 bits

7 6 5 4 3 2 1 0

Reserved

TOVF2<0>

Bit 7: Read/Write - Over-temperature bit 0, which is low Byte. Bit 6-0: Read Only - Reserved. This bit should be set to 0.

W83781D

PRELIMINARY

8.35

Temperature Sensor 3 Temperature Register - Index 50h (Bank 2)

Register Location: 50h Attribute: Read Only Size: 8 bits

7 6 5 4 3 2 1 0

TEMP2<8:1>

Bit 7-0: Temperature <8:1> of sensor 2, which is high byte.

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8.36 Temperature Sensor 3 Temperature Register - Index 51h (Bank 2)

Register Location: 51h Attribute: Read Only Size: 8 bits

7 6 5 4 3 2 1 0

Reserved

TEMP2<0>

Bit 7: Temperature <0> of sensor2, which is low byte. Bit 6-0: Reserved. This bit should be set to 0.

W83781D

PRELIMINARY

8.37

Temperature Sensor 3 Configuration Register - Index 52h (Bank 2)

Register Location: 52h Power on Default Value <7:0> = 0x00 Size: 8 bits

7 6 5 4 3 2 1 0

STOP3 INTMOD Reserved FAULT FAULT Reserved Reserved Reserved

Bit 7-5: Read - Reserved. This bit should be set to 0. Bit 4-3: Read/Write - Number of faults to detect before setting OVF# output to avoid false tripping

due to noise. Bit 2: Read - Reserved. This bit should be set to 0. Bit 1: Read/Write - Interrupt Mode select. This bit default is set to 0, which is Compared Mode. When

set to 1, Interrupt Mode will be selected. Bit 0: Read/Write - When set to 1 the sensor will stop monitor.

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W83781D

PRELIMINARY

8.38

Temperature Sensor 3 Hysteresis (High Byte) Register - Index 53h (Bank 2)

Register Location: 53h Power on Default Value <7:0> = 0x4B Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

THYST3<8:1>

Bit 7-0: Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C.

8.39

Temperature Sensor 3 Hysteresis (Low Byte) Register - Index 54h (Bank 2)

Register Location: 54h Power on Default Value <7:0> = 0x0 Attribute: Read Only Size: 8 bits

7 6 5 4 3 2 1 0

Reserved

THYST3<0>

Bit 7: Temperature hysteresis bit 0, which is low Byte. Bit 6-0: Reserved. This bit should be set to 0.

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8.40

Temperature Sensor 3 Over-temperature (High Byte)Register - Index 55h (Bank 2)

Register Location: 55h Power on Default Value <7:0> = 0x50 Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

TOVF3<8:1>

Bit 7-0: Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C.

W83781D

PRELIMINARY

8.41 Temperature Sensor 3 Over-temperature (Low Byte) Register - Index 56h (Bank 2)

Register Location: 56h Power on Default Value <7:0> = 0x0 Size: 8 bits

7 6 5 4 3 2 1 0

Reserved

TOVF3<0>

Bit 7: Read/Write - Over-temperature bit 0, which is low Byte. Bit 6-0: Read Only - Reserved. This bit should be set to 0.

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9. SPECIFICATIONS

12ts

9.1 Absolute Maximum Ratings

PARAMETER RATING UNIT

Power Supply Voltage -0.5 to 7.0 V Input Voltage -0.5 to VDD+0.5 V

W83781D

PRELIMINARY

Operating Temperature 0 to +70 Storage Temperature -55 to +150

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

° C ° C

9.2 DC Characteristics

(Ta = 0° C to 70° C, VDD = 5V ± 10%, VSS = 0V)

PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS

I/O

- TTL level bi-directional pin with source-sink capability of 12 mA

12t

Input Low Voltage VIL 0.8 V Input High Voltage VIH 2.0 V Output Low Voltage VOL 0.4 V IOL = 12 mA Output High Voltage VOH 2.4 V IOH = - 12 mA Input High Leakage ILIH +10 Input Low Leakage ILIL -10

I/O

- TTL level bi-directional pin with source-sink capability of 12 mA and schmitt-trigger level

µA µA

input

VIN = VDD VIN = 0V

Input Low Threshold Voltage Vt- 0.5 0.8 1.1 V VDD = 5 V Input High Threshold Voltage Vt+ 1.6 2.0 2.4 V VDD = 5 V Hysteresis VTH 0.5 1.2 V VDD = 5 V Output Low Voltage VOL 0.4 V IOL = 12 mA Output High Voltage VOH 2.4 V IOH = - 12 mA Input High Leakage ILIH +10 Input Low Leakage ILIL -10

OUT

- TTL level output pin with source-sink capability of 12 mA

12t

µA µA

VIN = VDD VIN = 0V

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9.2 DC Characteristics, continued

PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS

Output Low Voltage VOL 0.4 V IOL = 12 mA Output High Voltage VOH 2.4 V IOH = -12 mA

OD8 - Open-drain output pin with sink capability of 8 mA

Output Low Voltage VOL 0.4 V IOL = 8 mA

OD12 - Open-drain output pin with sink capability of 12 mA

Output Low Voltage VOL 0.4 V IOL = 12 mA

OD48 - Open-drain output pin with sink capability of 48 mA

Output Low Voltage VOL 0.4 V IOL = 48 mA

INt - TTL level input pin

Input Low Voltage VIL 0.8 V

W83781D

PRELIMINARY

Input High Voltage VIH 2.0 V Input High Leakage ILIH +10 Input Low Leakage ILIL -10

9.2 DC Characteristics, continued

PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS

IN

ts

Input Low Threshold Voltage Vt- 0.5 0.8 1.1 V VDD = 5 V Input High Threshold Voltage Vt+ 1.6 2.0 2.4 V VDD = 5 V Hysteresis VTH 0.5 1.2 V VDD = 5 V Input High Leakage ILIH +10 Input Low Leakage ILIL -10

- TTL level Schmitt-triggered input pin

µA µA

VIN = VDD VIN = 0 V

µA µA

VIN = VDD VIN = 0 V

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9.2.1 AC Characteristics

9.2.2 ISA Read/Write Interface Timing

AEN

SA[2:0],CS#

t

AR

W83781D

PRELIMINARY

t

RD

t

RCU

IOR#

IOW#

SD[7:0]

IRQ

AEN

SA[2:0],CS#

IOW#

IOR#

t

AW

t

RA

RC

t

RVD

VALID DATA

ISA Bus Read Timing

t

RDH

t

RI

VALID VALID

t

WR

t

WA

WC

t

WCU

SD[7:0]

IRQ

VALID DATA

t

DS

ISA Bus Write Timing

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t

DH

t

WI

Revision 0.60

W83781D

PRELIMINARY

ISA Read/Write Timing

PARAMETER SYMBOL MIN. MAX. UNIT

Valid Address to Read Active Valid Address to Write Active t Data Hold t Data Setup t Address Hold from Inactive Read t Read Cycle Update t Read Strobe Width t Read Data Hold t Read Strobe to Clear IRQ t Active Read to Valid Data t Address Hold from Inactive Write t Write Cycle Update t Write Strobe to Clear IRQ t Write Strobe Width t Read Cycle = t Write Cycle = tAW+tWR - t

+ tRD+t

AR

RCV

WCV

-

t

AR

AW

DH

DS

RA

RCU

RD

RDH

RI

RVD

WA

WCU

WI

WR

10 nS 10 nS

5 nS 80 nS 40 nS

200 nS 120 nS

40 nS

60 nS

115 nS

5 nS 80 nS

60 nS

120 nS

RC 210 nS

WC 210 nS

9.2.3 Serial Bus Timing Diagram

SCL

t

HD;SDA

SDA IN

SDA OUT

t

SCL

t

HD;DAT

VALID DATA

t

SU;DAT

Serial Bus Timing Diagram

t

SU;STO

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PRELIMINARY

Serial Bus Timing

PARAMETER SYMBOL MIN. MAX. UNIT

SCL clock period Start condition hold time t Stop condition setup-up time t DATA to SCL setup time t DATA to SCL hold time t SCL and SDA rise time t SCL and SDA fall time t

10. HOW TO READ THE TOP MARKING

-

t

SCL

HD;SDA

SU;STO

SU;DAT

HD;DAT

R

F

10 uS

4.7 uS

120 nS

5 nS

1.0 uS

300 nS

The top marking of W83781D

W83781D

745AA

Left: Winbond logo

1st line: Type number W83781D, D means LQFP (Thickness = 1.4 mm).

2nd line: Tracking code 745 A A

745: packages made in '97, week 45 A: assembly house ID; A means ASE, O means OSE A: IC revision; A means version A, B means version B

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11. PACKAGE DIMENTIONS

(48-pin QFP)

H

D

25

12

b

y

37

48

Seating Plane

36

1

e

See Detail F

W83781D

PRELIMINARY

Dimension in inch Dimension in mm

Symbol

Min. Nom. Max. Max.Nom.Min.

A

1

24

A

2

A b

E

H

13

c D E

e

D

H H

E

L

1

L y

0

c

A

2

A

1

A

L

1

Detail F

Notes:

1. Dimensions D & E do not include interlead flash.

2. Dimension b does not include dambar protrusion/intrusion.

3. Controlling dimension: Millimeters

4. General appearance spec. should be based on final visual inspection spec.

---

0.05

1.35

0.17 0.27

0.09

0.45

--- ---

0

---

1.40

0.20

---

7.00

0.50

9.00

0.60

1.00

0.08

3.5 7

1.60

0.15

1.45

0.20

0.75

Headquarters

No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064

Winbond Electronics (North America) Corp.

2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE

Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their

respective owners.

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