Datasheet W83195BR-S Datasheet (Winbond Electronics)

W83195BR-S

STEPLESS 200MHZ 3-DIMM CLOCK FOR SOLANO CHIPSET

1.0 GENERAL DESCRIPTION

The W83195BR-S is a Clock Synthesizer for Intel 815 Solano chipset. W83195BR-S provides all clocks required for high-speed RISC or CISC microprocessor and also provides 64 different frequencies of CPU, SDRAM, PCI, 3V66, IOAPIC clocks frequency setting. All clocks are externally selectable with smooth transitions.

The W83195BR-S provides I2C serial bus interface to program the registers to enable or disable each clock outputs and provides 0.25% and 0.5% center type spread spectrum to reduce EMI. A watch dog timer is quipped and when time out, the RESET# pin will output 4ms pulse signal.

The W83195BR-S provides stepless frequency programming by controlling the VCO freq. and the clock output divisor ratio. Also the skew of CPU, SDRAM and 3V66 clock outputs are programmable.

The W83195BR-S accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50± 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide better than 0.5V /ns slew rate.

2.0 PRODUCT FEATURES

• 2 CPU clocks

• 3 3V66 for chipset and AGP clocks

• 12 SDRAM clocks for 3 DIMMs

• 8 PCI synchronous clocks.

• Optional single or mixed supply:

(VddR = VddP=VddS = Vdd48 = Vdd3 = 3.3V, VddLAPIC=VddLCPU=2.5V)

• Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns

• Smooth frequency switch with selections from 66.8 to 200 MHz

• I2C 2-Wire serial interface and I2C read back

• 0.25% and 0.5% center type spread spectrum

• Programmable registers to enable/stop each output and select modes

(mode as Tri-state or Normal )

• Two 48 MHz pins for USB

• 24 MHz for super I/O

• 56-pin SSOP package

Publication Release Date: June 2000

- 1 - Revision 0.42

3.0 PIN CONFIGURATION

W83195BR-S

PRELIMINARY

Vss

Vdd3

REF2X/ *FS3

PCICLK0^/ *FS0

PCICLK1^/ *FS1 PCICLK2^/*FS2

PCICLK3^/Mode1*

48MHz_1/ FS4*

SIO_SEL*/24_48MHz

*: interanl pull-up #:active low input ^:1.5X~2X strength $: open drain

Xin

Xout

Vdd3

3V66-0

3V66-1

3V66-2

Vss3

VssP

PCICLK4^

Vdd3

PCICLK5^

PCICLK6^

PCICLK7

Vss48

48MHz_0

Vdd3

*SDATA

VssS Vdd3

16

26

1 2 3 4

6 7

9 10 11 12

13 14 15

17 18 19 20 21 22

24

25

27

5

8

23

28

56

33

32 31 30

29

55 54 53

52 51 50

49 48 47

46 45 44 43 42 41 40 39 38 37 36 35 34

Vdd2

IOAPIC

Vss VddLCPU CPUCLK0

CPUCLK1

VssC SDRAM 0 SDRAM 1 SDRAM 2 Vdd3 VssS

SDRAM 3

SDRAM 4 SDRAM 5

SDRAM 6

Vdd3

VssS

SDRAM 7

SDRAM 8

SDRAM 9 SDRAM 10

Vdd3

VssS SDRAM 11

SDRAM 12

PD#/RESET$

*SDCLK

Publication Release Date: June 2000

- 2 - Revision 0.42

4.0 FREQUENCY SELECTION BY HARDWARE

W83195BR-S

PRELIMINARY

FS4 FS3 FS2 FS1 FS0

0 0 0 0 0 75.30 112.95 75.30 37.65 18.83 0 0 0 0 1 95.00 95.00 63.33 31.67 15.83 0 0 0 1 0 129.00 129.00 86.00 43.00 21.50 0 0 0 1 1 150.00 113.00 75.33 37.67 18.83 0 0 1 0 0 150.00 150.00 75.00 37.50 18.75 0 0 1 0 1 110.00 110.00 73.33 36.67 18.33 0 0 1 1 0 140.00 140.00 70.00 35.00 17.50 0 0 1 1 1 144.00 108.00 72.00 36.00 18.00 0 1 0 0 0 68.30 102.45 68.30 34.15 17.08 0 1 0 0 1 105.00 105.00 70.00 35.00 17.50 0 1 0 1 0 138.00 138.00 69.00 34.50 17.25 0 1 0 1 1 140.00 105.00 70.00 35.00 17.50 0 1 1 0 0 66.80 100.20 66.80 33.40 16.70 0 1 1 0 1 100.20 100.20 66.80 33.40 16.70 0 1 1 1 0 133.60 133.60 66.80 33.40 16.70 0 1 1 1 1 133.60 100.20 66.80 33.40 16.70 1 0 0 0 0 157.30 118.00 78.67 39.33 19.67 1 0 0 0 1 160.00 120.00 80.00 40.00 20.00 1 0 0 1 0 146.00 110.00 73.33 36.67 18.33 1 0 0 1 1 122.00 91.50 61.00 30.50 15.25 1 0 1 0 0 127.00 127.00 84.67 42.33 21.17 1 0 1 0 1 122.00 122.00 81.33 40.67 20.33 1 0 1 1 0 117.00 117.00 78.00 39.00 19.50 1 0 1 1 1 114.00 114.00 76.00 38.00 19.00 1 1 0 0 0 80.00 120.00 80.00 40.00 20.00 1 1 0 0 1 78.00 117.00 78.00 39.00 19.50 1 1 0 1 0 166.00 166.00 83.00 41.50 20.75 1 1 0 1 1 160.00 160.00 80.00 40.00 20.00 1 1 1 0 0 66.60 100.00 66.67 33.33 16.67 1 1 1 0 1 100.00 100.00 66.67 33.33 16.67 1 1 1 1 0 133.30 133.30 66.65 33.33 16.66 1 1 1 1 1 133.30 100.00 66.67 33.33 16.67

CPU(MHz)

SDRAM

(MHz)

3V66(MHz) PCI(MHz) IOAPIC (MHz)

Publication Release Date: June 2000

- 3 - Revision 0.42

W83195BR-S

PRELIMINARY

5.0 SERIAL CONTROL 0REGISTERS

The Pin column lists the affected pin number and the @PowerUp column gives the state at true power up. Registers are set to the values shown only on true power up. "Command Code" byte and "Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge.

After that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and

acknowledged.

Frequency Table Setting by I2C (SEL5 ~ SEL0)

SSEL5 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0

0 0 0 0 0 0 75.30 112.95 75.30 37.65 18.83 0 0 0 0 0 1 95.00 95.00 63.33 31.67 15.83 0 0 0 0 1 0 129.00 0 0 0 0 1 1 150.00 0 0 0 1 0 0 150.00 0 0 0 1 0 1 110.00 0 0 0 1 1 0 140.00 0 0 0 1 1 1 144.00 0 0 1 0 0 0 68.30 102.45 68.30 34.15 17.08 0 0 1 0 0 1 105.00 0 0 1 0 1 0 138.00 0 0 1 0 1 1 140.00 0 0 1 1 0 0 66.80 100.20 66.80 33.40 16.70 0 0 1 1 0 1 100.20 0 0 1 1 1 0 133.60 0 0 1 1 1 1 133.60 0 1 0 0 0 0 157.30 0 1 0 0 0 1 160.00 0 1 0 0 1 0 146.00 0 1 0 0 1 1 122.00 0 1 0 1 0 0 127.00 0 1 0 1 0 1 122.00 0 1 0 1 1 0 117.00 0 1 0 1 1 1 114.00 0 1 1 0 0 0 80.00 120.00 80.00 40.00 20.00 0 1 1 0 0 1 78.00 117.00 78.00 39.00 19.50 0 1 1 0 1 0 166.00 0 1 1 0 1 1 160.00

CPU

(MHz)

- 4 - Revision 0.42

SDRAM

(MHz)

129.00 86.00 43.00 21.50

113.00 75.33 37.67 18.83

150.00 75.00 37.50 18.75

110.00 73.33 36.67 18.33

140.00 70.00 35.00 17.50

108.00 72.00 36.00 18.00

105.00 70.00 35.00 17.50

138.00 69.00 34.50 17.25

105.00 70.00 35.00 17.50

100.20 66.80 33.40 16.70

133.60 66.80 33.40 16.70

100.20 66.80 33.40 16.70

118.00 78.67 39.33 19.67

120.00 80.00 40.00 20.00

110.00 73.33 36.67 18.33

91.50 61.00 30.50 15.25

127.00 84.67 42.33 21.17

122.00 81.33 40.67 20.33

117.00 78.00 39.00 19.50

114.00 76.00 38.00 19.00

166.00 83.00 41.50 20.75

160.00 80.00 40.00 20.00

3V66

(MHz)

Publication Release Date: June 2000

PCI(MHz)

IOAPIC

(MHz)

0 1 1 1 0 0 66.60 100.00 66.67 33.33 16.67 0 1 1 1 0 1 100.00 0 1 1 1 1 0 133.30 0 1 1 1 1 1 133.30

SSEL5 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0

1 0 0 0 0 0 136.00 1 0 0 0 0 1 138.00 1 0 0 0 1 0 139.00 1 0 0 0 1 1 141.00 1 0 0 1 0 0 142.00 1 0 0 1 0 1 142.00 1 0 0 1 1 0 143.00 1 0 0 1 1 1 143.00 1 0 1 0 0 0 144.00 1 0 1 0 0 1 144.00 1 0 1 0 1 0 146.00 1 0 1 0 1 1 146.00 1 0 1 1 0 0 147.00 1 0 1 1 0 1 147.00 1 0 1 1 1 0 148.00 1 0 1 1 1 1 148.00 1 1 0 0 0 0 149.00 1 1 0 0 0 1 152.00 1 1 0 0 1 0 153.00 1 1 0 0 1 1 156.00 1 1 0 1 0 0 157.00 1 1 0 1 0 1 158.00 1 1 0 1 1 0 159.00 1 1 0 1 1 1 160.00 1 1 1 0 0 0 162.00 1 1 1 0 0 1 164.00 1 1 1 0 1 0 170.00 1 1 1 0 1 1 175.00 1 1 1 1 0 0 180.00 1 1 1 1 0 1 185.00 1 1 1 1 1 0 190.00 1 1 1 1 1 1 200.40

W83195BR-S

PRELIMINARY

100.00 66.67 33.33 16.67

133.30 66.65 33.33 16.66

100.00 66.67 33.33 16.67

CPU

(MHz)

- 5 - Revision 0.42

SDRAM

(MHz)

102.00 68.00 34.00 17.00

138.00 69.00 34.50 17.25

104.25 69.50 34.75 17.38

105.75 70.50 35.25 17.63

142.00 71.00 35.50 17.75

106.50 71.00 35.50 17.75

143.00 71.50 35.75 17.88

107.25 71.50 35.75 17.88

144.00 72.00 36.00 18.00

108.00 72.00 36.00 18.00

146.00 73.00 36.50 18.25

109.50 73.00 36.50 18.25

147.00 73.50 36.75 18.38

110.25 73.50 36.75 18.38

148.00 74.00 37.00 18.50

111.00 74.00 37.00 18.50

111.75 74.50 37.25 18.63

152.00 76.00 38.00 19.00

114.75 76.50 38.25 19.13

156.00 78.00 39.00 19.50

117.75 78.50 39.25 19.63

158.00 79.00 39.50 19.75

119.25 79.50 39.75 19.88

160.00 80.00 40.00 20.00

121.50 81.00 40.50 20.25

123.00 82.00 41.00 20.50

127.50 85.00 42.50 21.25

116.67 77.78 38.89 19.44

120.00 80.00 40.00 20.00

185.00 61.67 30.83 15.42

126.67 63.33 31.67 15.83

133.60 66.80 33.40 16.70

3V66

(MHz)

Publication Release Date: June 2000

PCI(MHz)

IOAPIC

(MHz)

5.1 Register 0: Control Register

W83195BR-S

PRELIMINARY

Bit @PowerUp

7 6 5

4 X - FS3# 3 X - FS4# 2 1 -

1 0 -

0 1 - 1=CENTER SPREAD 0=DOWN SPREAD

X - FS0# X - FS1# X - FS2#

Pin Description

If Reg0-bit7=1 0 = ± 0.5% Center type Spread Spectrum Modulation 1 = ± 0.25% Center type Spread Spectrum Modulation If Reg0-bit7=0 0 = 0 ~ - 1 % Down type Spread Spectrum Modulation

1 = 0 ~ - 0.5% Down type Spread Spectrum Modulation 0 = Normal

1 = Spread Spectrum enabled

5.2 Register 1 : SDRAM Register (1 = Active, 0 = Inactive)

Bit @PowerUp Pin

7 1 38 SDRAM7 (Active / Inactive) 6 1 41 SDRAM6 (Active / Inactive) 5 1 42 SDRAM5 (Active / Inactive) 4 1 43 SDRAM4 (Active / Inactive) 3 1 44 SDRAM3 (Active / Inactive) 2 1 47 SDRAM2 (Active / Inactive) 1 1 48 SDRAM1 (Active / Inactive) 0 1 49 SDRAM0 (Active / Inactive)

Description

5.3 Register 2: PCI Clock Register (1 = Active, 0 = Inactive)

Bit @PowerUp Pin

7 1 20 PCICLK7 (Active / Inactive) 6 1 19 PCICLK6 (Active / Inactive) 5 1 18 PCICLK5 (Active / Inactive) 4 1 16 PCICLK4 (Active / Inactive) 3 1 15 PCICLK3 (Active / Inactive) 2 1 13 PCICLK2 (Active / Inactive) 1 1 12 PCICLK1 (Active / Inactive) 0 1 11 PCICLK0 (Active / Inactive)

- 6 - Revision 0.42

Description

Publication Release Date: June 2000

5.4 Register 3: Control Register (1 = Active, 0 = Inactive)

W83195BR-S

PRELIMINARY

Bit @PowerUp Pin

7 1 9 3V66_2(Active/Inactive) 6 1 8 3V66_1(Active / Inactive) 5 1 7 3V66_0(Active / Inactive) 4 1 31 SDRAM12 (Active / Inactive) 3 1 32 SDRAM11 (Active / Inactive) 2 1 35 SDRAM10 (Active / Inactive) 1 1 36 SDRAM9 (Active / Inactive) 0 1 37 SDRAM8 (Active / Inactive)

Description

5.5 Register 4: Control Register (1 = Active, 0 = Inactive)

Bit @PowerUp Pin

7 0 6 0 5 0 4 0 3 0 -

2 0 1 0 0

0 - 0 = Running

-

SSEL3 (Frequency table selection by software via I2C ) SSEL2 ( Frequency table selection by software via I2C) SSEL1 ( Frequency table selection by software via I2C) SSEL0 ( Frequency table selection by software via I2C) 0 = Selection by hardware

1 = Selection by software I2C - Bit (1,2, 4:6) SSEL4 (Frequency table selection by software via I2C )

SSEL5 (Frequency table selection by software via I2C )

1 = Tristate all outputs

Description

5.6 Register 5: Skew Register

Bit @PowerUp Pin

7 6 5 4 3 2 1 1 51 CPUCLK1(Active/Inactive) 0 1 52 CPUCLK0(Active / Inactive)

1 - CSkew2 (CPU to SDRAM skew program bit) 0 - CSkew1 (CPU to SDRAM skew program bit) 0 - CSkew0 (CPU to SDRAM skew program bit) 1 - CASkew2 (CPU to 3V66 skew program bit) 0 - CASkew1 (CPU to 3V66 skew program bit) 0 - CASkew0 (CPU to 3V66 skew program bit)

- 7 - Revision 0.42

Description

Publication Release Date: June 2000

5.7 Register 6~10: Step-less M/N control registers

5.12 Register 11: Winbond Chip ID Register (Read Only)

W83195BR-S

PRELIMINARY

Bit @PowerUp Pin

7 0 - Winbond Chip ID 6 1 - Winbond Chip ID 5 0 - Winbond Chip ID 4 1 - Winbond Chip ID

3 0 - Winbond Chip ID

2 0 - Winbond Chip ID 1 0 - Winbond Chip ID 0 0 - Winbond Chip ID

Description

5.13 Register 12: Winbond Chip ID Register (Read Only)

Bit @PowerUp Pin

7 0 - Winbond Chip ID 6 0 - Winbond Chip ID 5 1 - Winbond Chip ID 4 0 - Winbond Chip ID 3 0 - Winbond Chip ID 2 0 - Winbond Version ID 1 1 - Winbond Version ID 0 0 - Winbond Version ID

Description

Register10 Bit3-6 Ratio Bit6 Bit 5 Bit 4 Bit 3 DS3 DS2 DS1 DS0 CPU SDRAM 3V66

0 0 0 0 4 4 6 0 0 0 1 3 3 6 0 0 1 0 2 3 6 0 0 1 1 2 2 6 0 1 0 0 6 4 6 0 1 0 1 3 4 6 0 1 1 0 6 3 6 0 1 1 1 4 3 6 1 0 x x 2 2 4 1 1 x x 2 4 6

- 8 - Revision 0.42

Publication Release Date: June 2000

6.0 ORDERING INFORMATION

Part Number Package Type Production Flow

W83195BR-S

PRELIMINARY

W83195BR-S 56 PIN SSOP

Commercial, 0°C to +70°C

7.0 HOW TO READ THE TOP MARKING

1st line: Winbond logo and the type number: W83195BR-S

2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2

8051234: wafer production series lot number

3rd line: Tracking code 814 G B B 814: packages made in '98, week 14

G: assembly house ID; O means OSE, G means GR

A: Internal use code

B: IC revision

All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

W83195BR-S 28051234 814GAB

Publication Release Date: June 2000

- 9 - Revision 0.42

8.0 PACKAGE DRAWING AND DIMENSIONS

Y

SEATING PLANE

TOP VIEW

D

e

SIDE VIEW

0.40/0.50 DIA

b

θ

.035 .045

PARTING LINE

c

A1

E

HE

A2

DETAIL"A"

A

L

.045 .055

L1

SEE DETAIL "A"

SYMBOL

END VIEW

c

θ

DIMENSION IN MM

MIN. NOM MAX. MAX.NOM

2.79

2.57

2.41

A

0.30 0.41

0.20

A1

A2

2.24

0.20 0.34

b

0.13 0.25

c

18.2

D

H

10.16

E

7.42

0.51 0.760.64

e

0.61 0.81

L

L1

Y

0

θ

2.29

0.25

18.42

10.31

7.52

1.40

2.34

18.54

10.41

7.59

1.02

0.08 8

W83195BR-S

PRELIMINARY

DIMENSION IN INCH

MIN.

0.101

0.095

0.008

0.088

0.008 0.0135

0.005 0.010

0.720 0.7300.725

0.400

0.292

0.020 0.0300.025

0.024 0.032

0

0.110

0.012 0.016

0.090

0.092

0.010

0.410

0.406

0.2990.296

0.040

0.055

0.003 8

Headquarters

No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064

Winbond Electronics (North America) Corp.

2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE

Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale.

Publication Release Date: June 2000

- 10 - Revision 0.42