Datasheet W83194BR-S Datasheet (Winbond Electronics)

W83194BR-S

200MHZ 2-DIMM CLOCK FOR SOLANO CHIPSET

1.0 GENERAL DESCRIPTION

The W83194BR-S is a Clock Synthesizer for Intel 815 Solano chipset. W83194BR-S provides all clocks required for high-speed RISC or CISC microprocessor and also provides 64 different frequencies of CPU, SDRAM, PCI, 3V66, IOAPIC clocks frequency setting. All clocks are externally selectable with smooth transitions.

The W83194BR-S provides I2C serial bus interface to program the registers to enable or disable each clock outputs and provides 0.25% and 0.5% center type spread spectrum to reduce EMI.

The W83194BR-S provides stepless frequency programming by controlling the VCO freq. and the clock output divisor ratio. Also the skew of CPU, SDRAM and 3V66 clock outputs are programmable. A watch dog timer is quipped and when time out, the RESET# pin will output 4ms pulse signal.

The W83194BR-S accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50± 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide better than 0.5V /ns slew rate.

2.0 PRODUCT FEATURES

• 2 CPU clocks

• 3 3V66 for chipset and AGP clocks

• 9 SDRAM clocks for 2 DIMMs

• 7 PCI synchronous clocks.

• Optional single or mixed supply:

(VddR = VddP=VddS = Vdd48 = Vdd3 = 3.3V, VddLAPIC=VddLCPU=2.5V)

• Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns

• Smooth frequency switch with selections from 66.8 to 200 MHz

• I2C 2-Wire serial interface and I2C read back

• 0.25% and 0.5% center type spread spectrum

• Programmable registers to enable/stop each output and select modes

• Two 48 MHz pins for USB

• 24 MHz for super I/O

• 48-pin SSOP package

Publication Release Date:June 2000

- 1 - Revision 0.42

3.0 PIN CONFIGURATION

W83194BR-S

PRELIMINARY

*SIO_SEL/24_48MHz

*: internal pull-up #: active low $: ope drain

REFX2/*FS3

VddR

Xin

Xout

Vss

Vdd3 3V66-0 3V66-1

3V66-2

Vss

PCICLK0^/ *FS0 PCICLK1^/ FS1# PCICLK2^/*FS2

VssP

PCICLK3/MODE1*

PCICLK4^

VddP

PCICLK5^ PCICLK6

Vss48

48MHz_0

48MHz_1/ FS4#

Vdd48

1 2 3 4

5 6 7

8 9 10 11

12 13

14 15

16

17 18 19 20 21 22

23 24

48 47 46 45

44 43 42 41 40 39 38 37 36 35

34 33 32 31 30 29 28 27

26 25

VddLAPIC

IOAPIC

VddLCPU CPUCLK0 CPUCLK1

VssC

VddS SDRAM 0 SDRAM 1 SDRAM 2 VssS

SDRAM 3 SDRAM 4

SDRAM 5 VddS

SDRAM 6 SDRAM 7

SDRAM 8 VssS

PD#/RESET$

SDCLK*

VddA

VssA SDATA*

4.0 PIN DESCRIPTION

IN - Input OUT - Output I/O - Bi-directional Pin # - Active Low l - Internal 250kΩ pull-up

Publication Release Date: June 2000

- 2 - Revision

0.42

PCICLK1/ FS1#

PCICLK2/ *FS2

4.1 Crystal I/O

SYMBOL PIN I/O FUNCTION

Xin 3 IN Crystal input with internal loading capacitors(36pF)

Xout 4 OUT Crystal output at 14.318MHz nominally with internal

4.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs

SYMBOL PIN I/O FUNCTION

CPUCLK [0:1] 45,44 OUT Low skew (< 250ps) clock outputs for host

PD#/RESET$ 29 IN Pin16 *Mode1=1, Power Down mode when driven

IOAPIC

SDRAM [ 0:8] 41,40,

PCICLK0/ *FS0 11 I/O 3.3V 33MHz PCI clock during normal operation.

PCICLK3/MODE1* 15 I/O PCI clock during normal operation.

PCICLK [ 4:6 ] 16,18,19 OUT Low skew (< 250ps) PCI clock outputs.

3V66 [0:2] 7,8,9 OUT 3.3V output clocks for the chipset.

W83194BR-S

PRELIMINARY

and feedback resistors.

loading capacitors(36pF).

frequencies such as CPU and Chipset.

low. Pin16 *Mode1=0, RESET# output (4ms low active

pulse when Watch Dog time out)

47 OUT Clock outputs synchronous with PCI clock and

powered by VddA.

OUT SDRAM clock outputs.

39,37,36,35,33

,32,31

Latched input for FS0 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks(Default=1).

12 I/O Low skew (< 250ps) PCI clock outputs.

Latched input for FS1 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks(Default=0).

13 I/O Low skew (< 250ps) PCI clock outputs.

Latched input for FS2 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks(Default=1).

Latched Input. *Mode1=1, Pin 29 is PD#; *Mode1=0, Pin 29 is RESET$

Publication Release Date: June 2000

- 3 - Revision

0.42

W83194BR-S

output frequency of 24MHz(HIGH) and 48MHz(LOW)

PRELIMINARY

4.3 I2C Control Interface

SYMBOL PIN I/O FUNCTION

SDATA 25 I/O Serial data of I2C 2-wire control interface SDCLK 28 IN Serial clock of I2C 2-wire control interface

4.4 Fixed Frequency Outputs

SYMBOL PIN I/O FUNCTION

REFX2 / *FS3 3 I/O 14.318MHz reference clock. This REF output is the

stronger buffer for ISA bus loads. Latched input for FS3 at initial power up for H/W

selecting the output frequency of CPU, SDRAM and PCI clocks (Default=1).

*SIO_SEL/24_48MHz 23 I/O 24MHz or 48MHz output clock.

Latched input for SIO_SEL at initial power up for the

48MHz_0 21 O 48MHz output for USB during normal operation. 48MHz_1/ FS4# 22 I/O 48MHz / Latched input for FS4 at initial power

4.5 Power Pins

SYMBOL PIN FUNCTION

VddL 48 Power supply for CPU & IOAPIC, 2.5V or 3.3V. Vdd48 24 Power supply for 48MHz output,3.3V. Vdd3 6 Power supply for 3V_66 output, 3.3V. VddP 16 Power supply for PCICLK, 3.3V. VddR 2 Power supply for REFX2, 3.3V. VddS 42,34 Power supply for SDRAM[0:8], nominal 3.3V. VddA 27 Power for I2C CLK and DATA. Vss 5,10,14,20,26,30,38,

43

clocks.

up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks (Default=0).

Circuit Ground.

Publication Release Date: June 2000

- 4 - Revision

0.42

5.0 FREQUENCY SELECTION BY HARDWARE

SDRAM

W83194BR-S

PRELIMINARY

FS4 FS3 FS2 FS1 FS0

0 0 0 0 0 75.30 112.95 0 0 0 0 1 95.00 95.00 0 0 0 1 0 129.00 129.00 0 0 0 1 1 150.00 113.00 0 0 1 0 0 150.00 150.00 0 0 1 0 1 110.00 110.00 0 0 1 1 0 140.00 140.00 0 0 1 1 1 144.00 108.00 0 1 0 0 0 68.30 102.45 0 1 0 0 1 105.00 105.00 0 1 0 1 0 138.00 138.00 0 1 0 1 1 140.00 105.00 0 1 1 0 0 66.80 100.20 0 1 1 0 1 100.20 100.20 0 1 1 1 0 133.60 133.60 0 1 1 1 1 133.60 100.20 1 0 0 0 0 157.30 118.00 1 0 0 0 1 160.00 120.00 1 0 0 1 0 146.00 110.00 1 0 0 1 1 122.00 91.50 1 0 1 0 0 127.00 127.00 1 0 1 0 1 122.00 122.00 1 0 1 1 0 117.00 117.00 1 0 1 1 1 114.00 114.00 1 1 0 0 0 80.00 120.00 1 1 0 0 1 78.00 117.00 1 1 0 1 0 166.00 166.00 1 1 0 1 1 160.00 160.00 1 1 1 0 0 66.60 100.00 1 1 1 0 1 100.00 100.00 1 1 1 1 0 133.30 133.30 1 1 1 1 1 133.30 100.00

CPU(MHz)

(MHz)

3V66(MHz) PCI(MHz)

75.30 37.65 18.83

63.33 31.67 15.83

86.00 43.00 21.50

75.33 37.67 18.83

75.00 37.50 18.75

73.33 36.67 18.33

70.00 35.00 17.50

72.00 36.00 18.00

68.30 34.15 17.08

70.00 35.00 17.50

69.00 34.50 17.25

70.00 35.00 17.50

66.80 33.40 16.70

78.67 39.33 19.67

80.00 40.00 20.00

73.33 36.67 18.33

61.00 30.50 15.25

84.67 42.33 21.17

81.33 40.67 20.33

78.00 39.00 19.50

76.00 38.00 19.00

80.00 40.00 20.00

78.00 39.00 19.50

83.00 41.50 20.75

80.00 40.00 20.00

66.67 33.33 16.67

66.65 33.33 16.66

66.67 33.33 16.67

IOAPIC

(MHz)

Publication Release Date: June 2000

- 5 - Revision

0.42

SDRAM

W83194BR-S

PRELIMINARY

6.0 SERIAL CONTROL REGISTERS

The Pin column lists the affected pin number and the @PowerUp column gives the state at true power up. Registers are set to the values shown only on true power up. "Command Code" byte and "Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge.

After that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and

acknowledged.

Frequency Table Setting by I2C (SEL5 ~ SEL0)

SSEL5 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0

0 0 0 0 0 0 75.30 0 0 0 0 0 1 95.00 0 0 0 0 1 0 129.00 129.00 0 0 0 0 1 1 150.00 113.00 0 0 0 1 0 0 150.00 150.00 0 0 0 1 0 1 110.00 110.00 0 0 0 1 1 0 140.00 140.00 0 0 0 1 1 1 144.00 108.00 0 0 1 0 0 0 68.30 0 0 1 0 0 1 105.00 105.00 0 0 1 0 1 0 138.00 138.00 0 0 1 0 1 1 140.00 105.00 0 0 1 1 0 0 66.80 0 0 1 1 0 1 100.20 100.20 0 0 1 1 1 0 133.60 133.60 0 0 1 1 1 1 133.60 100.20 0 1 0 0 0 0 157.30 118.00 0 1 0 0 0 1 160.00 120.00 0 1 0 0 1 0 146.00 110.00 0 1 0 0 1 1 122.00 0 1 0 1 0 0 127.00 127.00 0 1 0 1 0 1 122.00 122.00 0 1 0 1 1 0 117.00 117.00 0 1 0 1 1 1 114.00 114.00 0 1 1 0 0 0 80.00 0 1 1 0 0 1 78.00 0 1 1 0 1 0 166.00 166.00 0 1 1 0 1 1 160.00 160.00 0 1 1 1 0 0 66.60

- 6 - Revision

CPU

(MHz)

112.95

95.00

102.45

100.20

91.50

120.00

117.00

100.00

3V66

(MHz)

75.30

63.33

86.00

75.33

75.00

73.33

70.00

72.00

68.30

70.00

69.00

70.00

66.80

78.67

80.00

73.33

61.00

84.67

81.33

78.00

76.00

80.00

78.00

83.00

80.00

66.67

Publication Release Date: June 2000

PCI(MHz)

37.65

31.67

43.00

37.67

37.50

36.67

35.00

36.00

34.15

35.00

34.50

35.00

33.40

39.33

40.00

36.67

30.50

42.33

40.67

39.00

38.00

40.00

39.00

41.50

40.00

33.33

IOAPIC

(MHz)

18.83

15.83

21.50

18.83

18.75

18.33

17.50

18.00

17.08

17.50

17.25

17.50

16.70

19.67

20.00

18.33

15.25

21.17

20.33

19.50

19.00

20.00

19.50

20.75

20.00

16.67

0.42

W83194BR-S

SDRAM

PRELIMINARY

0 1 1 1 0 1 100.00 100.00 0 1 1 1 1 0 133.30 133.30 0 1 1 1 1 1 133.30 100.00

SSEL5 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0

1 0 0 0 0 0 136.00 102.00 1 0 0 0 0 1 138.00 138.00 1 0 0 0 1 0 139.00 104.25 1 0 0 0 1 1 141.00 105.75 1 0 0 1 0 0 142.00 142.00 1 0 0 1 0 1 142.00 106.50 1 0 0 1 1 0 143.00 143.00 1 0 0 1 1 1 143.00 107.25 1 0 1 0 0 0 144.00 144.00 1 0 1 0 0 1 144.00 108.00 1 0 1 0 1 0 146.00 146.00 1 0 1 0 1 1 146.00 109.50 1 0 1 1 0 0 147.00 147.00 1 0 1 1 0 1 147.00 110.25 1 0 1 1 1 0 148.00 148.00 1 0 1 1 1 1 148.00 111.00 1 1 0 0 0 0 149.00 111.75 1 1 0 0 0 1 152.00 152.00 1 1 0 0 1 0 153.00 114.75 1 1 0 0 1 1 156.00 156.00 1 1 0 1 0 0 157.00 117.75 1 1 0 1 0 1 158.00 158.00 1 1 0 1 1 0 159.00 119.25 1 1 0 1 1 1 160.00 160.00 1 1 1 0 0 0 162.00 121.50 1 1 1 0 0 1 164.00 123.00 1 1 1 0 1 0 170.00 127.50 1 1 1 0 1 1 175.00 116.67 1 1 1 1 0 0 180.00 120.00 1 1 1 1 0 1 185.00 185.00 61.67 1 1 1 1 1 0 190.00 126.67 1 1 1 1 1 1 200.40 133.60

- 7 - Revision

CPU

(MHz)

66.67

66.65

66.67

3V66

(MHz)

68.00

69.00

69.50

70.50

71.00

71.50

72.00

73.00

73.50

74.00

74.50

76.00

76.50

78.00

78.50

79.00

79.50

80.00

81.00

82.00

85.00

77.78

80.00

63.33

66.80

Publication Release Date: June 2000

33.33

PCI(MHz)

34.00

34.50

34.75

35.25

35.50

35.75

36.00

36.50

36.75

37.00

37.25

38.00

38.25

39.00

39.25

39.50

39.75

40.00

40.50

41.00

42.50

38.89

40.00

30.83

31.67

33.40

16.67

16.66

16.67

IOAPIC

(MHz)

17.00

17.25

17.38

17.63

17.75

17.88

18.00

18.25

18.38

18.50

18.63

19.00

19.13

19.50

19.63

19.75

19.88

20.00

20.25

20.50

21.25

19.44

20.00

15.42

15.83

16.70

0.42

6.1 Register 0: Control Register

W83194BR-S

PRELIMINARY

Bit @PowerUp

7 6

5 4 X - FS3#

3 X - FS4# 2 1 -

1 0 0 1 - 1=CENTER SPREAD 0=DOWN SPREAD

X - FS0# X - FS1#

X - FS2#

Pin Description

If Reg0-bit7=1 0 = ±0.5% Center type Spread Spectrum Modulation 1 = ±0.75% Center type Spread Spectrum Modulation If Reg0-bit7=0 0 = -0.6% Down type Spread Spectrum Modulation

1 = -1.0% Down type Spread Spectrum Modulation 0 = Normal

1 = Spread Spectrum enabled

6.2 Register 1 : SDRAM Register (1 = Active, 0 = Inactive)

Bit @PowerUp Pin

7 1 38 SDRAM7 (Active / Inactive) 6 1 41 SDRAM6 (Active / Inactive) 5 1 42 SDRAM5 (Active / Inactive) 4 1 43 SDRAM4 (Active / Inactive) 3 1 44 SDRAM3 (Active / Inactive) 2 1 47 SDRAM2 (Active / Inactive) 1 1 48 SDRAM1 (Active / Inactive) 0 1 49 SDRAM0 (Active / Inactive)

Description

6.3 Register 2: PCI Clock Register (1 = Active, 0 = Inactive)

Bit @PowerUp Pin

7 1 20 PCICLK7 (Active / Inactive) 6 1 19 PCICLK6 (Active / Inactive) 5 1 18 PCICLK5 (Active / Inactive) 4 1 16 PCICLK4 (Active / Inactive) 3 1 15 PCICLK3 (Active / Inactive) 2 1 13 PCICLK2 (Active / Inactive) 1 1 12 PCICLK1 (Active / Inactive) 0 1 11 PCICLK0 (Active / Inactive)

- 8 - Revision

Description

Publication Release Date: June 2000

0.42

6.4 Register 3: Control Register (1 = Active, 0 = Inactive)

W83194BR-S

PRELIMINARY

Bit @PowerUp Pin

7 1 9 3V66_2(Active/Inactive) 6 1 8 3V66_1(Active / Inactive) 5 1 7 3V66_0(Active / Inactive) 4 3 2 1 0 1 1 REF2X (Active / Inactive)

1 23 24_48MHz (Active / Inactive) 1 47 IOAPIC (Active / Inactive) 1 21 48MHz0 (Active / Inactive) 1 22 48MHz1 (Active / Inactive)

Description

6.5 Register 4: Control Register (1 = Active, 0 = Inactive)

Bit @PowerUp Pin

7 0 6 0 5 0 4 0 3 0 -

2 0 1 0 0

0 - 0 = Running

-

SSEL3 (Frequency table selection by software via I2C ) SSEL2 ( Frequency table selection by software via I2C) SSEL1 ( Frequency table selection by software via I2C) SSEL0 ( Frequency table selection by software via I2C) 0 = Selection by hardware

1 = Selection by software I2C - Bit (1,2, 4:6) SSEL4 (Frequency table selection by software via I2C )

SSEL5 (Frequency table selection by software via I2C )

1 = Tristate all outputs

Description

6.6 Register 5: Skew Register

Bit @PowerUp Pin

7 6 5 4 3 2 1 1 51 CPUCLK1(Active/Inactive) 0 1 52 CPUCLK0(Active / Inactive)

- 9 - Revision

1 - CSkew2 (CPU to SDRAM skew program bit) 0 - CSkew1 (CPU to SDRAM skew program bit) 0 - CSkew0 (CPU to SDRAM skew program bit) 1 - CASkew2 (CPU to 3V66 skew program bit) 0 - CASkew1 (CPU to 3V66 skew program bit) 0 - CASkew0 (CPU to 3V66 skew program bit)

Description

Publication Release Date: June 2000

0.42

6.7 Register 6~10: Step-less M/N Mode Control Registers

6.12 Register 11: Winbond Chip ID Register (Read Only)

W83194BR-S

PRELIMINARY

Bit @PowerUp Pin

7 0 - Winbond Chip ID 6 1 - Winbond Chip ID 5 0 - Winbond Chip ID 4 1 - Winbond Chip ID

3 0 - Winbond Chip ID

2 0 - Winbond Chip ID 1 0 - Winbond Chip ID 0 0 - Winbond Chip ID

Description

6.13 Register 12: Winbond Chip ID Register (Read Only)

Bit @PowerUp Pin

7 0 - Winbond Chip ID 6 1 - Winbond Chip ID 5 0 - Winbond Chip ID 4 0 - Winbond Chip ID 3 0 - Winbond Chip ID 2 0 - Winbond Version ID 1 1 - Winbond Version ID 0 0 - Winbond Version ID

Description

Register10 Bit3-6 Ratio Bit6 Bit 5 Bit 4 Bit 3 DS3 DS2 DS1 DS0 CPU SDRAM 3V66

0 0 0 0 4 4 6 0 0 0 1 3 3 6 0 0 1 0 2 3 6 0 0 1 1 2 2 6 0 1 0 0 6 4 6 0 1 0 1 3 4 6 0 1 1 0 6 3 6 0 1 1 1 4 3 6 1 0 x x 2 2 4 1 1 x x 2 4 6

- 10 - Revisio

Publication Release Date: June 2000

n 0.42

W83194BR-S

than those listed in this table may cause permanent damage to the device.

PRELIMINARY

7.0 SPECIFICATIONS

7.1 Absolute Maximum Ratings

Stresses greater Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or Vdd).

Symbol Parameter Rating

Vdd , VIN

Voltage on any pin with respect to GND - 0.5 V to + 7.0 V

T

STG

TB TA

Storage Temperature

Ambient Temperature

Operating Temperature

- 65°C to + 150°C

- 55°C to + 125°C 0°C to + 70°C

7.2 Electronical Characteristics---Input/Output

Vddq1=Vddq2 = Vddq3 = Vddq4 =3.3V, VddL1 =VddL2= 2.5V , TA = 0°C to +70°C

Parameter Symbol Min Typ

Input Low Voltage Input High Voltage Input Low Current Input Low Current Input High Current Input Capacitance CIN 5 pF Logic inputs

C C Operating Supply

Current Power Down Supply

Current Settling Time Ts 3

VIL VIH

IIL IIL

IIH

OUT

INX

I

dd3

I

dd2

Vss-0.3

2.0 Vdd+0.3

-5

-200

-5 5

6 pF Output capacitance

27 45 pF Xin and Xout

100 MA CPU = 66.6 MHz

600

0.8

Max Units

Vdc Vdc

µA µA µA

µA

mS

Test Conditions

No pull-up resistors Pull-up resistros

PCI = 33.3 Mhz with load

From first crossing to 1% target freq.

Publication Release Date: June 2000

- 11 - Revisio n 0.42

W83194BR-S

PRELIMINARY

Delay t t

PZH,tPZH

PLZ,tPZH

1 10 nS Output enable delay 1 10 nS Output enable delay

7.3 Electronical Characteristics of CPU Clock

Vdd=2.5V +/- 5%; CL=10-20pF

Parameter Symbol Min Typ Max Units

Ouput Impedance R Ouput Impedance R Output Low Voltage

Output High Voltage Output Low Current Output High Current Pull-Up Current Min Pull-Up Current Max Rise/Fall Time Min

Between 0.4 V and 2.0 V Rise/Fall Time Max

Between 0.4 V and 2.0 V

13.5 40 Ohm

DSP

13.5 40 Ohm

DSN

VOL

VOH

IOL IOH

I

OH(min)

I

OH(max)

T

RF(min)

T

RF(max)

0.4 V IOL=1mA

2.0 V IOH=-1mA 27 30 MA

-27 -27 MA

-27 MA Vout = 1.0 V

-27 MA Vout = 2.0V

0.4 ns 10pF Load

1.6 ns 20pF Load

Duty Cycle Dt 45 55 % VT=1.25V Skew TSK 175 ps VT=1.25V Jitter Tsc-c 250 ps VT=1.25V

Test Conditions

7.4 Electronical Characteristics of 3V66 Clock

Vdd=3.3V +/- 5%; CL=10-30pF

Parameter Symbol Min Typ Max Units

Ouput Impedance R Ouput Impedance R Output Low Voltage

Output High Voltage Output Low Current Output High Current Rise/Fall Time Min

Between 0.4 V and 2.0 V Rise/Fall Time Max

Between 0.4 V and 2.0 V

15 55 Ohm

DSP

15 55 Ohm

DSN

VOL VOH

IOL IOH

T

RF(min)

T

RF(max)

0.55

2.4 V IOH=-1mA 30 38 MA

-33 -33 MA

0.4 ns 10pF Load

1.6 ns 20pF Load

V IOL=1mA

Publication Release Date: June 2000

- 12 - Revisio

Test Conditions

n 0.42

W83194BR-S

PRELIMINARY

Duty Cycle Dt 45 55 % VT=1.5V Skew TSK 175 ps VT=1.5V Jitter Tsc-c 500 ps VT=1.5V

7.5 Electronical Characteristics of SDRAM Clock

Vdd=3.3V +/- 5%; CL=20-30pF

Parameter Symbol Min Typ Max Units

Ouput Impedance R Ouput Impedance R Output Low Voltage

Output High Voltage Output Low Current Output High Current Rise/Fall Time Min

Between 0.4 V and 2.0 V Rise/Fall Time Max

Between 0.4 V and 2.0 V

13.5 40 Ohm

DSP

13.5 40 Ohm

DSN

VOL VOH

IOL IOH

T

RF(min)

T

RF(max)

0.45

2.4 V IOH=-1mA 54 54 MA

-54 -45 MA

0.4 ns 10pF Load

1.6 ns 20pF Load

V IOL=1mA

Duty Cycle Dt 45 55 % VT=1.5V Skew TSK 250 ps VT=1.5V Jitter Tsc-c 250 ps VT=1.5V

Test Conditions

7.6 Electronical Characteristics of PCI Clock

Vdd=3.3V +/- 5%; CL=10-30pF

Parameter Symbol Min Typ Max Units

Ouput Impedance R Ouput Impedance R Output Low Voltage

Output High Voltage Output Low Current Output High Current Rise/Fall Time Min

Between 0.4 V and 2.0 V Rise/Fall Time Max

15 55 Ohm

DSP

15 55 Ohm

DSN

VOL VOH

IOL IOH

T

RF(min)

T

RF(max)

0.55

2.4 V IOH=-1mA 30 38 MA

-33 -33 MA

0.5 ns 10pF Load

2.0 ns 20pF Load

V IOL=1mA

Publication Release Date: June 2000

- 13 - Revisio

Test Conditions

n 0.42

W83194BR-S

PRELIMINARY

Between 0.4 V and 2.0 V Duty Cycle Dt 45 55 % VT=1.5V Skew TSK 500 ps VT=1.5V Jitter Tsc-c 500 ps VT=1.5V

7.7 Electronical Characteristics of 48MHz, REF Clock

Vdd=3.3V +/- 5%; CL=10-20pF

Parameter Symbol Min Typ Max Units

Ouput Impedance R Ouput Impedance R Output Low Voltage

Output High Voltage Output Low Current Output High Current RiseTime Fall Time Duty Cycle Dt 45 55 % VT=1.5V

Skew TSK 500 ps VT=1.5V Jitter Tsc-c 1000

20 55 Ohm

DSP

20 55 Ohm

DSN

VOL VOH

IOL IOH

TR TF

0.4 V IOL=1mA

2.4 V IOH=-1mA 29 27 MA

-29 -23 MA

1.8 4 ns 10pF Load

1.7 4 ns 20pF Load

ps VT=1.5V

Test Conditions

Publication Release Date: June 2000

- 14 - Revisio n 0.42

8.0 ORDERING INFORMATION

Part Number Package Type Production Flow

W83194BR-S

PRELIMINARY

W83194BR-S 48 PIN SSOP

9.0 HOW TO READ THE TOP MARKING

1st line: Winbond logo and the type number: W83194BR-S

2nd line: Tracking code 2 8051234

2: wafers manufactured in Winbond FAB 2

8051234: wafer production series lot number

3rd line: Tracking code 814 G B B 814: packages made in '98, week 14

G: assembly house ID; O means OSE, G means GR

A: Internal use code B: IC revision

W83194BR-S 28051234 814GAB

Commercial, 0°C to +70°C

All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

Publication Release Date: June 2000

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W83194BR-S

PRELIMINARY

Publication Release Date: June 2000

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10.0 PACKAGE DRAWING AND DIMENSIONS

W83194BR-S

PRELIMINARY

Headquarters

No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064

Winbond Electronics (North America) Corp.

2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668

Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale.

Publication Release Date: June 2000

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n 0.42