Datasheet W83194BR-39B Datasheet (Winbond Electronics)

W83194BR-39B

STEP-LESS 3-DIMM CLOCK

1.0 GENERAL DESCRIPTION

The W83194BR-39B is a Clock Synthesizer which provides all clocks required for high-speed RISC or CISC microprocessor such as Intel Pentium II or Pentium III. W83194BR-39B provides 64 CPU/PCI frequencies which are selectable with smooth transitions by hardware or software. W83194BR-39B also provides 13 SDRAM clocks controlled by the none-delay buffer_in pin.

The W83194BR-39B provides step-less frequency programming by controlling the VCO freq. and the programmable PCI clock output divisor ratio. A watch dog timer is quipped and when time out, the RESET# pin will output 4ms pulse signal.

The W83194BR-39B accepts a 14.318 MHz reference crystal as its input. Spread spectrum built in at ±0.5% or ±0.25% to reduce EMI. Programmable stopping individual clock outputs and frequency selection through I2C interface. The device meets the Pentium power-up stabilization, which requires CPU and PCI clocks be stable within 2 ms after power-up. Using dual function pin for the slots(ISA, PCI, CPU, DIMM) is not recommend.

2.0 PRODUCT FEATURES

• Supports Pentium II and !!! CPU with I2C.

• 2 CPU clocks (one free-running CPU clock)

• 13 SDRAM clocks for 3 DIMMs

• 6 PCI synchronous clocks

• One IOAPIC clock for multiprocessor support

• Optional single or mixed supply:

(Vddq1=Vddq2 = Vddq3 = Vddq4 = VddL1 =VddL2= 3.3V) or (Vddq1= Vddq2 = Vddq3=Vddq4 =

3.3V, VddL1 = VddL2 = 2.5V)

• < 250ps skew among CPU and SDRAM clocks

• < 250ps skew among PCI clocks

• < 5ns propagation delay SDRAM from buffer input

• Skew from CPU (earlier) to PCI clock 1 to 4ns, center 2.6ns.

• Smooth frequency switch with selections from 66 MHz to 200 MHz CPU

• Step-less frequency programming by controlling the VCO freq. and the clock output divisor ratio

• I2C 2-Wire serial interface and I2C read back

• ±0.25% or ±0.5% spread spectrum function to reduce EMI in freq. table mode

• Programmable spread spectrum in the M/N step-less mode

• Programmable registers to enable/stop each output and select modes

• MODE pin for power Management

• RESET# out when watch dog timer time out

• One 48 MHz for USB & one 24 MHz for super I/O

Publication Release Date: June 2000

- 1 - Revision 0.46

• 48-pin SSOP package

3.0 PIN CONFIGURATION

W83194BR-39B

PRELIMINARY

Vddq1

* PD#/REF0^

Vss Xin

Xout

Vddq2

PCICLK_F/MODE0*

PCICLK0^/FS3&

Vss

PCICLK1^ PCICLK2^ PCICLK3^

PCICLK4

Vddq2

BUFFER IN

Vss

SDRAM11 SDRAM10

Vddq3

SDRAM 9 SDRAM 8

Vss

SDATA*

SDCLK*

* :internal 120K pull-high &:Internal 120K pull-down ^ :1.5X strength #: active low $ :open drain

16

21

1 2 3 4

5 6 7 8 9 10 11 12

13 14 15

17 18 19 20

22 23 24

48 47 46 45

44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27

26 25

VddL1 IOAPIC

REF1/FS2*

Vss

CPUCLK_F

CPUCLK1 VddL2

RESET$

SDRAM12 Vss SDRAM 0

SDRAM 1

Vddq3 SDRAM 2 SDRAM 3 Vss SDRAM 4 SDRAM 5

Vddq3 SDRAM 6 SDRAM 7

Vddq4 48MHz/FS0*

24MHz/FS1*

4.0 PIN DESCRIPTION

IN - Input OUT - Output I/O - Bi-directional Pin # - Active Low

Publication Release Date: June 2000

- 2 - Revision 0.46

& - Internal 120KΩ pull-down

Latched Input. *Mode0=1, Pin 2 is REF0; *Mode0=0,

PCICLK0^/FS3&

* - Internal 120kΩ pull-up

4.1 Crystal I/O

SYMBOL PIN I/O FUNCTION

Xin 4 IN Crystal input with internal loading capacitors and

Xout 5 OUT Crystal output at 14.318MHz nominally.

4.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs

SYMBOL PIN I/O FUNCTION

CPUCLK_F 44 OUT Free running CPU clock. Not affected by PD# CPUCLK1 43 OUT Low skew (< 250ps) clock outputs for host

RESET# 41 OD RESET# (open drain, 4ms low active pulse when

IOAPIC 47 OUT High drive buffered output of the crystal, and is

SDRAM [ 0:12] 17,18,20,21,28

,29,31,32,34,

35,37,38,40 PCICLK_F/ *MODE0

PCICLK [1:3]^ PCICLK 4

BUFFER IN 15 IN Inputs to fanout for SDRAM outputs.

7 I/O Free running PCI clock during normal operation.

8 I/O Low skew (< 250ps) PCI clock outputs.

10,11,12,13 OUT Low skew (< 250ps) PCI clock outputs.

W83194BR-39B

PRELIMINARY

feedback resistors.

frequencies such as CPU, Chipset and Cache. Powered by VddL2. Low if PD# is low.

Watch Dog time out)

powered by VddL1.

OUT SDRAM clock outputs. Fanout buffer outputs from

BUFFER IN pin.(Controlled by chipset)

Pin2 is PD#

Latched input for FS3 at initial power up for H/W selecting the output frequency of CPU and PCI clocks.

PCICLK 0:3 are double strength pins PCICLK 4 is not.

Publication Release Date: June 2000

- 3 - Revision 0.46

W83194BR-39B

PRELIMINARY

4.3 I2C Control Interface

SYMBOL PIN I/O FUNCTION

SDATA* 23 I/O Serial data of I2C 2-wire control interface SDCLK* 24 IN Serial clock of I2C 2-wire control interface

4.4 Fixed Frequency Outputs

SYMBOL PIN I/O FUNCTION

REF0^ / PD# 2 I/O 14.318MHz reference clock. This REF output is the

stronger buffer for ISA bus loads.(pin7 *Mode0=1) Halt all clocks at logic 0 level, when input low (pin7

*Mode0=0)

REF1 / FS2* 46 I/O 14.318MHz reference clock.

Latched input for FS2 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks.

24MHz / FS1* 25 I/O 24MHz output clock.

Latched input for FS1 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks.

48MHz / FS0* 26 I/O 48MHz output for USB during normal operation.

Latched input for FS0 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks.

4.5 Power Pins

SYMBOL PIN FUNCTION

Vddq1 1 Power supply for Ref [0:1] crystal and core logic. VddL1 48 Power supply for IOAPIC output, either 2.5V or 3.3V. VddL2 42 Power supply for CPUCLK[0:3], either 2.5V or 3.3V. Vddq2 6, 14 Power supply for PCICLK_F, PCICLK[0:4], 3.3V. Vddq3 19, 30, 36 Power supply for SDRAM[0:12], and CPU PLL core,

nominal 3.3V.

Vddq4 27 Power for 24 & 48MHz output buffers and fixed PLL

core.

Vss 3,9,16,22,33,39,45 Circuit Ground.

Publication Release Date: June 2000

- 4 - Revision 0.46

5.0 FREQUENCY BY HARDWARE

W83194BR-39B

PRELIMINARY

FS3 FS2 FS1 FS0

0 0 0 0 80.00 80.00 40.00 0 0 0 1 75.00 75.00 37.50 0 0 1 0 83.30 83.30 41.65 0 0 1 1 66.82 66.82 33.41 0 1 0 0 103.00 103.00 34.33 0 1 0 1 112.00 112.00 37.34 0 1 1 0 68.01 68.01 34.01 0 1 1 1 100.23 100.23 33.41 1 0 0 0 120.00 120.00 30.00 1 0 0 1 115.00 115.00 38.33 1 0 1 0 120.00 120.00 40.00 1 0 1 1 105.00 105.00 35.00 1 1 0 0 140.00 140.00 35.00 1 1 0 1 155.00 155.00 38.75 1 1 1 0 124.00 124.00 31.00 1 1 1 1 133.30 133.30 33.30

CPU(MHz) SDRAM(MHz)

PCI(MHz)

Publication Release Date: June 2000

- 5 - Revision 0.46

W83194BR-39B

PRELIMINARY

6.0 MODE PIN -POWER MANAGEMENT INPUT CONTROL

MODE0, Pin7 (Latched Input) PIN 2

0 PD# (Input) 1 REF0 (Output)

7.0 FUNCTION DESCRIPTION

7.1 2-WIRE I2C CONTROL INTERFACE

The clock generator is a slave I2C component which can be read back the data stored in the latches for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-wire control interface allows each clock output individually enabled or disabled. On power up, the W83194BR-39Binitializes with default register settings. Use of the 2-wire control interface is then optional.

The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high during normal data transfer. There are only two exceptions. One is a high-to-low transition on SDATA while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a low-to-high transition on SDATA while SDCLK is high used to indicate the end of a data transfer cycle. Data is always sent as complete 8-bit bytes followed by an acknowledge generated.

Byte writing starts with a “start” condition followed by 7-bit slave address and a write command bit [1101 0010], command code checking [0000 0000], and byte count checking. After successful reception of each byte, an “acknowledge“ (low) on the SDATA wire will be generated by the clock chip. Controller can start to write to internal I2C registers after the string of data. The sequence order is as follows:

Bytes sequence order for I2C controller :

Clock Address A(6:0) & R/W

Set R/W to 1 when ?ead back”, the data sequence is as follows :

Clock Address A(6:0) & R/W

Ack

8 bits dummy Command code

Byte 0 Ack

Ack

8 bits dummy Byte count

Byte 1

Ack

Byte0,1,2... until Stop

Byte2, 3, 4... until Stop

Publication Release Date: June 2000

- 6 - Revision 0.46

W83194BR-39B

PRELIMINARY

7.2 SERIAL CONTROL REGISTERS

The Pin column lists the affected pin number and the @PowerUp column gives the default state at true power up. "Command Code" byte and "Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. After that, the sequence described below

(Register 0, Register 1, Register 2, ....) will be valid and acknowledged.

FREQUENCY BY SOFTWARE

SSEL5 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0

0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 0 1 1 1 1 0 1 0 0 0 0 0 1 0 0 0 1 127.00 127.00 31.75 0 1 0 0 1 0 130.00 130.00 32.50 0 1 0 0 1 1 135.00 135.00 33.75 0 1 0 1 0 0 136.00 136.00 34.00 0 1 0 1 0 1 137.00 137.00 34.25 0 1 0 1 1 0 139.00 139.00 34.75 0 1 0 1 1 1 140.00 140.00 35.00 0 1 1 0 0 0 141.00 141.00 35.25 0 1 1 0 0 1 142.00 142.00 35.50 0 1 1 0 1 0 143.00 143.00 35.75

CPU(MHz) SDRAM(MHz) PCI(MHz)

80.00 80.00 40.00

75.00 75.00 37.50

83.30 83.30 41.65

66.82 66.82 33.41

103.00 103.00 34.33

112.00 112.00 37.34

68.01 68.01 34.01

100.23 100.23 33.41

120.00 120.00 30.00

115.00 115.00 38.33

120.00 120.00 40.00

105.00 105.00 35.00

140.00 140.00 35.00

155.00 155.00 38.75

124.00 124.00 31.00

133.30 133.30 33.30

160.00 160.00 40.00

Publication Release Date: June 2000

- 7 - Revision 0.46

W83194BR-39B

PRELIMINARY

0 1 1 0 1 1 144.00 144.00 36.00 0 1 1 1 0 0 145.00 145.00 36.25 0 1 1 1 0 1 146.00 146.00 36.50 0 1 1 1 1 0 148.00 148.00 37.00 0 1 1 1 1 1 149.00 149.00 37.25

SSEL5 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0

1 0 0 0 0 0 151.00 151.00 37.75 1 0 0 0 0 1 152.00 152.00 38.00 1 0 0 0 1 0 153.00 153.00 38.25 1 0 0 0 1 1 154.00 154.00 38.50 1 0 0 1 0 0 155.00 155.00 38.75 1 0 0 1 0 1 156.00 156.00 39.00 1 0 0 1 1 0 157.00 157.00 39.25 1 0 0 1 1 1 158.00 158.00 39.50 1 0 1 0 0 0 159.00 159.00 39.75 1 0 1 0 0 1 162.00 162.00 40.50 1 0 1 0 1 0 163.00 163.00 32.60 1 0 1 0 1 1 164.00 164.00 32.80 1 0 1 1 0 0 165.00 165.00 33.00 1 0 1 1 0 1 167.00 167.00 33.40 1 0 1 1 1 0 168.00 168.00 33.60 1 0 1 1 1 1 169.00 169.00 33.80 1 1 0 0 0 0 170.00 170.00 34.00 1 1 0 0 0 1 172.00 172.00 34.40 1 1 0 0 1 0 174.00 174.00 34.80 1 1 0 0 1 1 176.00 176.00 35.20 1 1 0 1 0 0 178.00 178.00 35.60 1 1 0 1 0 1 180.00 180.00 36.00 1 1 0 1 1 0 182.00 182.00 36.40 1 1 0 1 1 1 184.00 184.00 36.80 1 1 1 0 0 0 186.00 186.00 37.20 1 1 1 0 0 1 188.00 188.00 37.60 1 1 1 0 1 0 190.00 190.00 38.00 1 1 1 0 1 1 192.00 192.00 38.40 1 1 1 1 0 0 194.00 194.00 38.80

CPU(MHz) SDRAM(MHz) PCI(MHz)

Publication Release Date: June 2000

- 8 - Revision 0.46

W83194BR-39B

PRELIMINARY

1 1 1 1 0 1 196.00 196.00 39.20 1 1 1 1 1 0 198.00 198.00 39.60 1 1 1 1 1 1 200.00 200.00 40.00

7.2.1 Register 0: CPU Frequency Select Register (default = 0)

Bit @PowerUp

7 0 - SSEL5 (for frequency table selection by software via I2C) 6 0 - SSEL4 (for frequency table selection by software via I2C) 5 0 - SSEL3 (for frequency table selection by software via I2C) 4 0 - SSEL2 (for frequency table selection by software via I2C) 3 0 - SSEL1 (for frequency table selection by software via I2C) 2 0 - SSEL0 (for frequency table selection by software via I2C) 1 0 - 0 = Selection by hardware

0 0 - 0 = Running

Pin Description

1 = Selection by software I2C - Bit 7:2

1 = Tristate all outputs

7.2.2 Register 1 : CPU , 48/24 MHz Clock Register (1 = enable, 0 = Stopped)

Bit @PowerUp Pin

7 1 - Reserved 6 1 - Reserved

Description

5 0 - 0 = Normal

1 = Spread Spectrum enabled

4 0 - 0 = ±0.25% Spread Spectrum Modulation

1 = ±0.5% Spread Spectrum Modulation 3 1 40 SDRAM12 (Active / Inactive) 2 1 - Reserved 1 1 43 CPUCLK1 (Active / Inactive) 0 1 44 CPUCLK_F (Active / Inactive)

Publication Release Date: June 2000

- 9 - Revision 0.46

7.2.3 Register 2: PCI Clock Register (1 = enable, 0 = Stopped)

W83194BR-39B

PRELIMINARY

Bit @PowerUp Pin

7 1 - Reserved 6 1 7 PCICLK_F (Active / Inactive) 5 1 - Reserved 4 1 14 PCICLK4 (Active / Inactive) 3 1 12 PCICLK3 (Active / Inactive) 2 1 11 PCICLK2 (Active / Inactive) 1 1 10 PCICLk1 (Active / Inactive) 0 1 8 PCICLK0 (Active / Inactive)

Description

7.2.4 Register 3: SDRAM Clock Register ( 1 = enable, 0 = Stopped )

Bit @PowerUp

7 1 46 REF1 (Active / Inactive) 6 1 2 REF0 (Active / Inactive) 5 1 26 48MHz (Active / Inactive) 4 1 25 24MHz (Active / Inactive) 3 1 47 IOAPIC (Active / Inactive) 2 1 21,20,18,17 SDRAM(8:11) (Active / Inactive) 1 1 32,31,29,28 SDRAM(4:7) (Active / Inactive) 0 1 38,37,35,34 SDRAM(0:3) (Active / Inactive)

Pin Description

7.2.5 Register 4: Reserved Register (1 = enable, 0 = Stopped)

Bit @PowerUp Pin

7 1 - Reserved 6 X - Latched FS3# 5 X - Latched FS2# 4 X - Latched FS1# 3 X - Latched FS0#

- 10 - Revision 0.46

Description

Publication Release Date: June 2000

2 1 - Reserved 1 1 - Reserved 0 1 - Reserved

7.2.6 Register 5: Reserved Register

W83194BR-39B

PRELIMINARY

Bit @PowerUp Pin

7 1 - Reserved 6 0 - Reserved 5 0 - Reserved 4 1 - Reserved 3 0 - Reserved 2 0 - Reserved 1 1 - Reserved 0 1 - Reserved

Description

7.2.7 Register 6~11: M/N step-less mode control registers

7.2.12 Register 11: Winbond Chip ID Register (Read Only)

Bit @PowerUp Pin

7 0 - Winbond Chip ID 6 1 - Winbond Chip ID 5 1 - Winbond Chip ID 4 0 - Winbond Chip ID 3 0 - Winbond Chip ID 2 0 - Winbond Chip ID 1 1 - Winbond Chip ID 0 0 - Winbond Chip ID

Description

7.2.13 Register 12: Winbond Chip ID Register (Read Only)

Bit @PowerUp Pin

7 6 5 4 3

0 - Winbond Chip ID 1 - Winbond Chip ID 0 - Winbond Chip ID 1 - Winbond Chip ID 0 - Winbond Version ID

- 11 - Revision 0.46

Description

Publication Release Date: June 2000

W83194BR-39B

PRELIMINARY

2 1 0

0 - Winbond Version ID 0 - Winbond Version ID 1 - Winbond Version ID

Publication Release Date: June 2000

- 12 - Revision 0.46

W83194BR-39B

PRELIMINARY

8.0 SPECIFICATIONS

8.1 ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or Vdd).

Symbol Parameter Rating

Voltage on any pin with respect to GND - 0.5 V to + 7.0 V

Storage Temperature

Ambient Temperature

Operating Temperature

- 65°C to + 150°C

- 55°C to + 125°C 0°C to + 70°C

Vdd , VIN

T

STG

TB TA

8.2 AC CHARACTERISTICS

Vdd = Vddq3 = 3.3V ± 5 %, Vddq2 = VddL1=VddL2 = 2.375V~2.9V , TA = 0°C to +70°C

Parameter Symbol Min Typ

Output Duty Cycle CPU/SDRAM to PCI Offset

Skew (CPU-CPU), (PCIPCI), (SDRAM-SDRAM)

CPU/SDRAM Cycle to Cycle Jitter CPU/SDRAM Absolute Jitter Jitter Spectrum 20 dB Bandwidth from Center Output Rise (0.4V ~ 2.0V) & Fall (2.0V ~0.4V) Time

Overshoot/Undershoot Beyond Power Rails Ring Back Exclusion VRBE 0.7 2.1 V Ring Back must not enter this

t

OFF

t

SKEW

t

CCJ

tJA

BWJ 500 KHz

t

TLH

t

THL

Vover 0.7 1.5 V

45 50 55 % Measured at 1.5V

1 2.6 4 ns 15 pF Load Measured at 1.5V

250 ps 15 pF Load Measured at 1.5V

±250 ps

500 ps

0.4 1.6 ns 15 pF Load on CPU and PCI

Max Units

Test Conditions

outputs

22 Ω at source of 8 inch PCB run to 15 pF load

range.

Publication Release Date: June 2000

- 13 - Revision 0.46

W83194BR-39B

PRELIMINARY

8.3 DC CHARACTERISTICS

Vdd = Vddq3 = 3.3V ± 5 %, Vddq2 = VddL1=VddL2 = 2.375V~2.9V , TA = 0°C to +70°C

Parameter Symbol Min Typ Max Units

Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage

I

= 4 mA

OL

Output High Voltage IOH = 4mA Tri-State leakage Current Dynamic Supply Current

for Vdd + Vddq3 Dynamic Supply Current for Vddq2 + Vddq2b CPU Stop Current for Vdd + Vddq3 CPU Stop Current for Vddq2 + Vddq2b

VIL

VIH

IIL

IIH

VOL

VOH

Ioz 10

I

dd3

I

dd2

I

CPUS3

I

CPUS2

0.8

2.0

-66 5

0.4

2.4

mA CPU = 66.6 MHz

mA Same as above

Vdc Vdc

µA µA

Vdc

µA

Test Conditions

All outputs

All outputs using 3.3V power

PCI = 33.3 Mhz with load

PCI Stop Current for Vdd + Vddq3

I

PD3

mA

Publication Release Date: June 2000

- 14 - Revision 0.46

8.4 BUFFER CHARACTERISTICS

8.4.1 TYPE 1 BUFFER FOR CPU CLOCK

W83194BR-39B

PRELIMINARY

Parameter Symbol Min Typ Max Units

Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max I

Rise/Fall Time Min Between 0.4 V and 2.0 V

Rise/Fall Time Max Between 0.4 V and 2.0 V

I

OH(min)

I

OH(max)

I

OL(min)

OL(max)

T

RF(min)

T

RF(max)

-27 mA Vout = 1.0 V

-27 mA Vout = 2.0V mA Vout = 1.2 V

27 mA Vout = 0.3 V

0.4 ns 10pF Load

1.6 ns 20pF Load

8.4.2 TYPE 2 BUFFER FOR IOAPIC

Parameter Symbol Min Typ Max Units

Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max I

Rise/Fall Time Min Between 0.7 V and 1.7 V

Rise/Fall Time Max Between 0.7 V and 1.7 V

I

OH(min)

I

OH(max)

I

OL(min)

OL(max)

T

RF(min)

T

RF(max)

mA Vout = 1.4 V

-29 mA Vout = 2.7 V mA Vout = 1.0 V

28 mA Vout = 0.2 V

0.4 ns 10pF Load

1.8 ns 20pF Load

Test Conditions

Publication Release Date: June 2000

- 15 - Revision 0.46

8.4.3 TYPE 3 BUFFER FOR REF1, 24MHZ, 48MHZ

W83194BR-39B

PRELIMINARY

Parameter Symbol Min Typ Max Units

Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max I

Rise/Fall Time Min Between 0.8 V and 2.0 V

Rise/Fall Time Max

I

OH(min)

I

OH(max)

I

OL(min)

OL(max)

T

RF(min)

T

RF(max)

-29 mA Vout = 1.0 V

-23 mA Vout = 3.135V

29 mA Vout = 1.95 V

mA Vout = 0.4 V

1.0 ns 10pF Load

4.0 ns 20pF Load

Between 0.8 V and 2.0 V

8.4.4 TYPE 4 BUFFER FOR SDRAM (0:12)

Parameter Symbol Min Typ Max Units

Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max I

Rise/Fall Time Min Between 0.8 V and 2.0 V

Rise/Fall Time Max Between 0.8 V and 2.0 V

I

OH(min)

I

OH(max)

I

OL(min)

OL(max)

T

RF(min)

T

RF(max)

mA Vout = 1.65 V

-46 mA Vout = 3.135 V mA Vout = 1.65 V

53 mA Vout = 0.4 V

0.5 ns 20pF Load

1.3 ns 30pF Load

Test Conditions

8.4.5 TYPE 5 BUFFER FOR PCICLK(0:4,F)

Parameter Symbol Min Typ Max Units

Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max I

Rise/Fall Time Min Between 0.8 V and 2.0 V

Rise/Fall Time Max Between 0.8 V and 2.0 V

I

OH(min)

I

OH(max)

I

OL(min)

OL(max)

T

RF(min)

T

RF(max)

-33 mA Vout = 1.0 V

-33 mA Vout = 3.135 V

30 mA Vout = 1.95 V

38 mA Vout = 0.4 V

0.5 ns 15pF Load

2.0 ns 30pF Load

- 16 - Revision 0.46

Test Conditions

Publication Release Date: June 2000

W83194BR-39B

PRELIMINARY

9.0 OPERATION OF DUAL FUCTION PINS

Pins 2, 7, 8, 25, and 26 are dual function pins and are used for selecting different functions in this device (see Pin description). During power up, these pins are in input mode (see Fig1), therefore, and are considered input select pins. When Vdd reaches 2.5V, the logic level that is present on these pins is latched into their appropriate internal registers. Once the correct information is properly latched, these pins will change into output pins and will be pulled low by default. At the end of the power up timer (within 3 ms) outputs starts to toggle at the specified frequency.

#7 PCICLK_F/MODE #46 REF1/FS2 #25 24/FS1 #26 48/FS0

All other clocks

2.5V

Output tri-state

Input

Output tri-state

Output pull-low

Within 3ms

Output

Output pull-low

Vdd

Each of these pins has a large pull-up resistor ( 250 kΩ @3.3V ) inside. The default state will be logic 1, but the internal pull-up resistor may be too large when long traces or heavy load appear on these dual function pins. Under these conditions, an external 10 kΩ resistor is recommended to be connected to Vdd if logic 1 is expected. Otherwise, there should be direct connection to ground if a logic 0 is desired. The 10 kΩ resistor should be placed before the serious terminating resistor. Note that these logic will only be latched at initial power on.

If optional EMI reducing capacitor are needed, they should be placed as close to the series terminating resistor as possible and after the series terminating resistor. These capacitors have typical values ranging from 4.7pF to 22pF.

Publication Release Date: June 2000

- 17 - Revision 0.46

W83194BR-39B

PRELIMINARY

Vdd

Device

Programming Header

Vdd Pad

10k

Device

10k

10kΩΩ

Ground Ground

Ω

Series

Terminating

Resistor

Ground Pad

Series

Terminating

Resistor

Clock Trace

EMI Reducing Cap

Optional

Clock Trace

EMI Reducing Cap

Optional

Ground

Publication Release Date: June 2000

- 18 - Revision 0.46

10.0 ORDERING INFORMATION

Part Number Package Type Production Flow

W83194BR-39B

PRELIMINARY

W83194BR-39B 48 PIN SSOP

Commercial, 0°C to +70°C

11.0 HOW TO READ THE TOP MARKING

1st line: Winbond logo and the type number: W83194BR-39B

2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2

8051234: wafer production series lot number

3rd line: Tracking code 814 G B B 814: packages made in '98, week 14

G: assembly house ID; A means ASE, S means SPIL, G means GR

B: Winbond internal use code

W83194BR-39B 28051234 814GBA

A: IC revision

All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

- 19 - Revision 0.46

Publication Release Date: June 2000

12.0 PACKAGE DRAWING AND DIMENSIONS

W83194BR-39B

PRELIMINARY

Headquarters

No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064

Winbond Electronics (North America) Corp.

2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668

Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale.

Publication Release Date: June 2000

- 20 - Revision 0.46