Datasheet W83194AR-We Datasheet (Winbond Electronics)

W83194AR-W

e

200MHZ CLOCK FOR WHITNEY CHIPSET

1.0 GENERAL DESCRIPTION

The W83194AR-We is a Clock Synthesizer for Intel Whitney chipset. W83194AR-We provides all clocks required for high-speed RISC or CISC microprocessor and also provides 64 different frequencies of CPU, SDRAM, PCI, 3V66, IOAPIC clocks frequency setting. All clocks are externally selectable with smooth transitions.

The W83194AR-We provides I2C serial bus interface to program the registers to enable or disable each clock outputs and provides 0.5% and 0.75% center type spread spectrum to reduce EMI.

The W83194AR-We accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50± 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide better than 0.5V /ns slew rate.

2.0 PRODUCT FEATURES

•

2 CPU clocks

•

9 SDRAM clocks for 2 DIMMs

•

8 PCI synchronous clocks.

•

Optional single or mixed supply:

(VddR = VddP=VddS = Vdd48 = Vdd3 = 3.3V, VddA=VddC=2.5V)

• Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns

•

Smooth frequency switch with selections from 66.8 to 200MHz

•

I2C 2-Wire serial interface and I2C read back

•

0.5% and 0.75% center type spread spectrum

•

Programmable registers to enable/stop each output and select modes

(mode as Tri-state or Normal )

•

Two 48 MHz pins for USB

•

24 MHz for super I/O

•

48-pin SSOP package

Publication Release Date: Nov. 1999

- 1 - Revision 0.50

W83194AR-We

PRELIMINARY

3.0 PIN CONFIGURATION

REFX2/*FS3

VddR

Vdd3 3V66-0 3V66-1

Vss3

PCICLK0/ *FS0

PCICLK1/ FS1# PCICLK2/*FS2

VssP

PCICLK3/ *APIC_SEL

PCICLK4

VddP PCICLK5 PCICLK6

PCICLK7

Vss48

48MHz_0

48MHz_1/ FS4#

*SIO_SEL/24_48MHz

Vdd48

Xin

Xout

Vss

1 2 3 4

5 6 7 8 9 10 11 12 13 14 15

16

17 18 19 20

21

22 23 24

48 47 46 45

44 43 42 41 40 39 38 37 36 35

34 33 32 31 30 29 28 27 26 25

VddLAPIC

IOAPIC VddLCPU CPUCLK0 CPUCLK1

VssC

VddS SDRAM 0 SDRAM 1 SDRAM 2 VssS

SDRAM 3 SDRAM 4 SDRAM 5 VddS SDRAM 6 SDRAM 7

SDRAM 8 VssS

PD# *SDCLK VddA

VssA

*SDATA

Publication Release Date: Nov. 1999

- 2 - Revision 0.50

W83194AR-We

with internal

PCICLK1/ FS1#

PCICLK2/ *FS2

PRELIMINARY

4.0 PIN DESCRIPTION

IN - Input OUT - Output I/O - Bi-directional Pin # - Active Low * - Internal 250kΩ pull-up

4.1 Crystal I/O

SYMBOL PIN I/O FUNCTION

Xin 3 IN Crystal input with internal loading capacitors(36pF)

and feedback resistors.

Xout 4 OUT Crystal output at 14.318MHz nominally

4.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs

loading capacitors(36pF).

CPUCLK [0:1] 45,44 OUT Low skew (< 250ps) clock outputs for host

PD# 29 IN Power Down mode when driven low. IOAPIC

SDRAM [ 0:8] 41,40,

PCICLK0/ *FS0 10 I/O 3.3V 33MHz PCI clock during normal operation.

PCICLK3/*APIC_SEL 14 I/O Low skew (< 250ps) PCI clock outputs.

PCICLK [ 4:7 ] 15,17,18,19 OUT Low skew (< 250ps) PCI clock outputs. 3V66 [0:1] 7,8 OUT 3.3V output clocks for the chipset.

SYMBOL PIN I/O FUNCTION

frequencies such as CPU and Chipset.

47 OUT Clock outputs synchronous with PCI clock and

powered by VddA.

OUT SDRAM clock outputs.

39,37,36,35,33

,32,31

Latched input for FS0 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks(Default=1).

11 I/O Low skew (< 250ps) PCI clock outputs.

Latched input for FS1 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks(Default=0).

12 I/O Low skew (< 250ps) PCI clock outputs.

Latched input for FS2 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks(Default=1).

Latched input for APIC_SEL at initial power up for H/W selecting the output frequency of IOAPIC clock (Default=1).

Publication Release Date: Nov. 1999

- 3 - Revision 0.50

W83194AR-We

wire control interface with internal

output frequency of 24MHz(HIGH) and 48MHz(LOW)

PRELIMINARY

4.3 I2C Control Interface

SYMBOL PIN I/O FUNCTION

*SDATA 25 I/O Serial data of I2C 2-

*SDCLK 28 IN Serial clock of I2C 2-wire control interface with

4.4 Fixed Frequency Outputs

SYMBOL PIN I/O FUNCTION

REFX2 / *FS3 3 I/O 14.318MHz reference clock. This REF output is the

*SIO_SEL/24_48MHz 23 I/O 24MHz or 48MHz output clock.

pull-up resistor.

internal pull-up resistor.

stronger buffer for ISA bus loads. Latched input for FS3 at initial power up for H/W

selecting the output frequency of CPU, SDRAM and PCI clocks (Default=1).

Latched input for SIO_SEL at initial power up for the

48MHz_0 21 O 48MHz output for USB during normal operation. 48MHz_1/ FS4# 22 I/O 48MHz / Latched input for FS4 at initial power up

4.5 Power Pins

SYMBOL PIN FUNCTION

VddL 48 Power supply for CPU & IOAPIC, 2.5V or 3.3V. Vdd48 24 Power supply for 48MHz output,3.3V. Vdd3 6 Power supply for 3V_66 output, 3.3V. VddP 16 Power supply for PCICLK, 3.3V. VddR 2 Power supply for REFX2, 3.3V. VddS 42,34 Power supply for SDRAM[0:8], nominal 3.3V. VddA 27 Power for I2C CLK and DATA. Vss 5,9,13,20,26,30,38,

43

clocks.

for H/W selecting the output frequency of CPU, SDRAM and PCI clocks (Default=0).

Circuit Ground.

Publication Release Date: Nov. 1999

- 4 - Revision 0.50

5.0 FREQUENCY SELECTION BY HARDWARE

IOAPIC (MHz)

W83194AR-We

PRELIMINARY

FS4 FS3 FS2 FS1 FS0 CPU

0 0 0 0 0 83.3 124.95 0 0 0 0 1 90 90 1 60.00 30.00 15.00 30.00 0 0 0 1 0 75 112.5 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 95.25 95.25 1 63.50 31.75 15.88 31.75 0 0 1 1 0 121 121 1 80.67 40.33 20.17 40.33 0 0 1 1 1 124 124 1 82.67 41.33 20.67 41.33 0 1 0 0 0 119 119 1 79.33 39.67 19.83 39.67 0 1 0 0 1 114 114 1 76.00 38.00 19.00 38.00 0 1 0 1 0 110 110 1 73.33 36.67 18.33 36.67 0 1 0 1 1 105 105 1 70.00 35.00 17.50 35.00

0 1 1 0 0 66.8 100.2 2/3 0 1 1 0 1 100.2 100.2 1 0 1 1 1 0 133.6 133.6 1 0 1 1 1 1 133.6 100.2 4/3

1 0 0 0 0 135 101.25 4/3 67.50 33.75 16.88 33.75 1 0 0 0 1 125 125 1 83.33 41.67 20.83 41.67 1 0 0 1 0 127 127 1 84.67 42.33 21.17 42.33 1 0 0 1 1 130 130 1 86.67 43.33 21.67 43.33 1 0 1 0 0 140 140 1 70.00 35.00 17.50 35.00 1 0 1 0 1 136 136 1 68.00 34.00 17.00 34.00 1 0 1 1 0 166 166.00 1 83.00 41.50 20.75 41.50 1 0 1 1 1 155 155 1 77.50 38.75 19.38 38.75 1 1 0 0 0 1 1 0 0 1 117 117 1 78.00 39.00 19.50 39.00 1 1 0 1 0 107 107 1 71.33 35.67 17.83 35.67 1 1 0 1 1 100.9 100.9 1 67.27 33.63 16.82 33.63 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1

(MHz)

72 108 2/3 72.00

89.07 133.6 2/3 89.07

150 112.5 4/3 75.00 37.50 18.75 37.50

145 108.75 4/3 72.50 140 105 4/3 70.00 138 103.5 4/3 69.00 137 102.75 4/3 68.50

SDRAM

(MHz)

CPU

/SDRAM

2/3

3V66 (MHz) PCI(MHz)

83.30 41.65 20.83 41.65

75.00 37.50 18.75 37.50

36.00 18.00 36.00

44.53 22.27 44.53

66.80 33.40 16.70 33.40

36.25 18.13 36.25

35.00 17.50 35.00

34.50 17.25 34.50

34.25 17.13 34.25

APIC_SEL=1

APIC_SEL=0

Publication Release Date: Nov. 1999

- 5 - Revision 0.50

W83194AR-We

PRELIMINARY

6.0

SERIAL CONTROL 0REGISTERS

The Pin column lists the affected pin number and the @PowerUp column gives the state at true power up. Registers are set to the values shown only on true power up. "Command Code" byte and "Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge.

After that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and

acknowledged.

Frequency Table Setting by I2C (SEL5 ~ SEL0)

SSE

SS

L5

EL4

EL3

EL2

EL1

0 0 0 0 0 0 83.3 124.95 0 0 0 0 0 1 90 90 1 60.00 30.00 0 0 0 0 1 0 75 112.5 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 95.25 95.25 1 63.50 31.75 0 0 0 1 1 0 121 121 1 80.67 40.33 0 0 0 1 1 1 124 124 1 82.67 41.33 0 0 1 0 0 0 119 119 1 79.33 39.67 0 0 1 0 0 1 114 114 1 76.00 38.00 0 0 1 0 1 0 110 110 1 73.33 36.67 0 0 1 0 1 1 105 105 1 70.00 35.00 0

0 1 1 0 0 66.8 100.2 2/3

0

0 1 1 0 1 100.2 100.2 1

0

0 1 1 1 0 133.6 133.6 1

0

0 1 1 1 1 133.6 100.2 4/3

0 1 0 0 0 0 135 101.25 4/3 67.50 33.75 0 1 0 0 0 1 125 125 1 83.33 41.67 0 1 0 0 1 0 127 127 1 84.67 42.33 0 1 0 0 1 1 130 130 1 86.67 43.33 0 1 0 1 0 0 140 140 1 70.00 35.00 0 1 0 1 0 1 136 136 1 68.00 34.00 0 1 0 1 1 0 166 166.00 1 83.00 41.50 0 1 0 1 1 1 155 155 1 77.50 38.75 0 1 1 0 0 0 0 1 1 0 0 1 117 117 1 78.00 39.00 0 1 1 0 1 0 107 107 1 71.33 35.67 0 1 1 0 1 1 100.9 100.9 1 67.27 33.63 0 1 1 1 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 1 1 1 1 1

SS

EL0

CPU

(MHz)

72 108 2/3 72.00

89.07 133.6 2/3 89.07

150 112.5 4/3 75.00 37.50

145 108.75 4/3 72.50 140 105 4/3 70.00 138 103.5 4/3 69.00 137 102.75 4/3 68.50

SDRAM

(MHz)

CPU/S DRAM

2/3

3V66

(MHz)

83.30 41.65

75.00 37.50

66.80 33.40

PCI(M

Hz)

36.00

44.53

36.25

35.00

34.50

34.25

Publication Release Date: Nov. 1999

- 6 - Revision 0.50

IOAPIC (MHz)

APIC_SEL=1

20.83 41.65

15.00 30.00

18.75 37.50

18.00 36.00

22.27 44.53

15.88 31.75

20.17 40.33

20.67 41.33

19.83 39.67

19.00 38.00

18.33 36.67

17.50 35.00

16.70 33.40

16.88 33.75

20.83 41.67

21.17 42.33

21.67 43.33

17.50 35.00

17.00 34.00

20.75 41.50

19.38 38.75

18.75 37.50

19.50 39.00

17.83 35.67

16.82 33.63

18.13 36.25

17.50 35.00

17.25 34.50

17.13 34.25

IOAPIC (MHz)

APIC_SEL=0

W83194AR-We

PRELIMINARY

SSE

SS

L5

EL4

EL3

EL2

EL1

SS

EL0

1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 1 141 141.00 1 70.50 35.25 1 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 1 1 143 1 0 1 0 0 0 144 144.00 1 72.00 36.00 1 0 1 0 0 1 1 0 1 0 1 0 146 146 1 73.00 36.50 1 0 1 0 1 1 1 0 1 1 0 0 147 147 1 0 1 1 0 1 1 0 1 1 1 0 1 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1

CPU

(MHz)

SDRAM

(MHz)

136 102.00 4/3 138 138.00 139 104.25 4/3

142 142.00

CPU/S DRAM

3V66

(MHz)

68.00 34.00

1

69.00 34.50

69.50 34.75

1 71.00 142 106.50 4/3 71.00 143 143.00

1 71.50

107.25 4/3 71.50

144 108.00 4/3 72.00

146 109.50 4/3 73.00

1

73.50 36.75

147 110.25 4/3 73.50 148 148.00

1 74.00 148 111.00 4/3 74.00 149 111.75 4/3 74.50 152 152.00

1 76.00

153 114.75 4/3 76.50 38.25

156 156.00

1 78.00

157 117.75 4/3 78.50 39.25

158 158.00

1 79.00

159 119.25 4/3 79.50 39.75

160 160.00

1 80.00

162 121.5 4/3 81.00 40.50

164 164.00 170 170.00

1 82.00

1 85.00

175 175 1 87.5 43.75 180 90 2 60 30 15 30 185 92.5 2 61.67 30.83

190 126.67 3/2 63.33

200.4 133.60 3/2 66.80

PCI(M

Hz)

IOAPIC (MHz)

APIC_SEL=1

IOAPIC (MHz)

17.00 34.00

17.25 34.50

17.38 34.75

17.63 35.25

35.50

35.75

17.75 35.50

17.88 35.75

18.00 36.00

36.00

18.00 36.00

18.25 36.50

36.50

18.25 36.50

18.38 36.75

36.75

37.00

37.25

38.00

18.38 36.75

18.50 37.00

18.63 37.25

19.00 38.00

19.13 38.25

39.00

19.50 39.00

19.63 39.25

39.50

19.75 39.50

19.88 39.75

40.00

20.00 40.00

20.25 40.50

41.00

42.50

20.50 41.00

21.25 42.50

21.88 43.75

15.42 30.83

31.67

33.40

15.83 31.67

16.70 33.40

APIC_SEL=0

Publication Release Date: Nov. 1999

- 7 - Revision 0.50

6.1 Register 0: Control Register

Bit @PowerUp Pin Description

7 6 5 4 3 2 1

0

0 - Reserved 1 1 REF2X(Active / Inactive) 0 - Reserved 0 - Reserved 0 - Reserved 1 23 24_48MHz(Active / Inactive) 1 21,22 48MHz_0, 48MHz_1(Active / Inactive) 1 31 SDRAM8(Active / Inactive)

6.2 Register 1 : SDRAM Register (1 = Active, 0 = Inactive)

W83194AR-We

PRELIMINARY

Bit @PowerUp Pin Description

7 1 32 SDRAM7 (Active / Inactive) 6 1 33 SDRAM6 (Active / Inactive) 5 1 35 SDRAM5 (Active / Inactive) 4 1 36 SDRAM4 (Active / Inactive) 3 1 37 SDRAM3 (Active / Inactive) 2 1 39 SDRAM2 (Active / Inactive) 1 1 40 SDRAM1 (Active / Inactive) 0 1 41 SDRAM0 (Active / Inactive)

6.3 Register 2: PCI Clock Register (1 = Active, 0 = Inactive)

Bit @PowerUp Pin Description

7 1 19 PCICLK7 (Active / Inactive) 6 1 18 PCICLK6 (Active / Inactive) 5 1 17 PCICLK5 (Active / Inactive) 4 1 15 PCICLK4 (Active / Inactive) 3 1 14 PCICLK3 (Active / Inactive) 2 1 13 PCICLK2 (Active / Inactive) 1 1 11 PCICLK1 (Active / Inactive) 0 1 10 PCICLK0 (Active / Inactive)

Publication Release Date: Nov. 1999

- 8 - Revision 0.50

6.4 Register 3: CPU Clock Register (1 = Active, 0 = Inactive)

Bit @PowerUp Pin Description

7 X - FS0# 6 1 7 3V66_0(Active / Inactive) 5 1 8 3V66_1(Active / Inactive) 4 X - FS1# 3 1 47 IOAPIC(Active / Inactive) 2 1 44 CPUCLK1 (Active / Inactive) 1 1 43 CPUCLK0 (Active / Inactive) 0 X - FS2#

6.5 Register 4: Control Register (1 = Active, 0 = Inactive)

Bit @PowerUp Pin Description

7 0 6 0 5 0 4 0 3 0 -

2 0 1 0 0

0 - Reserved

SSEL3 (Frequency table selection by software via I2C ) SSEL2 ( Frequency table selection by software via I2C) SSEL1 ( Frequency table selection by software via I2C)

SSEL0 ( Frequency table selection by software via I2C) 0 = Selection by hardware

1 = Selection by software I2C - Bit (1,2, 4:6) SSEL4 (Frequency table selection by software via I2C )

SSEL5 (Frequency table selection by software via I2C )

W83194AR-We

PRELIMINARY

6.6 Register 5: Control Register (1 = Active, 0 = Inactive)

Bit @PowerUp Pin Description

7 0 -

6 1 - SKEW2(SDRAM to CPU Skew programming bit) 5 0 - SKEW1(SDRAM to CPU Skew programming bit) 4 0 - SKEW0(SDRAM to CPU Skew programming bit) 3 X - FS3# 2 X - FS4# 1 0 -

0 X - APIC_SEL#

0 = ±0.5% Center type Spread Spectrum Modulation 1 = ±0.75% Center type Spread Spectrum Modulation

0 = Normal 1 = Spread Spectrum enabled

Publication Release Date: Nov. 1999

- 9 - Revision 0.50

6.7 Register 6: Winbond Chip ID Register (Read Only)

Bit @PowerUp Pin Description

7 1 - Winbond Chip ID 6 0 - Winbond Chip ID 5 0 - Winbond Chip ID 4 1 - Winbond Chip ID 3 1 - Winbond Chip ID 2 0 - Winbond Chip ID 1 0 - Winbond Chip ID 0 0 - Winbond Chip ID

6.8 Register 7: Winbond Chip ID Register (Read Only)

Bit @PowerUp Pin Description

7 0 - Winbond Chip ID

W83194AR-We

PRELIMINARY

6 0 - Winbond Chip ID 5 0 - Winbond Chip ID 4 1 - Winbond Chip ID 3 0 - Winbond Chip ID 2 0 - Winbond Version ID 1 0 - Winbond Version ID 0 1 - Winbond Version ID

Publication Release Date: Nov. 1999

- 10 - Revision 0.50

W83194AR-We

PRELIMINARY

7.0 SPECIFICATIONS

7.1 Absolute Maximum Ratings

Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or Vdd).

Symbol Parameter Rating

Vdd , VIN

T

STG

TB TA

7.2 Electronical Characteristics---Input/Output

Voltage on any pin with respect to GND - 0.5 V to + 7.0 V

Storage Temperature Ambient Temperature

Operating Temperature

- 65°C to + 150°C

- 55°C to + 125°C 0°C to + 70°C

Vddq1=Vddq2 = Vddq3 = Vddq4 =3.3V, VddL1 =VddL2= 2.5V

, TA = 0°C to +70°C

Parameter Symbol Min Typ Max Units Test Conditions

Input Low Voltage Input High Voltage Input Low Current Input Low Current Input High Current

V

IL

V

IH

I

IL

I

IL

I

IH

Vss-0.3 0.8

2.0 Vdd+0.3

-5

-200

-5 5

Vdc Vdc

µ

A

µ

A

µ

A

No pull-up resistors Pull-up resistros

Input Capacitance CIN 5 pF Logic inputs C C Operating Supply

Current Power Down Supply

Current

6 pF Output capacitance

OUT

27 45 pF Xin and Xout

INX

I

dd3

100 MA CPU = 66.6 MHz

PCI = 33.3 Mhz with load

I

dd2

600

µ

A

Settling Time Ts 3 mS From first crossing to 1% target

freq. Delay t t

1 10 nS Output enable delay

PZH,tPZH

1 10 nS Output enable delay

PLZ,tPZH

Publication Release Date: Nov. 1999

- 11 - Revision 0.50

W83194AR-We

PRELIMINARY

7.3 Electronical Characteristics of CPU Clock

Vdd=2.5V +/- 5%; CL=10-20pF

Parameter Symbol Min Typ Max Units Test Conditions

Ouput Impedance R Ouput Impedance R Output Low Voltage

Output High Voltage Output Low Current Output High Current Pull-Up Current Min Pull-Up Current Max Rise/Fall Time Min

Between 0.4 V and 2.0 V Rise/Fall Time Max

Between 0.4 V and 2.0 V Duty Cycle Dt 45 55 % VT=1.25V Skew TSK 175 ps VT=1.25V Jitter Tsc-c 250 ps VT=1.25V

13.5 40 Ohm

DSP

13.5 40 Ohm

DSN

V

OL

V

OH

I

OL

I

OH

I

OH(min)

I

OH(max)

T

RF(min)

T

RF(max)

0.4 V IOL=1mA

2.0 V IOH=-1mA 27 30 MA

-27 -27 MA

-27 MA Vout = 1.0 V

-27 MA Vout = 2.0V

0.4 ns 10pF Load

1.6 ns 20pF Load

7.4 Electronical Characteristics of 3V66 Clock

Vdd=3.3V +/- 5%; CL=10-30pF

Parameter Symbol Min Typ Max Units Test Conditions

Ouput Impedance R Ouput Impedance R Output Low Voltage

Output High Voltage Output Low Current Output High Current Rise/Fall Time Min

Between 0.4 V and 2.0 V Rise/Fall Time Max

Between 0.4 V and 2.0 V Duty Cycle Dt 45 55 % VT=1.5V Skew TSK 175 ps VT=1.5V Jitter Tsc-c 500 ps VT=1.5V

15 55 Ohm

DSP

15 55 Ohm

DSN

V

OL

V

OH

I

OL

I

OH

RF(min)

RF(max)

T

0.55 V IOL=1mA

2.4 V IOH=-1mA 30 38 MA

-33 -33 MA

0.4 ns 10pF Load

1.6 ns 20pF Load

Publication Release Date: Nov. 1999

- 12 - Revision 0.50

7.5 Electronical Characteristics of SDRAM Clock

W83194AR-We

PRELIMINARY

Vdd=3.3V +/- 5%; CL=20-30pF

Parameter Symbol Min Typ Max Units Test Conditions

Ouput Impedance R Ouput Impedance R Output Low Voltage

Output High Voltage Output Low Current Output High Current Rise/Fall Time Min

Between 0.4 V and 2.0 V Rise/Fall Time Max

Between 0.4 V and 2.0 V

13.5 40 Ohm

DSP

13.5 40 Ohm

DSN

V

OH

I

OL

I

OH

T

RF(min)

T

RF(max)

OL

0.45 V IOL=1mA

2.4 V IOH=-1mA 54 54 MA

-54 -45 MA

0.4 ns 10pF Load

1.6 ns 20pF Load

Duty Cycle Dt 45 55 % VT=1.5V Skew TSK 250 ps VT=1.5V Jitter Tsc-c 250 ps VT=1.5V

7.6 Electronical Characteristics of PCI Clock

Vdd=3.3V +/- 5%; CL=10-30pF

Parameter Symbol Min Typ Max Units Test Conditions

Ouput Impedance R Ouput Impedance R Output Low Voltage

Output High Voltage Output Low Current Output High Current Rise/Fall Time Min

Between 0.4 V and 2.0 V Rise/Fall Time Max

Between 0.4 V and 2.0 V Duty Cycle Dt 45 55 % VT=1.5V Skew TSK 500 ps VT=1.5V Jitter Tsc-c 500 ps VT=1.5V

15 55 Ohm

DSP

15 55 Ohm

DSN

V

OL

V

OH

I

OL

I

OH

RF(min)

RF(max)

T

0.55 V IOL=1mA

2.4 V IOH=-1mA 30 38 MA

-33 -33 MA

0.5 ns 10pF Load

2.0 ns 20pF Load

Publication Release Date: Nov. 1999

- 13 - Revision 0.50

7.7 Electronical Characteristics of 48MHz, REF Clock

W83194AR-We

PRELIMINARY

Vdd=3.3V +/- 5%; CL=10-20pF

Parameter Symbol Min Typ Max Units Test Conditions

Ouput Impedance R Ouput Impedance R Output Low Voltage

Output High Voltage Output Low Current Output High Current RiseTime Fall Time Duty Cycle Dt 45 55 % VT=1.5V

Skew TSK 500 ps VT=1.5V Jitter Tsc-c 1000 ps VT=1.5V

20 55 Ohm

DSP

20 55 Ohm

DSN

V

OL

V

OH

I

OL

I

OH

T

R

T

F

0.4 V IOL=1mA

2.4 V IOH=-1mA 29 27 MA

-29 -23 MA

1.8 4 ns 10pF Load

1.7 4 ns 20pF Load

Publication Release Date: Nov. 1999

- 14 - Revision 0.50

8.0 ORDERING INFORMATION

Part Number Package Type Production Flow

W83194AR-We

48 PIN SSOP

9.0 HOW TO READ THE TOP MARKING

1st line: Winbond logo and the type number: W83194AR-We

2nd line: Tracking code 2 8051234

2

A: Internal use code

B

8051234

3rd line: Tracking code 814 G B B

G: assembly house ID; O means OSE, G means GR

W83194AR-We 28051234 814GAB

: wafers manufactured in Winbond FAB 2 : wafer production series lot number

814

: packages made in '98, week 14

: IC revision

W83194AR-We

PRELIMINARY

Commercial, 0°C to +70°C

All the trade marks of products and companies mentioned in this data sheet belong to their respective owners

.

Publication Release Date: Nov. 1999

- 15 - Revision 0.50

10.0 PACKAGE DRAWING AND DIMENSIONS

W83194AR-We

PRELIMINARY

Headquarters

No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064

Winbond Electronics (North America) Corp.

2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668

Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners

.

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale.

Publication Release Date: Nov. 1999

- 16 - Revision 0.50