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W83194AR-73
150MHZ CLOCK FOR WHITNEY CHIPSET
1.0 GENERAL DESCRIPTION
The W83194AR-73 is a Clock Synthesizer for Intel Whitney chipset. W83194AR-73 provides all
clocks required for high-speed RISC or CISC microprocessor and also provides 32 different
frequencies of CPU, SDRAM, PCI, 3V66, IOAPIC clocks frequency setting. All clocks are externally
selectable with smooth transitions.
The W83194AR-73 provides I2C serial bus interface to program the registers to enable or disable
each clock outputs and provides 0.25% center and 0-0.5% down type spread spectrum to reduce EMI.
The W83194AR-73 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30
pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as
maintaining 50¡Ó 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide
better than 0.5V /ns slew rate.
1.0 PRODUCT FEATURES
• 2 CPU clocks
• 9 SDRAM clocks for 2 DIMMs
• 8 PCI synchronous clocks.
• Optional single or mixed supply:
(VDDR = VDDP=VDDS = VDD48 = VDD3 = 3.3V, VDDA=VDDC=2.5V)
• Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns
• Smooth frequency switch with selections from 66.8 to 150MHz
• I2C 2-Wire serial interface and I2C read back
• 0.25% center and 0-0.5% down type spread spectrum
• Programmable registers to enable/stop each output and select modes
(mode as Tri-state or Normal )
• 48 MHz for USB
• 24 MHz for super I/O
• Packaged in 48-pin SSOP
Publication Release Date: May 1999
- 1 - Revision 0.40
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3.0 PIN CONFIGURATION
W83194AR-73
PRELIMINARY
REF1/*SEL_3V66
VDDR
Xin
Xout
VSS
VSS
3V66-0
3V66-1
VDD3
VDDP
PCICLK0/ *FS0
PCICLK1/ *FS1
PCICLK2/*SEL24_48#
VSS
PCICLK3
PCICLK4
PCICLK5
VDDP
PCICLK6
PCICLK7
VSS
PD#
*SDCLK
*SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VddA
IOAPIC
VDDC
CPUCLK0
CPUCLK1
VSS
VSS
SDRAM 0
SDRAM 1
SDRAM 2
VDDS
SDRAM 3
SDRAM 4
SDRAM 5
VSS
SDRAM 6
SDRAM 7
SDRAM_F
VDDS
VSS
24_48MHz/ *FS2
48MHz-0
48MHz-1/ *FS3
VDD48
Publication Release Date: May 1999
- 2 - Revision 0.30
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4.0 FREQUENCY SELECTION BY HARDWARE
W83194AR-73
PRELIMINARY
FS3 FS2 FS1 FS0 CPU(MHz) SDRAM
(MHz)
0 0 0 0 100.23 100.23 66.82
0 0 0 1 100.9 100.9 67.26 67.26 33.63 16.815
0 0 1 0 105 105 70 70 35 17.5
0 0 1 1 66.89 100.33 66.89 66.89 33.44 16.72
0 1 0 0 120 120 64 80 40 20.00
0 1 0 1 124 124 64 82.66 41.33 20.67
0 1 1 0 133.3 133.3
0 1 1 1
1 0 0 0 140 140 70 70 35 17.5
1 0 0 1 150 150 64 75 37.50 18.75
1 0 1 0 114.99 114.99 64 76.66 38.33 19.17
1 0 1 1 70 105 70 70 35 17.5
1 1 0 0 75 112.5 64 75 37.5 18.75
1 1 0 1 83.31 124.96 64 83.31 41.65 20.825
133.6 100.2 66.65 66.65
3V66 (MHz) PCI(MHz) IOAPIC
SEL_3V66=0 SEL_3V66=1
33.41 16.71
33.32 16.66
66.65
66.82
88.86 44.43 22.22
(MHz)
1 1 1 0 90 90 60 60 30 15
1 1 1 1 95 95 63.33 63.33 31.67 15.84
5.0 SERIAL CONTROL REGISTERS
The Pin column lists the affected pin number and the @PowerUp column gives the state at true
power up. Registers are set to the values shown only on true power up. "Command Code" byte and
"Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data
(bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge.
After that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and
acknowledged.
Publication Release Date: May 1999
- 3 - Revision 0.30
Page 4
W83194AR-73
PRELIMINARY
5.1 Register 0: CPU Frequency Select Register
Bit @PowerUp Pin Description
7 0 6 0 - SSEL2 ( Frequency table selection by software via I2C)
5 0 - SSEL1 ( Frequency table selection by software via I2C)
4 0 - SSEL0 ( Frequency table selection by software via I2C)
3 0 - 0 = Selection by hardware
2 0 - SSEL3 (Frequency table selection by software via I2C )
1 0 - 0 = Normal
0 0 - 0 = Running
0 = ¡Ó0.25% Center type Spread Spectrum Modulation
1 = 0~ 0.5% Down type Spread Spectrum Modulation
1 = Selection by software I2C - Bit (2, 6:4), Register1 Bit1
1 = Spread Spectrum enabled
1 = Tristate all outputs
5.2 Register 1 : CPU Clock Register (1 = Active, 0 = Inactive)
Bit @PowerUp Pin Description
7
6
5
4 1 28 24_48MHz(Active / Inactive)
3 1 27 48MHz-0(Active / Inactive)
2 1 26 48MHz-1(Active / Inactive)
1
0 1 31 SDRAM_F(Active / Inactive)
X - FS3#
X - FS0#
X - FS2#
1 - SEL_3V66(Frequency table selection by software via I2C )
5.3 Register 2: SDRAM Clock Register (1 = Active, 0 = Inactive)
Bit @PowerUp Pin Description
7 1 32 SDRAM7 (Active / Inactive)
6 1 33 SDRAM6 (Active / Inactive)
5 1 35 SDRAM5 (Active / Inactive)
4 1 36 SDRAM4 (Active / Inactive)
3 1 37 SDRAM3 (Active / Inactive)
2 1 39 SDRAM2 (Active / Inactive)
1 1 40 SDRAM1 (Active / Inactive)
0 1 41 SDRAM0 (Active / Inactive)
Publication Release Date: May 1999
- 4 - Revision 0.30
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5.4 Register 3: PCI Clock Register (1 = Active, 0 = Inactive)
Bit @PowerUp Pin Description
7 1 20 PCICLK7 (Active / Inactive)
6 1 19 PCICLK6 (Active / Inactive)
5 1 17 PCICLK5 (Active / Inactive)
4 1 16 PCICLK4 (Active / Inactive)
3 1 15 PCICLK3 (Active / Inactive)
2 1 13 PCICLK2 (Active / Inactive)
1 1 12 PCICLK1 (Active / Inactive)
0 1 11 PCICLK0 (Active / Inactive)
5.5 Register 4: Additional Register (1 = Active, 0 = Inactive)
Bit @PowerUp Pin Description
7
6 1 8 3V66_1(Active / Inactive)
5 1
4
3 1 47
2
1
0
X
0
X
1 44 CPUCLK1(Active / Inactive)
1 45 CPUCLK0(Active / Inactive)
- SEL_3V66#
7 3V66_0(Active / Inactive)
- Reserve
IOAPIC (Active / Inactive)
- FS1#
W83194AR-73
PRELIMINARY
5.6 Register 5: Reserve Register
Bit @PowerUp Pin Description
7 0 - Reserve
6 0 - Reserve
5 0 - Reserve
4 0 - Reserve
3 0 - Reserve
2 0 - Reserve
1 0 - Reserve
0 0 - Reserve
- 5 - Revision 0.30
Publication Release Date: May 1999
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5.7 Register 6: Winbond Chip ID Register (Read Only)
Bit @PowerUp Pin Description
7 1 - Winbond Chip ID
6 0 - Winbond Chip ID
5 0 - Winbond Chip ID
4 1 - Winbond Chip ID
3 0 - Winbond Chip ID
2 0 - Winbond Chip ID
1 1 - Winbond Chip ID
0 0 - Winbond Chip ID
5.8 Register 7: Winbond Chip ID Register (Read Only)
Bit @PowerUp Pin Description
W83194AR-73
PRELIMINARY
7 0 - Winbond Chip ID
6 0 - Winbond Chip ID
5 0 - Winbond Chip ID
4 0 - Winbond Chip ID
3 0 - Winbond Chip ID
2 0 - Winbond Chip ID
1 1 - Winbond Chip ID
0 0 - Winbond Chip ID
Publication Release Date: May 1999
- 6 - Revision 0.30
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W83194AR-73
PRELIMINARY
6.0 SPECIFICATIONS
6.1 ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in this table may cause permanent damage to the device.
Precautions should be taken to avoid application of any voltage higher than the maximum rated
voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability.
Unused inputs must always be tied to an appropriate logic voltage level (Ground or Vdd).
Symbol Parameter Rating
Vdd , V
T
STG
T
B
T
A
IN
Voltage on any pin with respect to GND - 0.5 V to + 7.0 V
Storage Temperature
Ambient Temperature
Operating Temperature
- 65°C to + 150°C
- 55°C to + 125°C
0°C to + 70°C
6.2 AC CHARACTERISTICS
VddR=Vdd3=VddP=VddS=3.3V ± 5 %, VddC = VddA= 2.375V~2.9V , TA = 0°C to +70°C
Parameter Symbol Min Typ Max Units Test Conditions
Output Duty Cycle 45 50 55 % Measured at 1.5V
CPU/SDRAM to PCI Offset
Skew (CPU-CPU), (PCIPCI), (SDRAM-SDRAM)
CPU/SDRAM
t
OFF
t
SKEW
t
CCJ
Cycle to Cycle Jitter
CPU/SDRAM
t
JA
Absolute Jitter
Jitter Spectrum 20 dB
BWJ 500 KHz
Bandwidth from Center
Output Rise (0.4V ~ 2.0V)
& Fall (2.0V ~0.4V) Time
Overshoot/Undershoot
t
TLH
t
THL
Vover 0.7 1.5 V
Beyond Power Rails
Ring Back Exclusion VRBE 0.7 2.1 V Ring Back must not enter this
1 4 ns 15 pF Load Measured at 1.5V
250 ps 15 pF Load Measured at 1.5V
¡Ó
250 ps
500 ps
0.4 1.6 ns 15 pF Load on CPU and PCI
outputs
22 Ω at source of 8 inch PCB
run to 15 pF load
range.
Publication Release Date: May 1999
- 7 - Revision 0.30
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W83194AR-73
IL
dc
IH
dc
IL
IL
IH
DD
DDPD
IN
OUT
INX
Tra
STA
PRELIMINARY
6.3 DC CHARACTERISTICS
VddR=Vdd3=VddP=VddS=3.3V ± 5 %, VddC = VddA= 2.375V~2.9V , TA = 0°C to +70°C
Parameter Symbol Min Typ Max Units Test Conditions
Input Low Voltage
V
Vss-
0.8
V
0.3
Input High Voltage
V
2.0 Vdd
V
+0.3
Input Low Current
I
-5 2.0
µA
(no pull-up Resistors)
Input Low Current
I
-200 -100
µA
(pull-up Resistors)
Input High Current
Operating Current I
Power Down Current I
I
-5 5
60 100 mA @66M
400 600
µA
µA
CL= 0pF
Input Frequency Fi 14.318 MHz Vdd=3.3V
Pin Inductance Lpin 7 nH
Input Capacitance C
C
C
Transition Time T
6 pF Output pins capacitance
13.5 22.5 pF X1 & X2 pins
5 pF Logic Inputs
3 mS
Disable/Enable Delay T 1 10 nS
Clock stabilization T
3 mS
Publication Release Date: May 1999
- 8 - Revision 0.30
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7.0 ORDERING INFORMATION
Part Number Package Type Production Flow
W83194AR-73
PRELIMINARY
W83194AR-73 48 PIN SSOP
8.0 HOW TO READ THE TOP MARKING
W83194AR-73
28051234
814GBB
1st line: Winbond logo and the type number: W83194AR-73
2nd line: Tracking code 2 8051234
2: wafers manufactured in Winbond FAB 2
8051234: wafer production series lot number
3rd line: Tracking code 814 G B B
814: packages made in '98, week 14
G: assembly house ID; A means ASE, S means SPIL, G means GR
BB: IC revision
Commercial, 0°C to +70°C
All the trade marks of products and companies mentioned in this data sheet belong to their
respective owners.
Publication Release Date: May 1999
- 9 - Revision 0.30
Page 10
9.0 PACKAGE DRAWING AND DIMENSIONS
W83194AR-73
PRELIMINARY
Headquarters
No. 4, Creation Rd. III
Science-Based Industrial Park
Hsinchu, Taiwan
TEL: 886-35-770066
FAX: 886-35-789467
www: http://www.winbond.com.tw/
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502
TLX: 16485 WINTPE
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II
123 Hoi Bun Rd., Kwun Tong
Kowloon, Hong Kong
TEL: 852-27516023-7
FAX: 852-27552064
Winbond Electronics
(North America) Corp.
2730 Orchard Parkway
San Jose, CA 95134 U.S.A.
TEL: 1-408-9436666
FAX: 1-408-9436668
Please note that all data and specifications are subject to change without notice. All the trade
marks of products and companies mentioned in this data sheet belong to their respective
owners.
These products are not designed for use in life support appliances, devices, or systems
where malfunction of these products can reasonably be expected to result in personal injury.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sale.
Publication Release Date: May 1999
- 10 - Revision 0.30
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