Datasheet W78LE58P-24, W78LE58F-24, W78LE58-24 Datasheet (Winbond Electronics)

Preliminary W78LE58

8-BIT MICROCONTROLLER

GENERAL DESCRIPTION

The W78LE58 is an 8-bit microcontroller which has an in-system programmable MTP-ROM for
firmware updating. The instruction set of the W78LE58 is fully compatible with the standard 8052.
The W78LE58 contains a 32K bytes of main MTP-ROM and a 4K bytes of auxiliary MTP-ROM which
allows the contents of the 32KB main MTP-ROM to be updated by the loader program located at the
4KB auxiliary MTP-ROM; 512 bytes of on-chip RAM; four 8-bit bi-directional and bit-addressable I/O
ports; an additional 4-bit port P4; three 16-bit timer/counters; a serial port. These peripherals are
supported by a eight sources two-level interrupt capability. To facilitate programming and verification,
the MTP-ROM inside the W78LE58 allows the program memory to be programmed and read
electronically. Once the code is confirmed, the user can protect the code for security.

The W78LE58 microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.

FEATURES

•

Fully static design 8-bit CMOS microcontroller

•

32K bytes of in-system programmable MTP-ROM for Application Program (APROM)

•

4K bytes of auxiliary MTP-ROM for Loader Program (LDROM)

•

512 bytes of on-chip RAM. (including 256 bytes of AUX-RAM, software selectable)

•

64K bytes program memory address space and 64K bytes data memory address space

•

Four 8-bit bi-directional ports

•

One 4-bit multipurpose programmable port

•

Three 16-bit timer/counters

•

One full duplex serial port

•

Eight-sources, two-level interrupt capability

•

Built-in power management

•

Code protection

•

Packaged in

− DIP 40: W78LE58-24

− PLCC 44: W78LE58P-24

− QFP 44: W78LE58F-24

Publication Release Date: June 2000

- 1 - Revision A1

PIN CONFIGURATIONS

40-Pin DIP (W78LE58)

T2, P1.0

T2EX, P1.1

P1.2
P1.3
P1.4
P1.5
P1.6
P1.7

RST
RXD, P3.0
TXD, P3.1

INT0, P3.2
INT1, P3.3

T0, P3.4
T1, P3.5

WR, P3.6

RD, P3.7

XTAL2
XTAL1

VSS

Preliminary W78LE58

VDD1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

40
39

P0.0, AD0

P0.1, AD1

38
37

P0.2, AD2

P0.3, AD3

36
35

P0.4, AD4

P0.5, AD5

34
33

P0.6, AD6

32

P0.7, AD7

31

EA

30

ALE

29

PSEN

28

P2.7, A15

27

P2.6, A14

26

P2.5, A13

25

P2.4, A12

24

P2.3, A11

23

P2.2, A10

22

P2.1, A9

21

P2.0, A8

44-Pin PLCC (W78LE58P) 44-Pin QFP (W78LE58F)

/

T

P1.5
P1.6
P1.7

RST

RXD, P3.0

INT2, P4.3

TXD, P3.1
INT0, P3.2
INT1, P3.3

T0, P3.4
T1, P3.5

P

P

1

1

.

.

3

4

6 5 4 3

7
8
9
10
11
12
13
14
15
16

17

P

P

3

3

.

.

7

6

,

,

/

/

R

W

D

R

2
E
X
,

P

P
1

1

.

.
2

1

X

X

T

T

A

A

L

L

1

2

I
N

T

T

2

3

,

,

P

P

1

V

4

.

D

.

0

D

2

2 1 44 43 42

V

P

P

S

2

4

S

.

.

0

0

,
A
8

A

A

A

A

D

D

D

D

3

2

1

0

,

,

,

,

P

P

P

P

0

0

0

0

.

.

.

.

3

2

1

0

40

41

39

P0.4, AD4

38

P0.5, AD5

37

P0.6, AD6

36

P0.7, AD7

35

EA

34

P4.1

33

ALE

32

PSEN

31

P2.7, A15

30

P2.6, A14

29

P2.5, A13

2827262524232221201918

P

P

P

P

2

2

2

2

.

.

.

.

4

3

2

1

,

,

,

,

A

A

A

A

1

1

1

9

2

1

0

P1.5
P1.6
P1.7

RST
RXD, P3.0
INT2, P4.3

TXD, P3.1
INT0, P3.2
INT1, P3.3

T0, P3.4
T1, P3.5

/

T

I

2

N

T

E

T

2

X

3

,

,

,

P

P

P

P

P

1

1

.

.

3

4

43 42 41

44

1
2

3

4
5
6
7
8
9
10

11

P

P

3

3

.

.

7

6

,

,

/

/

R

W

D

R

1

1

1

.

.

.

0

2

1

40 39 38 37 36 35

X

V

X

T

S

T

A

S

A

L

L

1

2

P

V

4

D

.

D

2

P

P

2

4

.

.

0

0

,
A
8

A

A

A

A

D

D

D

D

3

1

2

0

,

,

,

,

P

P

P

P

0

0

0

0

.

.

.

.

3

2

1

0

34

33

P0.4, AD4

32

P0.5, AD5

31

P0.6, AD6

30

P0.7, AD7

29

EA

28

P4.1

27

ALE

26

PSEN

25

P2.7, A15

24

P2.6, A14

23

P2.5, A13

2221201918171615141312

P

P

P

P

2

2

2

2

.

.

.

.

4

3

2

1

,

,

,

,

A

A

A

A

1

1

1

9

2

1

0

- 2 -

PIN DESCRIPTION

EA

Preliminary W78LE58

SYMBOL TYPE

P0.0−P0.7
P1.0−P1.7
P2.0−P2.7

P3.0−P3.7
P4.0−P4.3

PSEN

ALE O H ADDRESS LATCH ENABLE: ALE is used to enable the address latch that

RST I L RESET: A high on this pin for two machine cycles while the oscillator is

XTAL1 I CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an

XTAL2 O CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1.

SS

V

DD

V

I EXTERNAL ACCESS ENABLE: This pin forces the processor to execute the

external ROM. The ROM address and data will not be presented on the bus if
the EA pin is high.

O H

I/O D PORT 0: Function is the same as that of standard 8052.
I/O H PORT 1: Function is the same as that of standard 8052.
I/O H PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also

I/O H PORT 3: Function is the same as that of the standard 8052.
I/O H PORT 4: A bi-directional I/O. See details below.

PROGRAM STORE ENABLE: PSEN enables the external ROM data in the
Port 0 address/data bus. When internal ROM access is performed, no

strobe signal outputs originate from this pin.

separates the address from the data on Port 0. ALE runs at 1/6th of the
oscillator frequency.

running resets the device.

external clock.

I GROUND: ground potential.
I POWER SUPPLY: Supply voltage for operation.

provides the upper address bits for accesses to external memory.

DESCRIPTIONS

PSEN

* Note:

I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain

TYPE

Publication Release Date: June 2000

- 3 - Revision A1

BLOCK DIAGRAM

Preliminary W78LE58

P1.0

P1.7

P3.0

P3.7

P4.0
P4.3

Port

Interrupt

UART

Port 1
Latch

Timer

Timer

Timer

Port 3
Latch

Port 4
Latch

2

0

1

XTAL1

Oscillator

ACC

PSW

Instruction

Decoder

&

Sequencer

Bus & Clock

Controller

ALE

PSEN

ALU

SFR RAM

Address

512 bytes

RAM & SFR

Reset Block

B

T2T1

Stack

Pointer

Power control

VssVCCRSTXTAL2

Port 0

Latch

DPTR

Temp Reg.

PC

Incrementor

Addr. Reg.

32KB

MTP-ROM

MTP-ROM

4KB

Port 2

Latch

Port
0

Port
2

P0.0

P0.7

P2.0

P2.7

1

Port

3

Port

4

FUNCTIONAL DESCRIPTION

The W78LE58 architecture consists of a core controller surrounded by various registers, four general
purpose I/O ports, one special purpose programmable 4-bits I/O port, 512 bytes of RAM, three
timer/counters, a serial port. The processor supports 111 different opcodes and references both a 64K
program address space and a 64K data storage space.

RAM

The internal data RAM in the W78LE58 is 512 bytes. It is divided into two banks: 256 bytes of
scratchpad RAM and 256 bytes of AUX-RAM. These RAMs are addressed by different ways.

•

RAM 0H−7FH can be addressed directly and indirectly as the same as in 8051. Address pointers

are R0 and R1 of the selected register bank.

•

RAM 80H−FFH can only be addressed indirectly as the same as in 8051. Address pointers are R0,
R1 of the selected registers bank.

- 4 -

Preliminary W78LE58

•

AUX-RAM 0H−FFH is addressed indirectly as the same way to access external data memory with
the MOVX instruction. Address pointer are R0 and R1 of the selected register bank and DPTR
register. An access to external data memory locations higher than FFH will be performed with the
MOVX instruction in the same way as in the 8051. The AUX-RAM is disable after a reset. Setting
the bit 4 in CHPCON register will enable the access to AUX-RAM. When AUX-RAM is enabled the
instructions of "MOVX @Ri" will always access to on-chip AUX-RAM. When executing from internal

program memory, an access to AUX-RAM will not affect the Ports P0, P2, WR and RD.
Example,
CHPENR REG F6H

CHPCON REG BFH
MOV CHPENR ,#87H
MOV CHPENR,#59H
ORL CHPCON,#00010000B ; enable AUX-RAM
MOV CHPENR,#00H
MOV R0,#12H
MOV A,#34H
MOVX @R0,A ; Write 34h data to 12h address.

Timers 0, 1, and 2

Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer
0, TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer
1 are the same as in the W78C51. Timer 2 is a 16-bit timer/counter that is configured and controlled
by the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter
or as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating
modes: capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload
mode is the same as that of Timers 0 and 1.

Clock

The W78LE58 is designed with either a crystal oscillator or an external clock. Internally, the clock is
divided by two before it is used by default. This makes the W78LE58 relatively insensitive to duty
cycle variations in the clock.

Crystal Oscillator

The W78LE58 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be
connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each
pin to ground.

External Clock

An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator.

Publication Release Date: June 2000

- 5 - Revision A1

Preliminary W78LE58

INT1

Power Management

Idle Mode

Setting the IDL bit in the PCON register enters the idle mode. In the idle mode, the internal clock to
the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.

Power-down Mode

When the PD bit in the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks are stopped, including the oscillator. To exit from power-down mode is by a

hardware reset or external interrupts INT0 to

Reduce EMI Emission

The W78LE58 allows user to diminish the gain of on-chip oscillator amplifier by using programmer to
clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be decreased. Care must
be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may affect
the external crystal operating improperly at high frequency. The value of C1 and C2 may need some
adjustment while running at lower gain.

Reset

The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the W78LE58 is used with an external RC network. The reset logic also
has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are
initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the
other SFR registers except SBUF to 00H. SBUF is not reset.

when enabled and set to level triggered.

W78LE58 Special Function Registers (SFRs) and Reset Values

F8

F0 +B

E8

E0 +ACC

D8

D0 +PSW

C8 +T2CON

C0 XICON

B8 +IP

B0 +P3

00000000

00000000

+P4

xxxx1111

00000000

00000000

00000000

00000000

00000000

RCAP2L

00000000

P4CONA

00000000

RCAP2H

00000000

P4CONB

00000000

TL2

00000000

SFRAL

00000000

P43AL

00000000

00000000

SFRAH

00000000

P43AH

00000000

- 6 -

TH2

CHPENR

00000000

SFRFD

00000000

SFRCN
00000000
CHPCON
0xx00000

FF

F7

EF

E7

DF

D7

CF

C7

BF

B7

Preliminary W78LE58

INT3

INT2

INT2

INT2

CLR

Continued

A8 +IE

00000000

A0 +P2

11111111

98 +SCON

00000000

90 +P1

11111111

88 +TCON

00000000

80 +P0

11111111

Notes:

1.The SFRs marked with a plus sign(+) are both byte- and bit-addressable.

2. The text of SFR with bold type characters are extension function registers.

SBUF

xxxxxxxx

TMOD

00000000

SP

00000111

TL0

00000000

DPL

00000000

TL1

00000000

DPH

00000000

P42AL

00000000

P41AL

00000000

TH0

00000000

P40AL

00000000

P42AH

00000000

P41AH

00000000

TH1

00000000

P40AH

00000000

P2ECON

0000xx00

Port 4

Port 4, address D8H, is a 4-bit multipurpose programmable I/O port. Each bit can be configured
individually by software. The Port 4 has four different operation modes.

Mode 0: P4.0−P4.3 is a bi-directional I/O port which is same as port 1. P4.2 and P4.3 also serve as

external interrupt

and

if enabled.

PCON

00110000

AF

A7

9F

97

8F

87

Mode 1: P4.0−P4.3 are read strobe signals that are synchronized with RD signal at specified
addresses. These signals can be used as chip-select signals for external peripherals.

Mode 2: P4.0−P4.3 are write strobe signals that are synchronized with WRsignal at specified
addresses. These signals can be used as chip-select signals for external peripherals.

Mode 3: P4.0−P4.3 are read/write strobe signals that are synchronized with RD or WRsignal at
specified addresses. These signals can be used as chip-select signals for external
peripherals.

When Port 4 is configured with the feature of chip-select signals, the chip-select signal address range
depends on the contents of the SFR P4xAH, P4xAL, P4CONA and P4CONB. The registers P4xAH
and P4xAL contain the 16-bit base address of P4.x. The registers P4CONA and P4CONB contain the
control bits to configure the Port 4 operation mode.

INT3

/

Two additional external interrupts,

and

INT3

, whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register
is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To

set/clear bits in the XICON register, one can use the "SETB (

) bit" instruction. For example,

"SETB 0C2H" sets the EX2 bit of XICON.

Publication Release Date: June 2000

- 7 - Revision A1

Preliminary W78LE58

XICON - external interrupt control (C0H)

PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2

PX3: External interrupt 3 priority high if set
EX3: External interrupt 3 enable if set
IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software

Eight-source interrupt information:

INTERRUPT
SOURCE

External Interrupt 0 03H 0 (highest) IE.0 TCON.0
Timer/Counter 0 0BH 1 IE.1 ­External Interrupt 1 13H 2 IE.2 TCON.2
Timer/Counter 1 1BH 3 IE.3 ­Serial Port 23H 4 IE.4 ­Timer/Counter 2 2BH 5 IE.5 ­External Interrupt 2 33H 6 XICON.2 XICON.0
External Interrupt 3 3BH 7 (lowest) XICON.6 XICON.3

VECTOR
ADDRESS

POLLING
SEQUENCE WITHIN
PRIORITY LEVEL

ENABLE
REQUIRED
SETTINGS

INTERRUPT
TYPE
EDGE/LEVEL

P4CONB (C3H)

BIT NAME FUNCTION

7, 6 P43FUN1

P43FUN0

00: Mode 0. P4.3 is a general purpose I/O port which is the same as Port1.
01: Mode 1. P4.3 is a Read Strobe signal for chip select purpose. The address

range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0.
10: Mode 2. P4.3 is a Write Strobe signal for chip select purpose. The address

range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0.
11: Mode 3. P4.3 is a Read/Write Strobe signal for chip select purpose. The

address range depends on the SFR P43AH, P43AL, P43CMP1, and
P43CMP0.

- 8 -

P4CONB (C3H), continued

A8) of address bus with the base address

BIT NAME FUNCTION

5, 4 P43CMP1

P43CMP0

3, 2 P42FUN1

P42FUN0

1, 0 P42CMP1

P42CMP0

Chip-select signals address comparison:
00: Compare the full address (16 bits length) with the base address register

P43AH, P43AL.
01: Compare the 15 high bits (A15−A1) of address bus with the base address

register P43AH, P43AL.
10: Compare the 14 high bits (A15−A2) of address bus with the base address

register P43AH, P43AL.
11: Compare the 8 high bits (A15−

register P43AH, P43AL.
The P4.2 function control bits which are the similar definition as P43FUN1,

P43FUN0.
The P4.2 address comparator length control bits which are the similar

definition as P43CMP1, P43CMP0.

P4CONA (C2H)

BIT NAME FUNCTION

7, 6 P41FUN1

P41FUN0

5, 4 P41CMP1

P41CMP0

3, 2 P40FUN1

P40FUN0

1, 0 P40CMP1

P40CMP0

The P4.1 function control bits which are the similar definition as P43FUN1,
P43FUN0.

The P4.1 address comparator length control bits which are the similar
definition as P43CMP1, P43CMP0.

The P4.0 function control bits which are the similar definition as P43FUN1,
P43FUN0.

The P4.0 address comparator length control bits which are the similar
definition as P43CMP1, P43CMP0.

Preliminary W78LE58

P2ECON (AEH)

BIT NAME FUNCTION

7 P43CSINV The active polarity of P4.3 when pin P4.3 is defined as read and/or write strobe

signal.
= 1: P4.3 is active high when pin P4.3 is defined as read and/or write strobe signal.

= 0: P4.3 is active low when pin P4.3 is defined as read and/or write strobe signal.
6 P42CSINV The similarity definition as P43SINV.
5 P41CSINV The similarity definition as P43SINV.
4 P40CSINV The similarity definition as P43SINV.
3 - Reserve
2 - Reserve
1 - 0
0 - 0

Publication Release Date: June 2000

- 9 - Revision A1

Preliminary W78LE58

Port 4 Base Address Registers
P40AH, P40AL:

The Base address register for comparator of P4.0. P40AH contains the high-order byte of address,
P40AL contains the low-order byte of address.

P41AH, P41AL:

The Base address register for comparator of P4.1. P41AH contains the high-order byte of address,
P41AL contains the low-order byte of address.

P42AH, P42AL:

The Base address register for comparator of P4.2. P42AH contains the high-order byte of address,
P42AL contains the low-order byte of address.

P43AH, P43AL:

The Base address register for comparator of P4.3. P43AH contains the high-order byte of address,
P43AL contains the low-order byte of address.

P4 (D8H)

BIT NAME FUNCTION

7 - Reserve
6 - Reserve
5 - Reserve
4 - Reserve
3 P43 Port 4 Data bit which outputs to pin P4.3 at mode 0.
2 P42 Port 4 Data bit. which outputs to pin P4.2 at mode 0.
1 P41 Port 4 Data bit. which outputs to pin P4.1at mode 0.
0 P40 Port 4 Data bit which outputs to pin P4.0 at mode 0.

Here is an example to program the P4.0 as a write strobe signal at the I/O port address
1234H−1237H and positive polarity, and P4.1−P4.3 are used as general I/O ports.

MOV P40AH,#12H
MOV P40AL,#34H ; Base I/O address 1234H for P4.0
MOV P4CONA,#00001010B ; P4.0 a write strobe signal and address line A0 and A1 are masked.
MOV P4CONB,#00H ; P4.1−P4.3 as general I/O port which are the same as PORT1
MOV P2ECON,#10H ; Write the P40SINV = 1 to inverse the P4.0 write strobe polarity

MOV CHPENR,#00H ; Disable CHPCON write attribute.

Then any instruction MOVX @DPTR,A (with DPTR = 1234H−1237H) will generate the positive
polarity write strobe signal at pin P4.0. And the instruction MOV P4,#XX will output the bit3 to bit1 of
data #XX to pin P4.3−P4.1.

; default is negative.

- 10 -

Preliminary W78LE58

P4xCSINV

P4xFUN0
P4xFUN1

P4.x INPUT DATA BUS

DATA I/O

RD_CS

MUX 4->1

WR_CS

RD/WR_CS

PIN

P4.x

ADDRESS BUS

REGISTER
P4xAL
P4xAH

P4 REGISTER

READ
WRITE

P4.x

EQUAL

Bit Length

REGISTER
P4xCMP0
P4xCMP1

Selectable
comparator

In-System Programming (ISP) Mode

The W78LE58 equips one 32K byte of main MTP-ROM bank for application program (called APROM)
and one 4K byte of auxiliary MTP-ROM bank for loader program (called LDROM). In the normal
operation, the microcontroller executes the code in the APROM. If the content of APROM needs to be
modified, the W78LE58 allows user to activate the In-System Programming (ISP) mode by setting the
CHPCON register.

values 87H, then 59H sequentially to the CHPENR register to enable the CHPCON write
attribute. Writing CHPENR register with the values except 87H and 59H will close CHPCON
register write attribute.

enter/exit ISP Mode, program, erase, read ... etc, during device in the idle mode. Setting the bit
CHPCON.0 the device will enter in-system programming mode after a wake-up from idle mode.
Because device needs proper time to complete the ISP operations before awaken from idle mode,
software may use timer interrupt to control the duration for device wake-up from idle mode. To
perform ISP operation for revising contents of APROM, software located at APROM setting the
CHPCON register then enter idle mode, after awaken from idle mode the device executes the
corresponding interrupt service routine in LDROM. Because the device will clear the program counter
while switching from APROM to LDROM, the first execution of RETI instruction in interrupt service
routine will jump to 00H at LDROM area. The device offers a software reset for switching back to
APROM while the content of APROM has been updated completely. Setting CHPCON register bit 0,

1 and 7 to logic-1 will result a software reset to reset the CPU

external reset. This in-system programming feature makes the job easy and efficient in which the
application needs to update firmware frequently. In some applications, the in-system programming
feature make it possible to easily update the system firmware without opening the chassis.

The CHPCON is read-only by default, software must write two specific

The W78LE58 achieves all in-system programming operations including

. The software reset serves as a

Note: The ISP Mode operates by supply voltage from 3.3V to 5.5V.

Publication Release Date: June 2000

- 11 - Revision A1

Preliminary W78LE58

SFRAH, SFRAL:

SFRFD:
SFRCN:

The programming data for on-chip MTP-ROM in programming mode.

The control byte of on-chip MTP-ROM programming mode.

The objective address of on-chip MTP-ROM in the in-system programming mode.
SFRAH contains the high-order byte of address, SFRAL contains the low-order
byte of address.

SFRCN (C7)

BIT NAME FUNCTION

7 - Reserve.
6 WFWIN On-chip MTP-ROM bank select for in-system programming.

= 0: 32K bytes MTP-ROM bank is selected as destination for re­ programming.

= 1: 4K bytes MTP-ROM bank is selected as destination for re-

programming.
5 OEN MTP-ROM output enable.
4 CEN MTP-ROM chip enable.

3, 2, 1, 0 CTRL[3:0] The flash control signals

MODE WFWIN CTRL<3:0> OEN CEN SFRAH, SFRAL SFRFD

Erase 32KB APROM 0 0010 1 0 X X
Program 32KB APROM 0 0001 1 0 Address in Data in
Read 32KB APROM 0 0000 0 0 Address in Data out
Erase 4KB LDROM 1 0010 1 0 X X
Program 4KB LDROM 1 0001 1 0 Address in Data in
Read 4KB LDROM 1 0000 0 0 Address in Data out

- 12 -

In-System Programming Control Register (CHPCON)

0: The Loader Program locates at the 32 KB APROM. 4KB LDROM is

CHPCON (BFH)

BIT NAME FUNCTION

7 SWRESET

(F04KMODE)

6 - Reserve.
5 - Reserve.

ENAUXRAM

4

3 0 Must set to 0.
2 0 Must set to 0.
1 FBOOTSL The Program Location Select.

When this bit is set to 1, and both FBOOTSL and FPROGEN are set to 1. It
will enforce microcontroller reset to initial condition just like power on reset.
This action will re-boot the microcontroller and start to normal operation. To
read this bit in logic-1 can determine that the F04KBOOT mode is running.

1: Enable on-chip AUX-RAM.
0: Disable the on-chip AUX-RAM

Preliminary W78LE58

0 FPROGEN MTP-ROM Programming Enable.

destination for re-programming.
1: The Loader Program locates at the 4 KB memory bank. 32KB APROM is

destination for re-programming.

= 1: enable. The microcontroller enter the in-system programming mode after
entering the idle mode and wake-up from interrupt. During in-system
programming mode, the operation of erase, program and read are
achieve when device enters idle mode.

= 0: disable. The on-chip flash memory is read-only. In-system
programmability is disabled.

F04KBOOT Mode (Boot From LDROM)

By default, the W78LE58 boots from APROM program after a power on reset. On some occasions,
user can force the W78LE58 to boot from the LDROM program via following settings. The possible
situation that you need to enter F04KBOOT mode when the APROM program can not run properly
and device can not jump back to LDROM to execute in-system programming function. Then you can
use this F04KBOOT mode to force the W78LE58 jumps to LDROM and executes in-system
programming procedure. When you design your system, you may reserve the pins P2.6, P2.7 to
switches or jumpers. For example in a CD-ROM system, you can connect the P2.6 and P2.7 to PLAY
and EJECT buttons on the panel. When the APROM program fails to execute the normal application
program. User can press both two buttons at the same time and then turn on the power of the
personal computer to force the W78LE58 to enter the F04KBOOT mode. After power on of personal
computer, you can release both buttons and finish the in-system programming procedure to update

the APROM code. In application system design, user must take care of the P2, P3, ALE, EA and

PSEN

pin value at reset to prevent from accidentally activating the programming mode or

F04KBOOT mode.

Publication Release Date: June 2000

- 13 - Revision A1

F04KBOOT MODE

P4.3 P2.7 P2.6 MODE

X L L FO4KBOOT

L X X FO4KBOOT

The Reset Timing For Entering

Preliminary W78LE58

F04KBOOT Mode

P2.7

P2.6

RST

Hi-Z

Hi-Z

30 mS

10 mS

- 14 -

START

The Algorithm of In-System Programming

Preliminary W78LE58

Part 1:32KB APROM

procedure of entering

In-System Programming Mode

Enter In-System

Programming Mode ?

(conditions depend on

user's application)

Yes

Setting control registers

MOV CHPENR,#87H
MOV CHPENR,#59H

MOV CHPCON,#03H

Setting Timer (about 1.5 us)

and enable timer interrupt

Start Timer and enter idle Mode.

(CPU will be wakened from idle mode

by timer interrupt, then enter In-System

Programming mode)

No

Execute the normal application

program

END

CPU will be wakened by interrupt and
re-boot from 4KB LDROM to execute

the loader program.

Go

- 15 - Revision A1

Publication Release Date: June 2000

Preliminary W78LE58

Go

Timer Interrupt Service Routine:

Stop Timer & disable interrupt

Is F04KBOOT Mode?

(CHPCON.7=1)

No

Setting Timer and enable Timer

interrupt for wake-up .

(15 ms for erasing operation)

Setting erase operation mode:

MOV SFRCN,#22H

(Erase 32KB APROM)

Start Timer and enter IDLE

Mode.

(Erasing...)

Yes

Reset the CHPCON Register:

MOV CHPENR,#87H
MOV CHPENR,#59H

MOV CHPCON,#03H

PGM

End of Programming ?

No

Setting Timer and enable Timer

interrupt for wake-up .

(50us for program operation)

Get the parameters of new code

(Address and data bytes)

through I/O ports, UART or

other interfaces.

Setting control registers for

programming:

MOV SFRAH,#ADDRESS_H
MOV SFRAL,#ADDRESS_L
MOV SFRFD,#DATA
MOV SFRCN,#21H

Part 2: 4KB LDROM

Procedure of Updating

the 32KB APROM

Yes

Is currently in the

F04KBOOT Mode ?

No

Software reset CPU and
re-boot from the 32KB
APROM.

MOV CHPENR,#87H
MOV CHPENR,#59H
MOV CHPCON,#83H

Yes

Hardware Reset
to re-boot from

new 32 KB APROM.

(S/W reset is

invalid in F04KBOOT

Mode)

End of erase

operation. CPU will

be wakened by Timer

interrupt.

PGM

- 16 -

END

Executing new code

from address

00H in the 32KB APROM.

Preliminary W78LE58

SECURITY

During the on-chip MTP-ROM programming mode, the MTP-ROM can be programmed and verified
repeatedly. Until the code inside the MTP-ROM is confirmed OK, the code can be protected. The
protection of MTP-ROM and those operations on it are described below.

The W78LE58 has several Special Setting Registers, including the Security Register and
Company/Device ID Registers, which can not be accessed in programming mode. Those bits of the
Security Registers can not be changed once they have been programmed from high to low. They can
only be reset through erase-all operation. The contents of the Company ID and Device ID registers
have been set in factory. The Security Register is located at the 0FFFFH of the LDROM space.

D7 D6 D5 D4 D3 D2 D1D0

1 1 0 1 1 0 1 0

0 1 1 1 10 0

B7

B0: Lock bit, logic 0: active
B1: MOVC inhibit,

logic 0: the MOVC instruction in external memory

cannot access the code in internal memory.

logic 1: no restriction.

B2: Encryption
logic 0: the encryption logic enable
logic 1: the encryption logic disable

B07: Osillator Control
logic 0: 1/2 gain
logic 1: Full gain

Default 1 for all security bits.
Reserved bits must be kept in logic 1.

0

Reserved

B2

Company ID (#DAH)

Device ID (#63H)

Security Bits

B0B1

Special Setting Registers

4KB MTP ROM

Program Memory

LDROM

Reserved

Reserved

Security Register

0000h

0FFFh

7FFFh

FFFFh

32KB MTP ROM
Program Memory

APROM

Lock bit

This bit is used to protect the customer's program code in the W78LE58. It may be set after the
programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the
MTP ROM data and Special Setting Registers can not be accessed again.

MOVC Inhibit

This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC
instruction in external program memory from reading the internal program code. When this bit is set
to logic 0, a MOVC instruction in external program memory space will be able to access code only in
the external memory, not in the internal memory. A MOVC instruction in internal program memory
space will always be able to access the ROM data in both internal and external memory. If this bit is
logic 1, there are no restrictions on the MOVC instruction.

Encryption

This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is
enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will
reset this bit.

Publication Release Date: June 2000

- 17 - Revision A1

Preliminary W78LE58

EA

EA

Oscillator Control

W78LE58/E516 allow user to diminish the gain of on-chip oscillator amplifier by using programmer to
set the bit B7 of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be
taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may
improperly affect the external crystal operation at high frequency above 24 MHz. The value of R and
C1, C2 may need some adjustment while running at lower gain.

ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL MIN. MAX. UNIT

DC Power Supply
Input Voltage V
Operating Temperature T
Storage Temperature T

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

DD

SS

−

IN

ST

V

A

V

DC CHARACTERISTICS

VSS = 0V, TA = 25° C, unless otherwise specified.

PARAMETER SYM. SPECIFICATION UNIT TEST CONDITIONS

Operating Voltage V

DD

VDD 3.3 5.5 V With ISP
Operating Current I

DD

- 3 mA No load VDD = 2.4V
Idle Current I

IDLE

- 1.5 mA VDD = 2.4V, Fosc = 12 MHz
Power Down Current I

PWDN

- 20
Input Current

I

IN1

P1, P2, P3, P4
Input Current

I

IN2

RST
Input Leakage Current

P0,
Logic 1 to 0 Transition

LK

I

ITL [*4] -500 -

Current
P1, P2, P3, P4
Input Low Voltage V

P0, P1, P2, P3, P4,
Input Low Voltage V

IL1

0 0.5 V VDD = 2.4V

IL2

RST[*1] 0 0.3 V VDD = 2.4V

MIN. MAX.

2.4 5.5 V Without ISP

- 20 mA No load VDD = 5.5V

- 6 mA VDD = 5.5V, Fosc = 20 MHz

- 50

-50 +10

-10 +300

-10 +10

0 0.8 V VDD = 4.5V

0 0.8 V VDD = 4.5V

-0.3 +6.0 V

VSS -0.3 VDD +0.3 V

0 60

-55 +150

°

C

°

C

µ
µ
µ

µ

µ

µ

VDD = 5.5V, Fosc = 20 MHz

A

VDD = 2.4V, Fosc = 12 MHz

A

VDD = 5.5V

A

IN

< V

DD

DD

DD

A

A

A

VIN = 0V or V
VDD = 5.5V
0 < VIN < V
VDD = 5.5V
0V < V

VDD = 5.5V
VIN = 2.0V

- 18 -

DC Characteristics, continued

EA

PARAMETER SYM. SPECIFICATION UNIT TEST CONDITIONS

Preliminary W78LE58

Input Low Voltage V

IL3

MIN. MAX.

0 0.8 V VDD = 4.5V

XTAL1 [*3] 0 0.4 V VDD = 2.4V

IH1

Input High Voltage V
P0, P1, P2, P3, P4,

Input High Voltage V

2.4 V

1.4 V

IH2

3.5 V

RST[*1] 1.7 V

IH3

Input High Voltage V

3.5 V

XTAL1 [*3] 2.4 V

OL1

Output Low Voltage V

- 0.45 V VDD = 4.5V, IOL = +2 mA

DD

+0.2 V VDD = 5.5V

DD

+0.2 V VDD = 2.4V

DD

+0.2 V VDD = 5.5V

DD

+0.2 V VDD = 2.4V

DD

+0.2 V VDD = 5.5V

DD

+0.2 V VDD = 2.4V

P1, P2, P3, P4 - 0.25 V VDD = 2.4V, IOL = +1 mA

OL2

Output Low Voltage V
P0, ALE,

PSEN

[*2]

Sink Current I

- 0.45 V VDD = 4.5V, IOL = +4 mA

- 0.25 V VDD = 2.4V, IOL = +2 mA

SK1

4 12 mA VDD = 4.5V, Vin = 0.45V

P1, P2, P3, P4 1.8 5.4 mA VDD = 2.4V, Vin = 0.45V

SK2

Sink Current I
P0, ALE,

PSEN
Output High Voltage V
P1, P2, P3, P4 1.4 - V
Output High Voltage V

P0, ALE, PSEN [*2]

8 16 mA VDD = 4.5V, Vin = 0.45V

4.5 9 mA VDD = 2.4V, Vin = 0.4V

OH1

2.4 - V

OH2

2.4 - V

1.4 - V

VDD = 4.5V, I
VDD = 2.4V, I
VDD = 4.5V, IOH = -400 µA
VDD = 2.4V, IOH = -200 µA

OH

= -100 µA

OH

= -8 µA

SR1

Source Current I
P1, P2, P3, P4 -20 -50
Source Current I

P0, ALE, PSEN

Notes:
*1. RST pin is a Schmitt trigger input.

*2. P0, ALE and
*3. XTAL1 is a CMOS input.

*4. Pins of P1, P2, P3, P4 can source a transition current when they are being externally driven from 1 to 0.

are tested in the external access mode.

PSEN

SR2

-100 -250

µ
µ

-8 -14 mA VDD = 4.5V, Vin = 2.4V

VDD = 4.5V, Vin = 2.4V

A

VDD = 2.4V, Vin = 1.4V

A

-1.9 -3.8 mA VDD = 2.4V, Vin = 1.4V

Publication Release Date: June 2000

- 19 - Revision A1

Preliminary W78LE58

PSEN

PSEN

PSEN

PSEN

PSEN

PSEN

AC CHARACTERISTICS

The AC specifications are a function of the particular process used to manufacture the part, the
ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the
specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will
usually experience less than a ±20 nS variation. The numbers below represent the performance
expected from a 0.6 micron CMOS process when using 2 and 4 mA output buffers.

Clock Input Waveform

XTAL1

T

CH

F

OP, TCP

T

CL

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES

Operating Speed Fop 0 - 24 MHz 1
Clock Period TCP 25 - - nS 2
Clock High Tch 10 - - nS 3
Clock Low Tcl 10 - - nS 3

Notes:

1. The clock may be stopped indefinitely in either state.

2. The TCP specification is used as a reference in other specifications.

3. There are no duty cycle requirements on the XTAL1 input.

Program Fetch Cycle

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES

AAS

Address Valid to ALE Low T
Address Hold from ALE Low T

ALE Low to

Low

Low to Data Valid
Data Hold after
Data Float after

High

High

ALE Pulse Width T

Pulse Width

Notes:

1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.

2. Memory access time is 3 TCP.

3. Data have been latched internally prior to

4. "∆" (due to buffer driving delay and wire loading) is 20 nS.

AAH
APL

T

PDA

T

PDH

T

PDZ

T

ALW
PSW

T

going high.

1 TCP­1 TCP­1 TCP-

∆
∆
∆

- - nS 4

- - nS 1, 4

- - nS 4

- - 2 T
0 - 1 T
0 - 1 T

CP

2 T

∆

2 TCP-

CP

3 T

∆

3 TCP-

CP

nS 2

CP

nS 3

CP

nS

- nS 4

- nS 4

- 20 -

Preliminary W78LE58

RD

RD

WR

Data Read Cycle

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES

DAR

ALE Low to RD Low

Low to Data Valid
Data Hold from RD High
Data Float from RD High

Pulse Width

Notes:

1. Data memory access time is 8 TCP.

2. "∆" (due to buffer driving delay and wire loading) is 20 nS.

T
T
T
T
T

DDA

DDH

DDZ

DRD

∆

3 TCP-

- - 4 T
0 - 2 T
0 - 2 T

∆

6 TCP-

Data Write Cycle

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

DAW

ALE Low to WR Low
Data Valid to WR Low
Data Hold from WR High

Pulse Width

T

T
T
T

DAD
DWD
DWR

3 TCP­1 TCP­1 TCP­6 TCP-

∆
∆
∆
∆

6 T

-

CP

-

CP+

∆

3 T

CP
CP
CP

- nS 2

3 TCP+

∆

- - nS

- - nS

CP

6 T

- nS

nS 1, 2
nS 1
nS
nS

nS

Note: "∆" (due to buffer driving delay and wire loading) is 20 nS.

Port Access Cycle

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

Port Input Setup to ALE Low T
Port Input Hold from ALE Low T
Port Output to ALE T

Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.

- 21 - Revision A1

PDS
PDH
PDA

1 TCP - - nS

0 - - nS

1 TCP - - nS

Publication Release Date: June 2000

TIMING WAVEFORMS

Program Fetch Cycle

S1

XTAL1

ALE

PSEN

PORT 2

PORT 0

Preliminary W78LE58

S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6

T

ALW

T

APL

T

PSW

T

AAS

T

A0-A7

PDA

T

PDH,TPDZ

A0-A7

DataCode

Code

A0-A7

Data

T

AAH

A0-A7

Data Read Cycle

XTAL1

ALE

PSEN

PORT 2

PORT 0

RD

A0-A7

T

DAR

A8-A15

T

DDA

T

DRD

DATA

T

DDH,TDDZ

S2 S3S5 S6 S1S2 S3 S4S5 S6 S1S4

- 22 -

Timing Waveforms, continued

Data Write Cycle

XTAL1

ALE

PSEN

Preliminary W78LE58

S2 S3S5 S6 S1S2 S3 S4S1S5 S6S4

PORT 2

PORT 0

WR

Port Access Cycle

XTAL1

ALE

PORT

INPUT

SAMPLE

A0-A7

T

A8-A15

DATA OUT

T

T

DAD

T

DAW

S5 S6 S1

T

DWR

T

PDHPDS

DWD

T

PDA

DATA OUT

Publication Release Date: June 2000

- 23 - Revision A1

TYPICAL APPLICATION CIRCUIT

Expanded External Program Memory and Crystal

V

8.2 K

DD

10 u

CRYSTAL

C1

C2

31

EA

19

XTAL1

R

18

XTAL2

9

RST

INT0

12
13

INT1

14

T0

15

T1
P1.0 1

P1.1

2

P1.2

3

P1.3

4

P1.4

5

P1.5

6

P1.6

7

P1.7

8

W78LE58

P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7

P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7

PSEN

ALE
TXD
RXD

WR

AD0

39
38

37
36
35
34

33

32

21

22

23

24

25

26

27

28

RD

17
16
29
30

11
10

AD1
AD2
AD3
AD4
AD5
AD6

AD7

A9
A10
A11
A12

A13

A14

A15

AD0D0 3
AD1
AD2
AD3
AD4
AD5
AD6
AD7

GND

A8

Preliminary W78LE58

A0
D1
D2
D3
D4
D5
D6
D7

OC
G

74LS373

Q0

5

A1

Q1

6

A2

Q2

9

A3

Q3

12

A4

Q4

15

A5

Q5

A6

16

Q6

19

Q7

A7

4
7
8
13
14
17
18

1

11

A0

2

GND

A10
A11
A12
A13
A14
A15

10

A0

A1

9

A1

A2

8

A2

A3

7

A3

A4

6

A4

A5

5

A5

A6

4

A6

3

A7

A7

25

A8

A8

24

A9

A9

21

A10

23

A11

2

A12

26

A13

27

A14

1

A15

20

CE

22

OE

27512

11

O0

12

O1

13

O2

15

O3

16

O4

17

O5

18

O6

19

O7

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7

Figure A

CRYSTAL C1 C2 R

6 MHz 47P 47P ­16 MHz 30P 30P ­24 MHz 15P 10P _

Above table shows the reference values for crystal applications.

Notes:

1. C1, C2, R components refer to Figure A

2. Crystal layout must get close to XTAL1 and XTAL2 pins on user's application board.

- 24 -

Expanded External Data Memory and Oscillator

V

DD

31

EA

19

XTAL1

18

XTAL2

9

RST

INT0

12
13

INT1

14

T0

15

T1

1

P1.0

2

P1.1

3

P1.2

4

P1.3

5

P1.4

6

P1.5

7

P1.6

8

P1.7

W78LE58

8.2 K

V

DD

OSCILLATOR

10 u

P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7

P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7

RD

WR 16

PSEN

ALE
TXD
RXD

Preliminary W78LE58

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7

A8
A9
A10
A11
A12
A13
A14

AD0

AD1

AD2
AD3
AD4
AD5
AD6

AD7
GND

3

D0

4

D1

7

D2

8

D3

13

D4

14

D5

17

D6

18

D7

1

OC

11

G

A0

2

Q0

A1

5

Q1

A2

6

Q2

A3

9

Q3

A4

12

Q4

15

A5

Q5

16

A6

Q6

A7

19

Q7

74LS373

39
38
37
36
35
34
33
32

21
22

23
24
25

26

27

28

17

29
30
11
10

A0

A10
A11
A12
A13
A14

GND

10

A0

A1

9

A2

8

A3

7

A4

6

A5

5

A6

4

A7

3

25

A8
A9

24
21
23

2

26

1

20
22
27

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14

CE
OE
WR

D0
D1
D2
D3
D4
D5
D6
D7

AD0

11

AD1

12

AD2

13

AD3

15

AD4

16

AD5

17

AD6

18

AD7

19

20256

PACKAGE DIMENSIONS

40-pin DIP

40 21

1

E

1

S

A

2

A

L

D

B

e

1

B

1

Figure B

Dimension in inch Dimension in mm

Symbol

Min. Nom. Max. Max.Nom.Min.

A

0.010

1

A

0.150

A

2

0.016

B

1

B

0.008

c
D
E

0.540

E1
e

1

0.120

L

a

0.630 16.00

A

e

20

Base Plane

1

A

Seating Plane

E

eA

a

S

Notes:

1. Dimension D Max. & S include mold flash or
tie bar burrs.

c

2. Dimension E1 does not include interlead flash.

3. Dimension D & E1 include mold mismatch and

are determined at the mold parting line.

4. Dimension B1 does not include dambar
protrusion/intrusion.

5. Controlling dimension: Inches.

6. General appearance spec. should be based on
final visual inspection spec.

0.210

0.155

0.160

0.018

0.022

0.050 1.27

0.0540.048

0.010

0.014

2.055 2.070

0.610

0.6000.590

0.545

0.550

0.110

0.130

0.140

0 15

0.670

0.650

0.090

.

0.254

3.81

0.406

0.203

14.986

13.72

2.286 2.54 2.7940.090 0.100

3.048

3.937

0.457

0.254

52.20

15.24

3.302

16.51

5.334

4.064

0.559

1.3721.219

0.356

52.58

15.494

13.9713.84

3.556

17.01

2.286

150

Publication Release Date: June 2000

- 25 - Revision A1

Package Dimensions, continued

44-pin PLCC

H

6 1

7

17

L

θ

Seating Plane

D

e

G

D

44 40

b
b

1

D

Preliminary W78LE58

Dimension in inch

Symbol

39

H

E

E

29

2818

A

2

A

A

1

y

G

E

c

Min. Nom. Max. Max.Nom.Min.

A

0.020

A

1

0.150

0.145

A

2

0.026

b1
b

c
D
E
e
G
G
H
H
L

y

Notes:

1. Dimension D & E do not include interlead
flash.

2. Dimension b1 does not include dambar

protrusion/intrusion.

3. Controlling dimension: Inches

4. General appearance spec. should be based
on final visual inspection spec.

0.028

0.016

0.018

0.008

0.010

0.648

0.653

0.653

0.648

0.050

0.590

0.610

D

0.590

E

0.680

0.690

D

0.680

E

0.100

0.090

BSC

0.185

0.155

0.032

0.022

0.014

0.658

0.658

0.630

0.6300.610

0.700

0.7000.690

0.110

0.004

Dimension in mm

0.508

3.81

3.683

0.66

0.711

0.406

0.457

0.203

0.254

16.46

16.59

16.59

16.46

1.27

BSC

14.99

15.49

17.27

17.53

2.54

2.296

4.699

3.937

0.813

0.559

0.356

16.71

16.71

16.00

16.0015.4914.99

17.78

17.7817.5317.27

2.794

0.10

44-pin PQFP

44

1

11

12

Seating Plane

H

D

D

e

See Detail F

Dimension in inch Dimension in mm

34

33

Symbol

A
A
A
b

1

2

c
D

EEH

E
e

H
H
L

1

L

22

b

c

A

A

2

A

1

y

θ

L

L

1

Detail F

y

θ

Notes:

1. Dimension D & E do not include interlead
flash.

2. Dimension b does not include dambar
protrusion/intrusion.

3. Controlling dimension: Millimeter

4. General appearance spec. should be based
on final visual inspection spec.

Nom.

Min.

0.002

0.075

0.01

0.390

0.390

0.025

0.510 13.45

D

0.510

E

0.025

0.051 0.075 1.295

0

Max. Max.

Min.

---

0.087

0.018

0.0100.004

0.398

0.3980.394

0.036

0.530

0.530

0.037

0.003
7

--- --- --- --- ---

0.05

1.90

0.25

9.9

9.9

0.635

12.95

12.95

0.65

0

0.01 0.02 0.25

0.081

0.014

0.006 0.152

0.394

0.031

0.520

0.520

0.031

0.063

Nom.

2.05

0.35

10.00

10.00

0.80

13.2

0.8

1.6

0.5

2.20

0.45

0.2540.101

10.1

10.1

0.952

13.4513.2

0.95

1.905

0.08
7

- 26 -

Preliminary W78LE58

Application Note: In-system Programming Software Examples

This application note illustrates the in-system programmability of the Winbond W78LE58 MTP-ROM
microcontroller. In this example, microcontroller will boot from 32KB APROM bank and waiting for a
key to enter in-system programming mode for re-programming the contents of 32KB APROM. While
entering in-system programming mode, microcontroller executes the loader program in 4KB LDROM
bank. The loader program erases the 32KB APROM then reads the new code data from external
SRAM buffer (or through other interfaces) to update the 32KB APROM.

EXAMPLE 1:

;*******************************************************************************************************************
;* Example of 32K APROM program: Program will scan the P1.0. if P1.0 = 0, enters in-system
;* programming mode for updating the content of APROM code else executes the current ROM code.
;* XTAL = 16 MHz
;*******************************************************************************************************************

.chip 8052
.RAMCHK OFF
.symbols

CHPCON EQU BFH
CHPENR EQU F6H
SFRAL EQU C4H
SFRAH EQU C5H
SFRFD EQU C6H
SFRCN EQU C7H

ORG 0H

LJMP 100H ; JUMP TO MAIN PROGRAM
;************************************************************************
;* TIMER0 SERVICE VECTOR ORG = 000BH
;************************************************************************
ORG 00BH

CLR TR0 ; TR0 = 0, STOP TIMER0

MOV TL0,R6

MOV TH0,R7

RETI
;************************************************************************
;* 32K APROM MAIN PROGRAM
;************************************************************************
ORG 100H

MAIN_32K:

MOV A,P1 ; SCAN P1.0

ANL A,#01H
CJNE A,#01H,PROGRAM_32K ; IF P1.0 = 0, ENTER IN-SYSTEM PROGRAMMING MODE

JMP NORMAL_MODE
PROGRAM_32K:

MOV CHPENR,#87H ; CHPENR = 87H, CHPCON REGISTER WRTE ENABLE
MOV CHPENR,#59H ; CHPENR = 59H, CHPCON REGISTER WRITE ENABLE

MOV CHPCON,#03H ; CHPCON = 03H, ENTER IN-SYSTEM PROGRAMMING MODE
MOV TCON,#00H ; TR = 0 TIMER0 STOP
MOV IP,#00H ; IP = 00H

Publication Release Date: June 2000

- 27 - Revision A1

Preliminary W78LE58

MOV IE,#82H ; TIMER0 INTERRUPT ENABLE FOR WAKE-UP FROM IDLE MODE

MOV R6,#FEH ; TL0 = FEH
MOV R7,#FFH ; TH0 = FFH

MOV TL0,R6

MOV TH0,R7
MOV TMOD,#01H ; TMOD = 01H, SET TIMER0 A 16-BIT TIMER

MOV TCON,#10H ; TCON = 10H, TR0 = 1,GO

MOV PCON,#01H ; ENTER IDLE MODE FOR LAUNCHING THE IN-SYSTEM

;********************************************************************************
;* Normal mode 32KB APROM program: depending user's application
;********************************************************************************
NORMAL_MODE:

. ; User's application program
.

.
.

EXAMPLE 2:

;*****************************************************************************************************************************
;* Example of 4 KB LDROM program: This loader program will erase the 32KB APROM first, then reads the new
;* code from external SRAM and program them into 32 KB APROM bank. XTAL = 16 MHz

;*****************************************************************************************************************************

.chip 8052
.RAMCHK OFF
.symbols

CHPCON EQU BFH
CHPENR EQU F6H
SFRAL EQU C4H
SFRAH EQU C5H
SFRFD EQU C6H
SFRCN EQU C7H

ORG 000H

LJMP 100H ; JUMP TO MAIN PROGRAM
;************************************************************************

;* 1. TIMER0 SERVICE VECTOR ORG = 0BH
;************************************************************************
ORG 000BH
CLR TR0 ; TR0 = 0, STOP TIMER0
MOV TL0,R6
MOV TH0,R7

RETI
;************************************************************************

;* 4KB LDROM MAIN PROGRAM
;************************************************************************

ORG 100H

; PROGRAMMING

- 28 -

Preliminary W78LE58

MAIN_4K:
MOV CHPENR,#87H ; CHPENR = 87H, CHPCON WRITE ENABLE.

MOV CHPENR,#59H ; CHPENR = 59H, CHPCON WRITE ENABLE.
MOV A,CHPCON

ANL A,#80H

CJNE A,#80H,UPDATE_32K ; CHECK F04KBOOT MODE ?

MOV CHPCON,#03H ; CHPCON = 03H, ENABLE IN-SYSTEM PROGRAMMING.

MOV CHPENR,#00H ; DISABLE CHPCON WRITE ATTRIBUTE

MOV TCON,#00H ; TCON = 00H, TR = 0 TIMER0 STOP

MOV TMOD,#01H ; TMOD = 01H, SET TIMER0 A 16BIT TIMER

MOV IP,#00H ; IP = 00H

MOV IE,#82H ; IE = 82H, TIMER0 INTERRUPT ENABLED

MOV R6,#FEH
MOV R7,#FFH

MOV TL0,R6
MOV TH0,R7
MOV TCON,#10H ; TCON = 10H, TR0 = 1, GO
MOV PCON,#01H ; ENTER IDLE MODE

UPDATE_32K:

MOV CHPENR,#00H ; DISABLE CHPCON WRITE-ATTRIBUTE
MOV TCON,#00H ; TCON = 00H , TR = 0 TIM0 STOP

MOV IP,#00H ; IP = 00H

MOV IE,#82H ; IE = 82H, TIMER0 INTERRUPT ENABLED
MOV TMOD,#01H ; TMOD = 01H, MODE1

MOV R6,#E0H ; SET WAKE-UP TIME FOR ERASE OPERATION, ABOUT 15 mS. DEPENDING

MOV R7,#B1H

MOV TL0,R6
MOV TH0,R7

ERASE_P_4K:

MOV SFRCN,#22H ; SFRCN(C7H) = 22H ERASE 32K
MOV TCON,#10H ; TCON = 10H, TR0 = 1,GO

MOV PCON,#01H ; ENTER IDLE MODE (FOR ERASE OPERATION)
;*********************************************************************

;* BLANK CHECK
;*********************************************************************
MOV SFRCN,#0H ; READ 32KB APROM MODE

MOV SFRAH,#0H ; START ADDRESS = 0H
MOV SFRAL,#0H
MOV R6,#FEH

MOV R7,#FFH
MOV TL0,R6

MOV TH0,R7
BLANK_CHECK_LOOP:

SETB TR0 ; ENABLE TIMER 0

MOV PCON,#01H ; ENTER IDLE MODE

MOV A,SFRFD ; READ ONE BYTE

; ON USER'S SYSTEM CLOCK RATE.

; SET TIMER FOR READ OPERATION, ABOUT 1.5 µS.

Publication Release Date: June 2000

- 29 - Revision A1

Preliminary W78LE58

CJNE A,#FFH,BLANK_CHECK_ERROR

INC SFRAL ; NEXT ADDRESS

MOV A,SFRAL
JNZ BLANK_CHECK_LOOP

INC SFRAH

MOV A,SFRAH
CJNE A,#80H,BLANK_CHECK_LOOP ; END ADDRESS = 7FFFH

JMP PROGRAM_32KROM
BLANK_CHECK_ERROR:

MOV P1,#F0H

MOV P3,#F0H
JMP $

;*******************************************************************************
;* RE-PROGRAMMING 32KB APROM BANK
;*******************************************************************************
PROGRAM_32KROM:

MOV DPTR,#0H ; THE ADDRESS OF NEW ROM CODE
MOV R2,#00H ; TARGET LOW BYTE ADDRESS

MOV R1,#00H ; TARGET HIGH BYTE ADDRESS

MOV DPTR,#0H ; EXTERNAL SRAM BUFFER ADDRESS
MOV SFRAH,R1 ; SFRAH, TARGET HIGH ADDRESS
MOV SFRCN,#21H ; SFRCN(C7H) = 21 (PROGRAM 32K)

MOV R6,#BEH ; SET TIMER FOR PROGRAMMING, ABOUT 50 µS.

MOV R7,#FFH

MOV TL0,R6

MOV TH0,R7
PROG_D_32K:

MOV SFRAL,R2 ; SFRAL(C4H) = LOW BYTE ADDRESS

MOVX A,@DPTR ; READ DATA FROM EXTERNAL SRAM BUFFER. BY ACCORDING USER?

; CIRCUIT, USER MUST MODIFY THIS INSTRUCTION TO FETCH CODE
MOV SFRFD,A ; SFRFD(C6H) = DATA IN
MOV TCON,#10H ; TCON = 10H, TR0 = 1,GO
MOV PCON,#01H ; ENTER IDLE MODE (PRORGAMMING)
INC DPTR
INC R2

CJNE R2,#0H,PROG_D_32K
INC R1

MOV SFRAH,R1

CJNE R1,#80H,PROG_D_32K

;*****************************************************************************
; * VERIFY 32KB APROM BANK
;*****************************************************************************

MOV R4,#03H ; ERROR COUNTER
MOV R6,#FEH ; SET TIMER FOR READ VERIFY, ABOUT 1.5 µS.
MOV R7,#FFH

MOV TL0,R6

MOV TH0,R7
MOV DPTR,#0H ; The start address of sample code
MOV R2,#0H ; Target low byte address
MOV R1,#0H ; Target high byte address

- 30 -

Preliminary W78LE58

Winbond Electronics North America Corp.

Winbond Electronics North America Corp.

MOV SFRAH,R1 ; SFRAH, Target high address

MOV SFRCN,#00H ; SFRCN = 00 (Read ROM CODE)

READ_VERIFY_32K:

MOV SFRAL,R2 ; SFRAL(C4H) = LOW ADDRESS
MOV TCON,#10H ; TCON = 10H, TR0 = 1,GO

MOV PCON,#01H

INC R2
MOVX A,@DPTR

INC DPTR

CJNE A,SFRFD,ERROR_32K

CJNE R2,#0H,READ_VERIFY_32K
INC R1
MOV SFRAH,R1

CJNE R1,#80H,READ_VERIFY_32K
;******************************************************************************

;* PROGRAMMING COMPLETLY, SOFTWARE RESET CPU
;******************************************************************************

MOV CHPENR,#87H ; CHPENR = 87H

MOV CHPENR,#59H ; CHPENR = 59H

MOV CHPCON,#83H ; CHPCON = 83H, SOFTWARE RESET.

ERROR_32K:

DJNZ R4,UPDATE_32K ; IF ERROR OCCURS, REPEAT 3 TIMES.

. ; IN-SYSTEM PROGRAMMING FAIL, USER'S PROCESS TO DEAL WITH IT.

.
.

.

Headquarters

Headquarters

No. 4, Creation Rd. III,

No. 4, Creation Rd. III,
Science -Based Industrial Park,

Science -Based Industrial Park,
Hsinchu, Taiwan

Hsinchu, Taiwan
TEL: [phone]

TEL: [phone]
FAX: [phone]

FAX: [phone]
http://www.winbond.com.tw/

http://www.winbond.com.tw/
Voice & Fax -on-demand: 886 -2-27197006

Voice & Fax -on-demand: 886 -2-27197006

Taipei Office

Taipei Office

11F, No. 115, Sec. 3, Min -Sheng East Rd.,

11F, No. 115, Sec. 3, Min -Sheng East Rd.,
Taipei, Taiwan

Taipei, Taiwan
TEL: [phone]

TEL: [phone]
FAX: [phone]

FAX: [phone]

Note: All data and specifications are subject to change withou t notice.

Note: All data and specifications are subject to change withou t notice.

- 31 - Revision A1

Winbond Electronics (H.K.) Ltd.

Winbond Electronics (H.K.) Ltd.

Unit 9-15, 22F, Millennium City,

Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd;

No. 378 Kwun Tong Rd;
Kowloon, Hong Kong

Kowloon, Hong Kong
TEL: [phone]

TEL: [phone]
FAX: [phone]

FAX: [phone]

Winbond Memory Lab.

Winbond Memory Lab.
Winbond Microelectronics Corp.

Winbond Microelectronics Corp.
Winbond Systems Lab.

Winbond Systems Lab.

2727 N. First Street, San Jose,

2727 N. First Street, San Jose,
CA 95134, U.S.A.

CA 95134, U.S.A.
TEL: [phone]

TEL: [phone]
FAX: [phone]

FAX: [phone]

Publication Release Date: June 2000