Datasheet W78E54B Datasheet (winbond)

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W78E54B

8-BIT MICROCONTROLLER

GENERAL DESCRIPTION

The W78E54B is an 8-bit microcontroller which can accommodate a wider frequency range with low
power consumption. The instruction set for the W78E54B is fully compatible with the standard 8051.
The W78E54B contains an 16K bytes Flash EPROM; a 256 bytes RAM; four 8-bit bi-directional and bit­addressable I/O ports; an additional 4-bit I/O port P4; three 16-bit timer/counters; a hardware watchdog
timer and a serial port. These peripherals are supported by eight sources two-level interrupt capability.
To facilitate programming and verification, the Flash EPROM inside the W78E54B allows the program
memory to be programmed and read electronically. Once the code is confirmed, the user can protect
the code for security.

The W78E54B microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.

FEATURES

• Fully static design 8-bit CMOS microcontroller

• Wide supply voltage of 4.5V to 5.5V

• 256 bytes of on-chip scratchpad RAM

• 16 KB electrically erasable/programmable Flash EPROM

• 64 KB program memory address space

• 64 KB data memory address space

• Four 8-bit bi-directional ports

• One extra 4-bit bit-addressable I/O port, additional

(available on 44-pin PLCC/QFP package)

• Three 16-bit timer/counters

• One full duplex serial port(UART)

• Watchdog Timer

• Eight sources, two-level interrupt capability

• EMI reduction mode

• Built-in power management

• Code protection mechanism

• Packages:

− DIP 40: W78E54B-24/40

− PLCC 44: W78E54BP-24/40

− PQFP 44: W78E54BF-24/40

INT2 / INT3

Publication Release Date: December 2000

- 1 - Revision A3

PIN CONFIGURATIONS

40-Pin DIP (W78E54B)

T2, P1.0

T2EX, P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

RST

RXD, P3.0
TXD, P3.1

INT0, P3.2

INT1, P3.3

T0, P3.4
T1, P3.5

WR, P3.6

RD, P3.7

XTAL2
XTAL1

VSS

W78E54B

VDD1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

40

39

P0.0, AD0

38

P0.1, AD1

37

P0.2, AD2

36

P0.3, AD3

35

P0.4, AD4

P0.5, AD5

34

33

P0.6, AD6

P0.7, AD7

32

31

EA
ALE

30

29

PSEN
P2.7, A15

28

27

P2.6, A14

26

P2.5, A13

25

P2.4, A12

24

P2.3, A11

P2.2, A10

23

22

P2.1, A9

P2.0, A8

21

44-Pin PLCC (W78E54BP)

/

T

I

2

N

T

E

T

2

X

3

,

,

,

P

P

P

P

P1.5

P1.6

P1.7

RST
RXD, P3.0
INT2, P4.3
TXD, P3.1

INT0, P3.2

INT1, P3.3

T0, P3.4

T1, P3.5

P

1

1

.

.

3

4

6543

7

8

9

10

11

12

13

14

15

16
17

P

P

3

3

.

.

7

6

,

,

/

/

R

W

D

R

1

1

.

.

1

2

X

X

T

T

A

A

L

L

1

2

P

1

4

.

.

0

2

2 1 44 43 42

V

P

S

4

S

.
0

44-Pin QFP (W78E54BF)

/

T

I

2

A

A

A

A

D

D

D

D

3

2

1

0

,

,

,

,

P

P

P

P
V
D
D

P
2
.
0
,
A
8

0

0

0

0

.

.

.

.

3

2

1

0

40

41

P

P

P

2

2

2

.

.

.

3

1

2

,

,

,

A

A

A

1

9

1

1

0

P0.4, AD4

39
38

P0.5, AD5

37

P0.6, AD6

36

P0.7, AD7

35

EA

34

P4.1

33

ALE

32

PSEN

31

P2.7, A15

30

P2.6, A14

29

P2.5, A13

2827262524232221201918

P
2
.
4
,
A
1
2

P1.5

P1.6

P1.7
RST

RXD, P3.0

INT2, P4.3

TXD, P3.1

INT0, P3.2

INT1, P3.3

T0, P3.4
T1, P3.5

1
2

3

4
5

6
7
8
9

10

11

P
1
.
4

12

P
3
.
6
,
/
W
R

P
1
.
3

43 42 41

P
3
.
7
,
/
R
D

E
X
,
P

P

1

1

.

.

1

2

X

X

T

T

A

A

L

L

1

2

N

T

T

2

3

,

,

P

P

1

V

4

.

D

.

0

D

2

403938 37 36

V

P

P

S

2

4

S

.

.

0

0

,
A
8

A

A

A

A

D

D

D

D

3

2

1

0

,

,

,

,

P

P

P

P

0

0

0

0

.

.

.

.

3

2

1

0

34

3544

P

P

P

2

2

2

.

.

.

3

2

1

,

,

,

A

A

A

1

1

9

1

0

P0.4, AD4

33
32

P0.5, AD5

31

P0.6, AD6

30

P0.7, AD7

29

EA

28

P4.1

27

ALE

26

PSEN

25

P2.7, A15

24

P2.6, A14

23

P2.5, A13

22212019181716151413

P
2
.
4
,
A
1
2

- 2 -

PIN DESCRIPTION

SYMBOL DESCRIPTIONS

EA

PSEN

ALE

RST

XTAL1

XTAL2

VSS

VDD

P0.0−P0.7

P1.0−P1.7

P2.0−P2.7

P3.0−P3.7

P4.0−P4.3

EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of
external ROM. It should be kept high to access internal ROM. The ROM address and

data will not be presented on the bus if
on-chip ROM area.

PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the Port 0
address/ data bus during fetch and MOVC operations. When internal ROM access is

performed, no

ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates
the address from the data on Port 0.

RESET: A high on this pin for two machine cycles while the oscillator is running resets
the device.

CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an external
clock.

CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.

GROUND: Ground potential

POWER SUPPLY: Supply voltage for operation.

PORT 0: Port 0 is a bi-directional I/O port which also provides a multiplexed low order

address/data bus during accesses to external memory. The Port 0 is also an open-drain
port and external pull-ups need to be connected while in programming.

PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have alternate
functions which are described below:

T2(P1.0): Timer/Counter 2 external count input
T2EX(P1.1): Timer/Counter 2 Reload/Capture control

PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.

PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. All bits have alternate
functions, which are described below:
RXD(P3.0) : Serial Port receiver input
TXD(P3.1) : Serial Port transmitter output

INT0 (P3.2) : External Interrupt 0

INT1(P3.3) : External Interrupt 1
T0(P3.4) : Timer 0 External Input
T1(P3.5) : Timer 1 External Input

WR (P3.6) :External Data Memory Write Strobe

RD (P3.7) : External Data Memory Read Strobe

PORT 4: Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative
function pins. It can be used as general I/O port or external interrupt input sources

INT2 /INT3 ).

(

PSEN strobe signal outputs from this pin.

EA pin is high and the program counter is within

W78E54B

Publication Release Date: December 2000

- 3 - Revision A3

BLOCK DIAGRAM

W78E54B

P1.0

~

P1.7

P3.0
~
P3.7

P4.0
~
P4.3

INT2

INT3

Port

1

Port

Port

Port 1
Latch

ACC

Interrupt

PSW

Instruction

Decoder

&

Sequencer

Bus & Clock

Controller

T1

ALU

Timer

2

Timer

0

Timer

1

UART

3

4

Port 3

Latch

Port 4

Latch

Oscillator

T2

SFR RAM

Address

256 bytes

RAM & SFR

ROM

Watchdog

Timer

Reset Block

B

Stack

Pointer

Power control

Port 0
Latch

DPTR

Temp Reg.

PC

Incrementor

Addr. Reg.

Port 2

Latch

Port

Port

2

P0.0

0

~
P0.7

P2.0
~
P2.7

XTAL1

XTAL2

PSENALE

RST

Vcc

Vss

FUNCTIONAL DESCRIPTION

The W78E54B architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports
111 different opcodes and references both a 64K program address space and a 64K data storage
space.

Timers 0, 1, and 2

Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0 and 1. The T2CON register provides control functions for Timer 2.
RCAP2H and RCAP2L are used as reload/capture registers for Timer 2.

- 4 -

W78E54B

The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a special feature of
the W78E54B: it is a 16-bit timer/counter that is configured and controlled by the T2CON register. Like
Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer,
depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto­reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that
of Timers 0 and 1.

New Defined Peripheral

In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt

INT2 , INT3 has been added to either the PLCC or QFP 44-pin package. And description follows:

1.

Two additional external interrupts,
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are determined/shown
by the bits in the XICON (External Interrupt Control) register. The XICON register is bit-addressable
but is not a standard register in the standard 80C52. Its address is at 0C0H. To set/clear bits in the
XICON register, one can use the "SETB (/CLR) bit" instruction. For example, "SETB 0C2H" sets the
EX2 bit of XICON.

XICON - external interrupt control (C0H)

PX3: External interrupt 3 priority high if set
EX3: External interrupt 3 enable if set
IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software

Eight-source interrupt informations:

INTERRUPT SOURCE VECTOR

External Interrupt 0 03H 0 (highest) IE.0 TCON.0
Timer/Counter 0 0BH 1 IE.1 ­External Interrupt 1 13H 2 IE.2 TCON.2
Timer/Counter 1 1BH 3 IE.3 ­Serial Port 23H 4 IE.4 ­Timer/Counter 2 2BH 5 IE.5 ­External Interrupt 2 33H 6 XICON.2 XICON.0
External Interrupt 3 3BH 7 (lowest) XICON.6 XICON.3

INT3

/

INT2

INT2 and INT3 , whose functions are similar to those of external

PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2

ADDRESS

POLLING

SEQUENCE WITHIN

PRIORITY LEVEL

ENABLE

REQUIRED

SETTINGS

INTERRUPT

TYPE

EDGE/LEVEL

Publication Release Date: December 2000

- 5 - Revision A3

W78E54B

2. PORT4

Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port
address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are

alternative function pins. It can be used as general I/O pins or external interrupt input sources (

INT3 ).

Example:
P4 REG 0D8H

MOV P4, #0AH ; Output data "A" through P4.0−P4.3.

MOV A, P4 ; Read P4 status to Accumulator.
SETB P4.0 ; Set bit P4.0
CLR P4.1 ; Clear bit P4.1

3. Reduce EMI Emission

Because of on-chip Flash EPROM, when a program is running in internal ROM space, the ALE will be
unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it
is useless. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR, which
is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses external
ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off again after it
has been completely accessed or the program returns to internal ROM code space. The AO bit in the
AUXR register, when set, disables the ALE output. In order to reduce EMI emission from oscillation
circuitry, W78E54B allows user to diminish the gain of on-chip oscillator amplifiers by using
programmer to clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be decreased.
Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain
may affect the external crystal operating improperly at high frequency above 24 MHz. The value of R
and C1, C2 may need some adjustment while running at lower gain.

INT2

,

***AUXR - Auxiliary register (8EH)

- - - - - - - AO

AO: Turn off ALE output.

4. Power-off Flag

***PCON - Power control (87H)

- -

POF: Power off flag. Bit is set by hardware when power on reset. It can be cleared by software
to determine chip reset is a warm boot or cold boot.

GF1, GF0: These two bits are general-purpose flag bits for the user.

PD: Power down mode bit. Set it to enter power down mode.

IDL: Idle mode bit. Set it to enter idle mode.

The power-off flag is located at PCON.4. This bit is set when V
be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software.

-

POF

GF1 GF0 PD IDL

DD has been applied to the part. It can

- 6 -

W78E54B

Watchdog Timer

The Watchdog timer is a free-running timer which can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the
system clock. The divider output is selectable and determines the time-out interval. When the time-out
occurs, a system reset can also be caused if it is enabled. The main use of the Watchdog timer is as a
system monitor. This is important in real-time control applications. In case of power glitches or electro­magnetic interference, the processor may begin to execute errant code. If this is left unchecked the
entire system may crash. The watchdog time-out selection will result in different time-out values
depending on the clock speed. The Watchdog timer will be disabled on reset. In general, software
should restart the Watchdog timer to put it into a known state. The control bits that support the
Watchdog timer are discussed below.

Watchdog Timer Control Register

Bit: 7 6 5 4 3 2 1 0

ENW CLRW WIDL - - PS2 PS1 PS0

Mnemonic: WDTC Address: 8FH

ENW : Enable watch-dog if set.
CLRW : Clear watch-dog timer and prescaler if set. This flag will be cleared automatically
WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled
under IDLE mode. Default is cleared.

PS2, PS1, PS0: Watch-dog prescaler timer select. Prescaler is selected when set PS2~0 as follows:

PS2 PS1 PS0 PRESCALER SELECT

0 0 0 2
0 1 0 4
0 0 1 8
0 1 1 16
1 0 0 32
1 0 1 64
1 1 0 128
1 1 1 256

The time-out period is obtained using the following equation:

1

14

×× × ×

OSC

Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6
(CLRW). After 1 is written to this bit, the 14-bit timer, prescaler and this bit will be reset on the next
instruction cycle. The Watchdog timer is cleared on reset.

2 PRESCALER 1000 12 mS

- 7 - Revision A3

Publication Release Date: December 2000

W78E54B

WIDL

IDLE

OSC 1/12

Watchdog Timer Block Diagram

ENW

PRESCALER

CLRW

Typical Watch-Dog time-out period when OSC = 20 MHz

PS2 PS1 PS0 WATCHDOG TIME-OUT PERIOD

0 0 0 19.66 mS
0 1 0 39.32 mS
0 0 1 78.64 mS
0 1 1 157.28 mS
1 0 0 314.57 mS
1 0 1 629.14 mS
1 1 0 1.25 S
1 1 1 2.50 S

EXTERNAL

RESET

14-BIT TIMER

CLEAR

INTERNAL

RESET

Clock

The W78E54B is designed to be used with either a crystal oscillator or an external clock. Internally, the
clock is divided by two before it is used. This makes the W78E54B relatively insensitive to duty cycle
variations in the clock. The W78E54B incorporates a built-in crystal oscillator. To make the oscillator
work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must
be connected from each pin to ground. An external clock source should be connected to pin XTAL1.
Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as required by the
crystal oscillator.

Power Management

Idle Mode

The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.

Power-down Mode

When the PD bit of the PCON register is set, the processor enters the power-down mode. In this mode
all of the clocks are stopped, including the oscillator. The only way to exit power-down mode is by a
reset.

- 8 -

W78E54B

Reset

The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the W78E54B is used with an external RC network. The reset logic also
has a special glitch removal circuit that ignores glitches on the reset line.

During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit

4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.

ON-CHIP FLASH EPROM CHARACTERISTICS

The W78E54B has several modes to program the on-chip Flash EPROM. All these operations are
configured by the pins RST, ALE,
OECTRL(P3.3),

P1.7−P1.0) and the D7−D0(P0.7−P0.0) serve as the address and data bus respectively for these

operations.

CE (P3.6), OE (P3.7), A0(P1.0) and VPP( EA ). Moreover, the A15−A0(P2.7−P2.0,

Read Operation

This operation is supported for customer to read their code and the Security bits. The data will not be
valid if the Lock bit is programmed to low.

Output Disable Condition

PSEN , A9CTRL(P3.0), A13CTRL(P3.1), A14CTRL(P3.2),

When the

OE is set to high, no data output appears on the D7..D0.

Program Operation

This operation is used to program the data to Flash EPROM and the security bits. Program operation
is done when the Vpp is reach to Vcp (12.5V) level,

CE set to low, and OE set to high.

Program Verify Operation

All the programming data must be checked after program operations. This operation should be
performed after each byte is programmed; it will ensure a substantial program margin.

Erase Operation

An erase operation is the only way to change data from 0 to 1. This operation will erase all the Flash
EPROM cells and the security bits from 0 to 1. This erase operation is done when the Vpp is reach to

Vep level,

CE set to low, and OE set to high.

Erase Verify Operation

After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to 1 or not. The erase verify operation automatically ensures a substantial erase

margin. This operation will be done after the erase operation if Vpp = Vep (14.5V),
is low.

CE is high and OE

Program/Erase Inhibit Operation

This operation allows parallel erasing or programming of multiple chips with different data. When

CE ) = VIH, P3.7( OE ) = VIH, erasing or programming of non-targeted chips is inhibited. So,

P3.6(
except for the P3.6 and P3.7 pins, the individual chips may have common inputs.

Publication Release Date: December 2000

- 9 - Revision A3

W78E54B

OPERATIONS P3.0

(A9

CTRL)

P3.1

(A13

CTRL)

P3.2

(A14

CTRL)

P3.3

(OE

CTRL)

P3.6

CE )

(

P3.7

( OE )

(V

EA

PP)

P2, P1

(A15..A0)

P0

(D7..D0)

Read 0 0 0 0 0 0 1 Address Data Out

Output Disable 0 0 0 0 0 1 1 X Hi-Z

Program 0 0 0 0 0 1 VCP Address Data In

Program Verify 0 0 0 0 1 0 VCP Address Data Out

Erase 1 0 0 0 0 1 VEP A0:0,

others: X

Data In

0FFH

Erase Verify 1 0 0 0 1 0 VEP Address Data Out

Program/Erase
Inhibit

Notes:

1. All these operations happen in RST = V

2. V

CP = 12.5V, VEP = 14.5V, VIH = VDD, VIL = Vss.

3. The program verify operation follows behind the program operation.

4. This erase operation will erase all the on-chip Flash EPROM cells and the Security bits.

5. The erase verify operation follows behind the erase operation.

X 0 0 0 1 1 VCP/

EP

V

IH, ALE = VIL and PSEN = VIH.

X X

NOTE

@3

@4

@5

SECURITY BITS

During the on-chip Flash EPROM operation mode, the Flash EPROM can be programmed and verified
repeatedly. Until the code inside the Flash EPROM is confirmed OK, the code can be protected. The
protection of Flash EPROM and those operations on it are described below.

The W78E54B has a Security Register which can not be accessed in normal mode. These registers
can only be accessed from the Flash EPROM operation mode. Those bits of the Security Register can
not be changed once they have been programmed from high to low. They can only be reset through
erase-all operation. The Security Register is addressed in the Flash EPROM operation mode by
address #0FFFFh.

- 10 -

W78E54B

0000h

3FFFh

0FFFFh

B0B1

Reserved

B7

B0 : Lock bit, logic 0 : active

B1 : MOVC inhibit,
logic 0 : the MOVC instruction in external memory
cannot access the code in internal memory.
logic 1 : no restriction.

B2 : Encryption
logic 0 : the encryption logic enable
logic 1 : the encryption logic disable

B7 : Osillator Control

logic 0 : 1/2 gain
logic 1 : Full gain
Default 1 for all security bits.

B2

Security Bits

Reserved bits must be kept in logic 1.

Special Setting Register

16KB On-chip ROM

Program Memory

Reserved

Security Register

Lock bit

This bit is used to protect the customer's program code in the W78E54B. It may be set after the
programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the
Flash EPROM data and Special Setting Register can not be accessed again.

MOVC Inhibit

This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC
instruction in external program memory from reading the internal program code. When this bit is set to
logic 0, a MOVC instruction in external program memory space will be able to access code only in the
external memory, not in the internal memory. A MOVC instruction in internal program memory space
will always be able to access the ROM data in both internal and external memory. If this bit is logic 1,
there are no restrictions on the MOVC instruction.

Encryption

This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is
enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will
reset this bit.

Publication Release Date: December 2000

- 11 - Revision A3

W78E54B

A0 to A7

V

IL

V

IL

V

IL

V

IL

V

IL

V

IH

Programming Configuration

P1

P3.0

P3.1

P3.2

P3.3

P3.6

P3.7

X'tal1

X'tal2

Vss

EA/Vpp

PSEN

+5V

V

DD

P0

ALE

RST

P2

PGM DATA

V

CP

V

IL

V

IH

V

IH

A8 to A15

A0 to A7

P1

V

IL

V

IL

V

IL

V

IL

V

IH

V

IL

P3.0

P3.1

P3.2

P3.3

P3.6

P3.7

X'tal1

X'tal2

Vss

EA/Vpp

Programming Verification

RST

PSEN

+5V

V

DD

P0

ALE

P2

PGM DATA

V

CP

V

IL

V

IH

V

IH

A8 to A15

ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL MIN. MAX. UNIT

DC Power Supply

DD−VSS

V

Input Voltage VIN VSS -0.3 VDD +0.3 V

Operating Temperature TA 0 70

Storage Temperature TST -55 +150

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.

-0.3 +7.0 V

°C
°C

DC CHARACTERISTICS

VCC−VSS = 5V ±10%, TA = 25° C, unless otherwise specified.

PARAMETER SYMBOL TEST CONDITIONS SPECIFICATION UNIT

Operating Voltage VDD

-

Operating Current IDD No load, VDD = 5.5V,

RST = 1

Idle Current IIDLE Idle mode VDD = 5.5V - 6 mA

Power Down Current IPWDN Power-down mode

V

DD = 5.5V

Input Current

P1, P2, P3, P4

Logical 1-to-0 Transition

Current P1, P2, P3

(*1)

, P4

Input Current

(*2)

RST

IIN1 VDD = 5.5V

V

IN

= 0V or V

TL VDD = 5.5V

I

V

IN = 2.0V

IN2 VDD = 5.5V

I

V

IN

DD

= V

(*1)

DD

- 12 -

MIN. MAX.

4.5 5.5 V

- 20 mA

- 50

-50 +10

-550 -

-10 +300

µA

µA

µA

µA

W78E54B

DC Characteristics, continued

PARAMETER SYMBOL TEST CONDITIONS SPECIFICATION UNIT

Input Leakage Current

P0,

EA
Output Low Voltage
P1, P2, P3, P4
Output Low Voltage

ALE,

PSEN , P0

(*3)

Output High Voltage
P1, P2, P3, P4

Output High Voltage

(*3)

ALE,

PSEN

, P0

Input Low Voltage

LK VDD = 5.5V

I

IN < VDD

0V < V

VOL1 VDD = 4.5V

I

OL1

= +2 mA

V

OL2 VDD = 4.5V

OL2

= +4 mA

I

VOH1 VDD = 4.5V

I

OH1 = -100 µA

V

OH2 VDD

I

OH2

= 4.5V

= -400 µA

VIL1 VDD = 4.5V 0 0.8 V
(Except RST)
Input Low Voltage

(*4)

RST
Input Low Voltage

XTAL1

(*4)

Input High Voltage

IL2 VDD = 4.5V 0 0.8 V

V

IL3 VDD = 4.5V 0 0.8 V

V

VIH1 VDD = 4.5V 2.4 VDD +0.2 V
(Except RST)
Sink Current
P1, P2, P3, P4
Input High Voltage

(*4)

RST
Input High Voltage

(*4)

XTAL1
Sink Current

P0, ALE,

PSEN

(*3)

Source Current
P1, P2, P3, P4
Source Current

P0, ALE,

Notes:
*1. Pins P1, P2 and P3 source a transition current when they are being externally driven from 1 to 0. The transition current

reaches its maximum value when V
*2. RST pin has an internal pull-down resistor.

*3. P0, ALE,
*4. XTAL1 is a CMOS input and RST is a Schmitt trigger input.

PSEN

PSEN are in the external access memory mode.

(*3)

ISK1 VDD = 4.5V

Vs = 0.45V

V

IH2 VDD

V

IH3 VDD = 4.5V 0.67 VDD VDD +0.2 V

I

SK2 VDD = 4.5V

Vs = 0.45V

ISR1 VDD = 4.5V

Vs

I

SR2 VDD = 4.5V

Vs

IN is approximately 2V.

= 4.5V 0.67 V

= 2.4V

= 2.4V

MIN. MAX.

-10 +10

µA

- 0.45 V

- 0.45 V

2.4 - V

2.4 - V

4 12 mA

DD VDD +0.2 V

8 16 mA

-100 -250 uA

-8 -14 mA

Publication Release Date: December 2000

- 13 - Revision A3

W78E54B

AC CHARACTERISTICS

The AC specifications are a function of the particular process used to manufacture the part, the ratings
of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications
can be expressed in terms of multiple input clock periods (T

experience less than a ±20 nS variation. The numbers below represent the performance expected

from a 0.6micron CMOS process when using 2 and 4 mA output buffers.

Clock Input Waveform

CP), and actual parts will usually

XTAL1

T

CH

F

OP,

T

CL

T

CP

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES

Operating Speed FOP 0 - 40 MHz 1
Clock Period TCP 25 - - nS 2
Clock High TCH 10 - - nS 3
Clock Low TCL 10 - - nS 3

Notes:

1. The clock may be stopped indefinitely in either state.

CP specification is used as a reference in other specifications.

2. The T

3. There are no duty cycle requirements on the XTAL1 input.

Program Fetch Cycle

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES

Address Valid to ALE Low TAAS

Address Hold from ALE Low TAAH

APL

ALE Low to

PSEN

PSEN

Low

Low to Data Valid

Data Hold after PSEN High

PSEN

Data Float after

High

T

PDA - - 2 TCP nS 2

T

PDH 0 - 1 TCP nS 3

T

T

PDZ 0 - 1 TCP nS

ALE Pulse Width TALW

PSW

PSEN Pulse Width

Notes:

1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.

2. Memory access time is 3 T

3. Data have been latched internally prior to

4. "∆" (due to buffer driving delay and wire loading) is 20 nS.

CP.

T

PSEN going high.

1 T

1 T

1 T

2 T

3 T

CP -∆
CP -∆
CP -∆

CP -∆
CP -∆

- - nS 4

- - nS 1, 4

- - nS 4

2 T

CP - nS 4

3 T

CP - nS 4

- 14 -

W78E54B

RD

RD

Data Read Cycle

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES

6 T

-

CP

3 TCP +∆

- nS 2

DAR

ALE Low to RD Low

Low to Data Valid

RD

Data Hold from

High

Data Float from RD High

Pulse Width

Notes:

1. Data memory access time is 8 T

2. "∆" (due to buffer driving delay and wire loading) is 20 nS.

CP.

T

DDA - - 4 TCP nS 1

T

T

DDH 0 - 2 TCP nS

DDZ 0 - 2 TCP nS

T

DRD

T

3 T

6 T

CP -∆

CP -∆

Data Write Cycle

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

ALE Low to WR Low

Data Valid to WR Low

Data Hold from WR High

WR

Pulse Width

DAW

T

DAD

T

DWD

T

T

DWR

3 T

1 T

1 T

6 T

CP -∆
CP -∆
CP -∆
CP -∆

-

3 T

CP +∆

- - nS

- - nS

6 T

CP

- nS

nS 1, 2

nS

Note: "∆" (due to buffer driving delay and wire loading) is 20 nS.

Port Access Cycle

Port Input Setup to ALE Low TPDS 1 TCP - - nS

Port Input Hold from ALE Low TPDH 0 - - nS

Port Output to ALE TPDA 1 TCP - - nS

Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

Program Operation

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

VPP Setup Time TVPS 2.0 - -

Data Setup Time TDS 2.0 - -

Data Hold Time TDH 2.0 - -

Address Setup Time TAS 2.0 - -

Address Hold Time TAH 0 - -

µS
µS
µS
µS
µS

Publication Release Date: December 2000

- 15 - Revision A3

W78E54B

Program Operation, continued

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

PWP 290 300 310

CE Program Pulse Width for

T

Program Operation

OECTRL Setup Time TOCS 2.0 - -

OECTRL Hold Time TOCH 2.0 - -

T

OE Setup Time

OE High to Output Float

Data Valid from

Note: Flash data can be accessed only in flash mode. The RST pin must pull in VIH status, the ALE pin must pull in VIL status,

and the

PSEN pin must pull in VIH status.

OE

OES 2.0 - -

T

DFP 0 - 130 nS

OEV - - 150 nS

T

TIMING WAVEFORMS

µS

µS
µS
µS

Program Fetch Cycle

XTAL1

ALE

PSEN

PORT 2

PORT 0

Code

S1

S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6

T

ALW

T

APL

T

PSW

T

AAS

T

A0-A7

PDA

Data

T

PDH,TPDZ

A0-A7

Code

A0-A7

Data

T

AAH

A0-A7

- 16 -

Timing Waveforms, continued

Data Read Cycle

XTAL1

ALE

PSEN

W78E54B

S2 S3S5 S6 S1S2 S3 S4S5 S6 S1S4

PORT 2

PORT 0

RD

Data Write Cycle

XTAL1

ALE

PSEN

PORT 2

A0-A7

A8-A15

DATA

A8-A15

T

DDA

T

DRD

T

DDH,TDDZ

S2 S3S5 S6 S1S2 S3 S4S1S5 S6S4

T

DAR

PORT 0

WR

A0-A7

T

DAW

T

DAD

DATA OUT

T

DWR

T

DWD

Publication Release Date: December 2000

- 17 - Revision A3

Timing Waveforms, continued

Port Access Cycle

XTAL1

ALE

W78E54B

S5 S6 S1

T

T

PDHPDS

T

PDA

PORT

INPUT

SAMPLE

Program Operation

P2, P1

(A15... A0)

P3.6

(CE)

P3.3

(OECTRL)

P3.7

(OE)

P0

(A7... A0)

Vpp

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

Vcp

V

IH

DATA OUT

Program Program

Verify

Address Stable

T

AS

T

PWP

T

OCH

AH

T

DFP

OUT

D

T

OEV

T

OCS

T

T

OES

T

DH

Data In Data Out

T

DS

T

VPS

Read Verify

Address Valid

- 18 -

TYPICAL APPLICATION CIRCUITS

Expanded External Program Memory and Crystal

V

DD

V

8.2 K

DD

10 u

C1

CRYSTAL

C2

R

18

9

12
13

14
15

8

31

19

1
2
3
4
5
6
7

EA

XTAL1

XTAL2

RST

INT0

INT1
T0
T1

P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7

W78E54B

P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7

P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7

RD
WR

PSEN

ALE
TXD
RXD

AD0

39

38

37
36
35

34
33
32

21
22
23
24
25
26
27
28

17
16
29
30
11
10

AD1
AD2
AD3
AD4
AD5
AD6
AD7

A8
A9
A10
A11
A12

A13
A14
A15

AD0
AD1
AD2

AD3
AD4
AD5
AD6
AD7

GND

3
4
7
8
13
14
17
18

11

1

D0
D1
D2
D3
D4
D5
D6
D7

OC
G

74373

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

W78E54B

11

A0
A1
A2
A3
A4
A5
A6
A7

A0
A1
A2
A3
A4
A5
A6
A7
A8

A9
A10
A11
A12
A13
A14
A15

GND

10

9
8
7
6
5
4

3
25
24
21
23
2
26
27

1

20
22

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15

CE

OE

27512

O0
O1
O2
O3
O4
O5
O6
O7

2
5
6
9
12
15
16
19

AD0

12

AD1

13

AD2

15

AD3

16

AD4

17

AD5

18

AD6

19

AD7

Figure A

CRYSTAL C1 C2 R

16 MHz 30P 30P -

24 MHz 15P 15P -

33 MHz 10P 10P 6.8K

40 MHz 5P 5P 4.7K

Above table shows the reference values for crystal applications (full gain).

Note: C1, C2, R components refer to Figure A.

Publication Release Date: December 2000

- 19 - Revision A3

Typical Application Circuits, continued

Expanded External Data Memory and Oscillator

V

DD

V

8.2 K

DD

10 u

OSCILLATOR

31

19

18

9

12
13
14
15

1
2
3
4
5
6
7
8

EA

XTAL1

XTAL2

RST

INT0

INT1
T0
T1

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

W78E54B

P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7

P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6

P2.7

RD

WR

PSEN

ALE
TXD
RXD

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7

A8
A9

A10
A11
A12
A13
A14

AD0
AD1
AD2
AD3
AD4
AD5
AD6

AD7

GND

39
38
37
36
35
34
33
32

21

22

23

24

25

26

27

28

17

16
29
30
11
10

3
4
7
8
13
14
17
18

11

W78E54B

10

A0

A0

2

D0

Q0

A1

A1

5

D1

Q1

D2

Q2

D3

Q3

D4

Q4

D5

Q5

D6

Q6

D7

1

Q7

OC
G

74373

A2

A2

6

A3

9

A3

A4

12

A4

15

A5

A5
A6

16

A6

19

A7

A7
A8
A9
A10
A11
A12
A13
A14

GND

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

A10
A11
A12
A13
A14

CE
OE

WR

20256

D0
D1
D2
D3
D4
D5
D6
D7

9
8
7
6
5
4

3
25
24
21
23

2
26

1

20
22
27

AD0

11

AD1

12

AD2

13

AD3

15

AD4

16

AD5

17

AD6

18

AD7

19

Figure B

- 20 -

PACKAGE DIMENSIONS

40-pin DIP

40

1

E

1

S

A

A

L

D

B

e

B

1

W78E54B

Dimension in inch Dimension in mm

Symbol

A
A
A
B
B
c

21

20

Base Plane

1

A

Seating Plane

E

a

A

e

D
E
E
e
L

a

e
S

Notes:

1. Dimension D Max. & S include mold flash or
tie bar burrs.

c

2. Dimension E1 does not include interlead flash.

3. Dimension D & E1 include mold mismatch and
are determined at the mold parting line.

4. Dimension B1 does not include dambar
protrusion/intrusion.

5. Controlling dimension: Inches.

6. General appearance spec. should be based on
final visual inspection spec.

Nom.

Min.

0.010

1

0.155

0.150

2

0.016

0.018

0.050 1.27

1

0.010

0.008

2.055 2.070

0.6000.590

0.540

0.545

1

1

0.120

0.130

015

0.630 16.00

0.650

A

Nom.

Max. Max.

0.210

0.160

0.022

0.0540.048

0.014

0.610

0.550

0.110

0.140

0.670

0.090

.

Min.

0.254

3.81

0.406

0.203

14.986

13.72

2.286 2.54 2.7940.090 0.100

3.048

3.937

0.457

0.254

52.20

15.24

13.84

3.302

16.51

5.334

4.064

0.559

1.3721.219

0.356

52.58

15.494

13.97

3.556

150

17.01

2.286

44-pin PLCC

7

17

L

θ

Seating Plane

H

D

D

e

44 40

G

D

b

1b

61

Dimension in inch Dimension in mm

Symbol

39

H

E

E

29

2818

2

A

A

1

A

y

E

G

c

A
A
A
b
b
c
D

E

e
G
G
H
H

L

y

Notes:

1. Dimension D & E do not include interlead
flash.

2. Dimension b1 does not include dambar
protrusion/intrusion.

3. Controlling dimension: Inches

4. General appearance spec. should be based
on final visual inspection spec.

Nom.

Min.

0.050

0.150

0.028

0.018

0.010

0.653

0.653

0.610

0.690

0.690

0.100

BSC

0.185

0.155

0.032

0.022

0.014

0.658

0.658

0.630

0.6300.610

0.700

0.700

0.110

0.004

0.020

1

0.145

2

0.026

1

0.016

0.008

0.648

0.648

0.590

D

0.590

E

0.680

D

0.680

E

0.090

Nom.

Max. Max.

Min.

0.66

1.27

3.81

0.711

0.457

0.254

16.59

16.59

15.49

15.4914.99

17.53

2.54

BSC

4.699

3.937

0.813

0.559

0.356

16.71

16.71

16.00

16.00

17.78

17.7817.53

2.794

0.10

0.508

3.683

0.406

0.203

16.46

16.46

14.99

17.27

17.27

2.296

Publication Release Date: December 2000

- 21 - Revision A3